KR20050009482A - Method of manufacturing a semiconductor device - Google Patents

Abstract

PURPOSE: A method of fabricating a semiconductor device is provided to form simultaneously triple gate insulating layers having different thickness by performing a nitrogen ion implantation process and a fluorine ion implantation process. CONSTITUTION: A semiconductor substrate(110) including a first region(A) having a first thickness, a second region(B) having a second thickness thinner than the first thickness, and a third region(C) having a third thickness thinner than the second thickness is provided. A nitrogen ion layer is formed on the third region by performing a nitrogen ion implantation process. A fluorine ion layer is formed on the first region by performing a fluorine ion implantation process. First, second, and third gate oxide layers(130a,130b,130c) are formed on the first, second, third regions, respectively by a thermal oxidation process. A conductive layer is formed on the entire surface of the semiconductor substrate. First, second, and third gate electrodes are formed on the first, second, and third regions, respectively by a patterning process.

Description

Method of manufacturing a semiconductor device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a triple gate oxide film having different thicknesses.

In general logic devices, gate oxide films having various thicknesses are required to use various threshold voltages (Multiple Vt).

1A to 1E are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.

Referring to FIG. 1A, a first region A in which a first gate insulating layer having a first thickness is to be formed, a second region B in which a second gate insulating layer having a second thickness thinner than the first thickness is formed, and The device isolation layer 12 and the well 14 are formed in the semiconductor substrate 10 in which the third region C in which the third gate insulating layer having the third thickness thinner than the second thickness is formed is defined.

Referring to FIG. 1B, a first oxide film 16 having a predetermined thickness is formed on the entire structure. The patterning process using the photosensitive film is performed to remove the first oxide film 16 formed on the second and third regions B and C.

Referring to FIG. 1C, a second oxide film 20 having a predetermined thickness is formed on the entire structure. The patterning process using the photosensitive film is performed to remove the second oxide film 20 formed on the third region (C).

Referring to FIG. 1D, a first gate in which a third oxide film 24 having a predetermined thickness is formed on the entire structure, and the first to third oxide films 16, 20, and 24 are stacked in the first region A. FIG. An insulating film 26 is formed, and in the second region B, a second gate insulating film 25 in which the second and third oxide films 20 and 24 are stacked is formed, and in the third region C, the second gate insulating film 25 is formed. A third gate insulating film 24 made of the second oxide film 24 is formed.

Referring to FIG. 1E, the conductive film 28 is deposited on the entire structure, and then the conductive film 28 and the first to third gate insulating layers 24 to 26 are patterned to form a first gate in the first region A. FIG. The electrode 30a is formed, the second gate electrode 30b is formed in the second region B, and the third gate electrode 30c is formed in the third region C.

As such, three masking processes and deposition / etching processes are performed to form triple gate oxide films having different thicknesses. Due to this, not only the manufacturing cost / manufacturing time is increased due to the increase in the processing steps, but also a weak effect on the yield improvement, and the patterning process using the photoresist film has a great difficulty in securing the margin as the directivity of the device increases. In addition, the cleaning process for removing the oxide film formed in the different areas is performed, causing a problem that increases the particle (Particle) of the surface portion of the semiconductor substrate. In addition, the use of stacked oxide films (SiO 2 / SiO 2 / SiO 2) as a gate insulating film causes a problem that the quality of the gate insulating film is degraded. In addition, the threshold voltage is changed due to excessive thermal supply of the gate oxide, and adversely affects the gate oxide reliability (GOI). Due to excessive heat supply, many problems may occur in the future when high-integration and high-performance semiconductor devices are realized. Also, a large problem occurs in terms of securing process margin and process integration.

Accordingly, the present invention can form triple gate electrodes having different thicknesses through a single deposition process after nitrogen and fluorine ion implantation processes to solve the above problems, thereby improving reliability of the gate oxide film as well as process margins. It provides a method for manufacturing a semiconductor device that can be.

1A to 1E are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 110: semiconductor substrate 12, 112: device isolation film

14, 114: well 18, 22, 118, 122: photoresist pattern

16, 20, 24, 116: oxide films 28, 132: conductive films

25, 26, 130: gate insulating film 30, 134: gate electrode

120: nitrogen ion layer 124: fluorine ion layer

136: low concentration impurity region 138: spacer

140: high concentration impurity region 142: source / drain

144: silicide film

A first region in which a first gate insulating film of a first thickness according to the present invention is to be formed, a second region in which a second gate insulating film of a second thickness thinner than the first thickness is to be formed, and a third thinner than the second thickness Providing a semiconductor substrate having a third region in which a third gate insulating layer having a thickness is formed, forming a nitrogen ion layer in the third region by performing a nitrogen ion implantation process, and performing a fluorine ion implantation process Forming a fluorine ion layer in a first region, and performing a thermal oxidation process to form a first gate insulating film having a first thickness in the first region where the fluorine ion layer is formed, and forming a second thickness in the second region. Forming a two-gate oxide film, forming a third gate oxide film having a third thickness in the third region where the nitrogen ion layer is formed, and forming a conductive film on the entire structure And forming a first gate electrode in the first region, forming a second gate electrode in the second region, and forming a third gate electrode in the third region. It provides a manufacturing method.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 2A, a first region in which a first gate insulating layer having a first thickness is formed (high voltage element region A) and a second region in which a second gate insulating layer having a second thickness is formed (low voltage element region B) And forming the device isolation film 112 in the device isolation region of the semiconductor substrate 110 in which the third region (high performance device region C) on which the third gate insulating film of the third thickness is formed is formed. The well 114 is formed in the semiconductor substrate 110. The first gate insulating film of the first thickness refers to the gate insulating film thicker than the second gate insulating film of the second thickness. In addition, the second gate insulating film of the second thickness refers to the gate insulating film thicker than the third gate insulating film of the third thickness. For example, the first gate insulating film is a gate insulating film having a thickness of about 45 to 75 kW, the gate insulating film used in a transistor of a high voltage device, and the second gate insulating film is a gate insulating film having a thickness of about 18 to 25 kW. , Refers to a gate insulating film used in a transistor of a low voltage device, and the third gate insulating film is a gate insulating film having a thickness of about 12 to 18 kHz, and refers to a gate insulating film used in a transistor of a high performance device.

A pad oxide film (not shown) and a pad nitride film (not shown) are sequentially formed on the semiconductor substrate 110. After the photoresist is deposited on the entire structure, a photolithography process using a photoresist mask is performed to form a photoresist pattern (not shown). A trench (not shown) is formed by using a STI (Sallow Trench Isolation) etching process using the photoresist pattern and the pad nitride layer as an etching mask, and the device isolation layer 112 is formed by filling the trench using an insulating layer. The semiconductor substrate 110 is separated into an active region and an inactive region (ie, an isolation region) by the isolation layer 112. The device isolation layer 112 may be formed through various forms of processes, without being limited thereto. For example, the device isolation film may be formed using only the photoresist pattern without depositing the above-described pad oxide film and pad nitride film, and the wells may be first formed on the semiconductor substrate, and then the device isolation film may be formed.

Next, the pad nitride film and the pad oxide film formed on the semiconductor substrate 110 are etched, but the pad oxide film is not etched completely, but is partially used to form a screen oxide film which serves as a buffer layer for ion implantation for subsequent well formation. . After forming an ion implantation mask (not shown) that opens the region where the semiconductor device is to be formed, the well 114 is formed in the exposed region of the semiconductor substrate 110 through an ion implantation process. In this case, in order to form the PMOS transistor and the NMOS transistor, n wells and p wells must be formed, respectively, so that n wells and p wells are formed through two ion implantation mask formation processes and two ion implantation processes, respectively. In more detail, first, an ion implantation mask for opening the p well region is formed, followed by implantation of boron (Boron) to form a p well, and again an ion implantation mask for opening the n well region, followed by phosphorus ) Or arsenic (Arsenic) is injected to form an n well. The pad oxide film remaining on the semiconductor substrate 110 is completely removed.

The above-described conditions of the ion implantation process are not limited thereto, and the ion implantation is performed under such a condition that a junction is formed on the surface of the semiconductor substrate so as not to cause other leakage currents and leakage between the well and the junction does not occur. In addition, the photoresist pattern may be formed to implant ions only in a predetermined region. The present invention is not limited thereto, and ion implantation may be performed after depositing a screen oxide film (not shown), which serves as a buffer layer for suppressing crystal defects or performing surface treatment and ion implantation on a semiconductor substrate.

Referring to FIG. 2B, a buffer oxide film 116 is formed on the semiconductor substrate 110. The buffer oxide film 116 is a buffer film for protecting the semiconductor substrate 110 during the subsequent ion implantation process, and is formed through a wet oxidation process, but preferably formed at a thickness of 80 to 120 占 퐉 in a temperature range of about 700 to 900 ° C. Do.

2C and 2D, a nitrogen ion implantation process is performed to form a nitrogen (N2) ion layer 120 in the third region C, and a fluorine ion implantation process is performed to fluorine in the first region A. FIG. An ion layer 124 is formed.

After applying the photoresist on the entire structure, a photolithography process using a mask is performed to form a first photoresist pattern 118 that opens the third region C. FIG. It is preferable to form the nitrogen ion layer 120 in the third region C by performing a nitrogen ion implantation process using the first photosensitive film pattern 118 as an ion implantation mask. In the nitrogen ion implantation process, N ₂ is used as a dopant, and a dose of 8E13 to 9E13 ion / cm 2 is preferably injected at an ion implantation energy of 3 to 7 KeV. It is preferable to inject a dose of 8E13 ion / cm 2 at an ion implantation energy of 5 KeV in a nitrogen ion implantation process. It is preferable to remove the first photoresist pattern 118 by performing a predetermined strip process.

After the photoresist is coated on the entire structure, a photolithography process using a mask is performed to form a second photoresist pattern 122 that opens the first region A. FIG. It is preferable to form a fluorine ion layer 124 in the first region A by performing a fluorine ion implantation process using the second photosensitive film pattern 122 as an ion implantation mask. In the fluorine ion implantation step, F is used as a dopant, and a dose of 1E14 to 3E14 ion / cm 2 is preferably injected at an ion implantation energy of 5 to 12 KeV. In the fluorine ion implantation process, it is preferable to inject a dose of 1E14 ion / cm 2 at an ion implantation energy of 10 KeV. In this case, the fluorine ion layer 124 may be first formed in the first region A through the fluorine ion implantation process, and then the nitrogen ion layer 120 may be formed in the third region C through the nitrogen ion implantation process. .

As a result, the oxide film formed on the semiconductor substrate 110 through the subsequent thermal oxidation process is formed thickest on the first region A in which the fluorine ion layer 124 is present, and the third region in which the nitrogen ion layer 120 is present. Most thinly formed on the phase. The second region B is formed thinner than the oxide film formed in the first region A and thicker than the third region C in which the nitrogen ion layer 120 is present. This is because the phenomenon in which the silicon substrate is oxidized by the fluorine / nitrogen ions injected into the substrate surface layer is different. That is, the oxidation phenomenon is increased through fluorine ion implantation and the oxidation phenomenon is reduced through nitrogen ion implantation.

It is preferable to remove the second photoresist pattern 122 by performing a predetermined strip process. It is preferable to remove the buffer oxide layer 116 on the semiconductor substrate 110 through an etching process. The buffer oxide film 116 is preferably removed using an HF aqueous solution. In addition, the buffer oxide film 116 may be removed through a cleaning process before a subsequent thermal oxidation process. The semiconductor substrate 110 may be cleaned to suppress the increase of particles on the surface of the substrate, thereby improving the quality of the gate insulating layer.

Referring to FIG. 2E, a thermal oxidation process is performed to form a first gate insulating film 130a having a first thickness in the first region A, and a second gate oxide film having a second thickness (second) in the second region B. 130b), and a third gate oxide film 130c having a third thickness is formed in the third region C.

As described above, the aspect of the semiconductor substrate 110 in the first to third regions A to C is different. In other words, the fluorine ion layer 124 is formed in the first region A, the nitrogen ion layer 120 is formed in the third region B, and the ion layer is not formed in the second region C. As a result, the thicknesses of the oxide films formed during the thermal oxidation process are different from each other. Therefore, by adjusting the dose of fluorine / nitrogen ions injected into the semiconductor substrate 110 in each of the first to third regions A to C, the target oxide film thickness can be formed in each region. Nitrogen prevents oxidation by acting as an oxygen barrier on the silicon and SiO ₂ interface used as the semiconductor substrate, and oxidization rate is faster because fluorine diffuses oxygen faster.

The thermal oxidation process is preferably subjected to wet oxidation followed by an annealing process in-situ under pure NO gas atmosphere. In addition, the annealing process may outgas the fluorine ions remaining in the substrate. The annealing process is preferably performed for about 10 to 30 minutes by injecting about 9 to 12 slm N ₂ gas and about 4 to 6 slm NO gas within a temperature range of 600 to 900 ° C.

Referring to FIG. 2F, a conductive film 132 is formed on the first to third gate insulating layers 130 formed on the first to third regions A to C, respectively. The conductive layer 132 and the first to third gate insulating layers 130 are patterned through a patterning process using a gate mask to form gate electrodes 134 in the first to third regions A to C, respectively. In order to form a source / drain having an LDD structure, a low concentration impurity region may be formed by a low concentration ion implantation process in the semiconductor substrate 110 at both edges of the gate electrode 134 formed in a predetermined pattern in the first to third regions A to C. 136), respectively.

The conductive film 132 is preferably formed using at least one of a polysilicon film, a SiGe film, a WSi ₂ film, a TiSi ₂ film, a TiN film, and a tungsten film (W). In this embodiment, a polysilicon film having a thickness of 1500 to 2500 Å is used as the conductive film 132. After the conductive film 132 is formed, the damage of the substrate through the nitrogen and fluorine ion implantation process is canceled, and the N ₂ furnace annealing for improving GOI characteristics is 20 to 40 in a temperature range of 700 to 900 ° C. It is preferable to carry out for a minute.

After the photoresist is coated on the conductive layer 132, a photolithography process using a gate mask is performed to form a photoresist pattern (not shown). An etching process using the photoresist pattern as an etching mask is performed to sequentially etch the conductive layer 132 and the first gate insulating layer 130a in the first region A, and the conductive layer 132 in the second region B. ) And the second gate insulating layer 130b are sequentially etched, and in the third region C, the conductive layer 132 and the third gate insulating layer 130c are sequentially etched to form the first to third gate electrodes 134. To form. The first to third gate electrodes 134 in the first to third regions A to C may be simultaneously formed by performing one etching process or may be formed by performing different etching processes. In order to form the junction region (source / drain) of the LDD structure, n-type impurities or p-type impurities are implanted to form a low concentration impurity region 136.

Referring to FIG. 2G, a first insulating film (not shown) for forming insulating film spacers 138 on both side surfaces of the first to third gate electrodes 134 formed in the first to third regions A to C, and A second insulating film (not shown) is sequentially formed over the whole. Subsequently, the first and second insulating layers are left only on both sides of the gate electrode 134 by the entire surface etching process to form an insulating layer spacer 138 including the first and second insulating layers.

In the above description, the first insulating film is formed of low pressure silicon oxide (LP-TEOS), and the second insulating film is formed of silicon nitride (Si ₃ N ₄ ). In this case, the first insulating film serves as a buffer oxide film that prevents stress from occurring when the gate electrode 134 made of a polysilicon film and the second insulating film made of silicon nitride directly contact each other.

Thereafter, the high concentration impurity region 140 is formed by the high concentration impurity region 140 in the high concentration ion implantation process on the semiconductor substrate 110 at the edge of the insulating film spacer 138 formed on both sides of the gate electrode 134 to form the source / drain 142. Deeper than 136). Here, the high concentration impurity region 140 is formed by implanting n-type impurities into the nMOS region, and the high concentration impurity region 140 is formed by implanting p-type impurities into the pMOS region. As a result, an LDD structure source / drain 142 including the low concentration impurity region 136 and the high concentration impurity region 140 is formed. In addition, a rapid heat treatment process for activating the implanted impurities after a high concentration of impurity ions implanted.

Meanwhile, in order to lower the contact resistance between the gate electrode 134 and the source / drain 142 and the contact plug to be formed in a subsequent process, the silicide layer 144 is disposed on the upper surface of the gate electrode 134 and the source / drain 142. Form.

A method of forming the silicide layer 144 will be described below. First, a natural oxide film on the surfaces of the gate electrode 134 and the source / drain 142 is removed, and a metal film (not shown) and a capping film (not shown) are sequentially formed on the entire top, and then the first heat treatment process is performed. The silicide layer 144 is formed by reacting the silicon component of the gate electrode 134 and the source / drain 142 with the metal component of the metal layer. Thereafter, after removing the capping film and the unreacted metal film, a second heat treatment process is performed to improve the quality of the silicide film 144. As a result, a triple gate insulating film having a gate insulating film having a different thickness can be formed.

As described above, the present invention may simultaneously form triple gate insulating films having different thicknesses through a nitrogen ion implantation process and a fluorine ion implantation process.

In addition, it is possible to improve the film quality of the gate insulating film by using a buffer oxide film during the nitrogen and fluorine ion implantation process, cleaning the substrate before forming the triple gate insulating film, and furnace annealing after polysilicon deposition.

In addition, the thermal burden can be suppressed to improve thermal safety, improve GOI characteristics, and suppress changes in threshold voltages that may occur during device operation.

Claims (4)

A first region in which a first gate insulating film having a first thickness is to be formed, a second region in which a second gate insulating film having a second thickness thinner than the first thickness is to be formed, and a third having a third thickness thinner than the second thickness Providing a semiconductor substrate having a third region in which a gate insulating film is formed; Performing a nitrogen ion implantation process to form a nitrogen ion layer in the third region; Performing a fluorine ion implantation process to form a fluorine ion layer in the first region; Thermal oxidation is performed to form a first gate insulating film having a first thickness in the first region where the fluorine ion layer is formed, a second gate oxide film having a second thickness in the second region, and the nitrogen ion layer is formed. Forming a third gate oxide film having a third thickness in the third region; And After forming a conductive film on the entire structure, a patterning process is performed to form a first gate electrode in the first region, a second gate electrode in the second region, and a third gate electrode in the third region. Method for manufacturing a semiconductor device comprising the step. The method of claim 1, In the nitrogen ion implantation process, N ₂ is used as a dopant, and a dose of 8E13 to 9E13 ion / cm 2 is injected at an ion implantation energy of 3 to 7 KeV. The method of claim 1, The fluorine ion implantation process is a semiconductor device manufacturing method using a dopant as a dopant, the dose amount of 1E14 to 3E14 ion / ㎠ by the ion implantation energy of 5 to 12 KeV. The method of claim 1, The thermal oxidation process is a semiconductor device which performs annealing for about 10 to 30 minutes by performing wet oxidation and injecting about 9 to 12 slm N ₂ gas and about 4 to 6 slm NO gas within a temperature range of 600 to 900 ° C. Method of preparation.