KR100247811B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR100247811B1 KR100247811B1 KR1019970072221A KR19970072221A KR100247811B1 KR 100247811 B1 KR100247811 B1 KR 100247811B1 KR 1019970072221 A KR1019970072221 A KR 1019970072221A KR 19970072221 A KR19970072221 A KR 19970072221A KR 100247811 B1 KR100247811 B1 KR 100247811B1
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000010410 layer Substances 0.000 claims abstract description 79
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 150000004767 nitrides Chemical class 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 18
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 18
- 230000008569 process Effects 0.000 claims abstract description 12
- 239000011229 interlayer Substances 0.000 claims abstract description 10
- 238000010405 reoxidation reaction Methods 0.000 claims abstract description 10
- 238000002955 isolation Methods 0.000 claims abstract description 9
- 230000004888 barrier function Effects 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 238000002844 melting Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 229910052750 molybdenum Inorganic materials 0.000 claims 1
- 238000004544 sputter deposition Methods 0.000 claims 1
- 229910052719 titanium Inorganic materials 0.000 claims 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 17
- 239000010937 tungsten Substances 0.000 abstract description 17
- 230000003647 oxidation Effects 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 7
- 230000002159 abnormal effect Effects 0.000 abstract description 6
- 238000000059 patterning Methods 0.000 abstract description 6
- 229920005591 polysilicon Polymers 0.000 abstract description 5
- 238000007796 conventional method Methods 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
Abstract
본 발명은 금속게이트를 갖는 소자의 게이트산화막의 신뢰성 및 소자의 성능을 개선시킨 것으로서 종래의 기술에서 텅스텐 게이트에서의 텅스텐 이상산화문제로 인한 재산화공정(reoxidation)을 생략하는 것에 비해 본 발명에서는 게이트 형성을 위한 폴리실리콘 패터닝 후 재산화공정을 진행하므로서 텅스텐의 이상 산화문제를 해결하는 반도체장치의 모스소자 제조방법에 관한 것이다.The present invention improves the reliability of the gate oxide film of the device having the metal gate and the performance of the device. In the present invention, the gate of the present invention is omitted, compared to the conventional technique, which eliminates reoxidation due to the problem of tungsten abnormal oxidation in the tungsten gate. The present invention relates to a method for manufacturing a MOS device of a semiconductor device that solves the problem of abnormal oxidation of tungsten by performing a reoxidation process after polysilicon patterning.
이를 위하여 본 발명은 반도체기판에 필드산화막을 형성하여 소자의 활성영역과 격리영역을 형성하고 채널을 형성하는 단계와, 기판의 표면에 게이트 제 1 산화막을 형성하는 단계와, 필드산화막 및 게이트 제 1 산화막위에 도전층을 형성하는 단계와, 도전층 위에 질화막을 형성하는 단계와, 질화막과 도전층 그리고 게이트 제 1 산화막의 소정부위를 제거하여 게이트를 패터닝함과 동시에 기판 표면을 노출시키는 단계와, 노출된 기판의 표면과 잔류한 도전층의 측면에 제 2 산화막을 형성하는 단계와, 기판 표면에 층간절연층을 형성한 다음 층간절연층의 표면과 잔류한 질화막의 표면을 평탄화시키는 단계와, 잔류한 질화막을 제거하는 단계와, 노출된 도전층의 표면에 배리어용 제 1 금속층을 형성하는 단계와, 제 1 금속층의 표면에 제 2 금속층을 형성하는 단계와, 잔류한 층간절연층을 제거하는 단계와, 기판의 소정 부위에 소스/드레인을 형성하는 단계로 이루어진 공정을 구비한다.To this end, the present invention is to form a field oxide film on the semiconductor substrate to form an active region and an isolation region of the device, and to form a channel, to form a gate first oxide film on the surface of the substrate, the field oxide film and the gate first Forming a conductive layer on the oxide film, forming a nitride film on the conductive layer, removing a predetermined portion of the nitride film, the conductive layer and the gate first oxide film, patterning the gate and exposing the substrate surface; Forming a second oxide film on the surface of the substrate and the side of the remaining conductive layer, forming an interlayer insulating layer on the surface of the substrate, and then planarizing the surface of the interlayer insulating layer and the surface of the remaining nitride film; Removing the nitride film, forming a barrier first metal layer on the exposed conductive layer, and forming a second metal layer on the surface of the first metal layer. And the step, a step consisting of removing the residual inter-layer insulating layer, and forming a source / drain to a predetermined portion of a substrate.
Description
본 발명은 반도체장치의 제조방법에 관한 것으로서 특히, 금속게이트를 갖는 소자의 게이트산화막의 신뢰성 및 소자의 성능을 개선시킨 것으로서 종래의 기술에서 텅스텐 게이트에서의 텅스텐 이상산화문제로 인한 재산화공정(reoxidation)을 생략하는 것에 비해 본 발명에서는 게이트 형성을 위한 폴리실리콘 패터닝 후 재산화공정을 진행하므로서 텅스텐의 이상산화문제를 해결하는 모스소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to improve the reliability and performance of a gate oxide film of a device having a metal gate. Compared to omission of the present invention, the present invention relates to a method for manufacturing a MOS device that solves the problem of tungsten abnormal oxidation by performing a reoxidation process after polysilicon patterning for gate formation.
반도체장치가 고집적화됨에 따라 소오스 및 드레인영역으로 이용되는 불순물영역과 게이트의 폭이 감소되고 있다. 이에 따라, 반도체장치는 불순물영역의 접촉 저항 및 게이트의 시트 저항이 증가하여 동작 속도가 저하되는 문제점이 발생되었다.As semiconductor devices are highly integrated, the widths of impurity regions and gates used as source and drain regions are reduced. As a result, the semiconductor device has a problem in that an operating speed decreases due to an increase in contact resistance of an impurity region and sheet resistance of a gate.
그러므로, 반도체장치 내의 소자들의 배선을 알루미늄 합금 및 텅스텐 등의 저저항 물질로 형성하거나, 또는, 게이트와 같이 다결정실리콘으로 형성하는 경우에 실리사이드층을 형성하여 저항을 감소시킨다. 상기에서 다결정실리콘으로 형성된 게이트에 실리사이드층을 형성할 때 불순물영역의 표면에도 실리사이드층을 형성하여 접촉 저항을 감소시킨다.Therefore, when the wirings of the elements in the semiconductor device are formed of low resistance materials such as aluminum alloy and tungsten, or formed of polycrystalline silicon such as a gate, a silicide layer is formed to reduce the resistance. When the silicide layer is formed on the gate formed of polycrystalline silicon, a silicide layer is also formed on the surface of the impurity region to reduce the contact resistance.
도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 제조공정도이다.1A to 1D are manufacturing process diagrams of a semiconductor device according to the prior art.
도 1a를 참조하면, P형의 반도체기판(1)의 소정 부분에 에스티아이(shallow trench isolation) 방법 등의 소자격리방법에 의해 트렌치를 형성하여 소자의 활성영역과 소자격리영역을 형성한 다음 트렌치를 충전하도록 필드산화막(2)을 트렌치 내부에 충분히 증착하여 형성한 후 표면을 씨엠피 공정으로 평탄화 시킨다.Referring to FIG. 1A, a trench is formed in a predetermined portion of a P-type semiconductor substrate 1 by an isolation method such as a shallow trench isolation method to form an active region and an isolation region of the device, and then the trench is formed. The
그리고 기판(21)의 표면에 열산화공정을 실시하여 게이트산화막(3)을 성장시켜 형성한다. 그리고 게이트 산화막(3) 상에 도핑되지 않은 비정질실리콘층(4)을 증착하여 형성한다.The thermal oxidation process is performed on the surface of the
도 1b를 참조하면, 비정질실리콘층(4)에 도전성을 주기 위하여 불순물주입을 위한 이온주입을 실시한 후 어닐링을 실시하여 불순물 이온을 충분히 확산시킨다.Referring to FIG. 1B, in order to impart conductivity to the amorphous silicon layer 4, ion implantation for impurity implantation is performed, followed by annealing to sufficiently diffuse impurity ions.
도 1c를 참조하면, 실리콘층(4) 위에 배리어 금속으로 TiN층(5)을 형성한 후 다시 그(5) 위에 텅스텐층(6)을 형성한다. 그리고 식각시 하드마스크로 이용하기 위하여 PETOS층(7)을 텅스텐층(6) 위에 형성한다.Referring to FIG. 1C, after forming the
그리고 텅스텐층(7) 위에 포토레지스트를 도포한 후 사진공정을 실시하여 게이트를 정의하기 위한 포토레지스트패턴(8)을 형성한다.After the photoresist is applied on the tungsten layer 7, a photoresist is performed to form a
도 1d를 참조하면, 포토레지스트패턴(8)을 이용한 비등방성 식각을 기판(1) 표면에 실시하여 포토레지스트패턴(8)으로 보호되지 아니하는 부위의 PETEOS 층(7)을 제거한 후 포토레지스트패턴(8)을 제거한다.Referring to FIG. 1D, anisotropic etching using the
그리고 잔류한 PETOS층(7)을 하드마스크로 이용한 건식식각을 실시하여 하드마스크로 보호되지 아니하는 부위의 텅스텐층(6)/TiN층(5)을 식각한 다음 다시 실리콘층(4)을 식각하여 게이트(4, 5, 6)을 패터닝한다.Dry etching using the remaining PETOS layer 7 as a hard mask is performed to etch the
이후 일반적인 제조공정으로 소스/드레인을 형성하여 MOSFET(MOS field effect transistor)를 완성한다.After that, a source / drain is formed in a general manufacturing process to complete a MOSFET (MOS field effect transistor).
상술한 바와 같이 종래 기술은 금속층을 증착하여 형성한 후 텅스텐/TiN/실리콘을 동시에 식각하므로서 게이트 패터닝 후 재산화공정을 실시할 경우 텅스텐의 이상산화 문제가 발생하며, 만약 재산화공정을 실시하지 아니할 경우 게이트산화막의 모서리 부분이 취약해져서 게이트 산화막의 신뢰성을 저하시키는 문제점이 있다.As described above, in the prior art, when tungsten / TiN / silicon is simultaneously etched and then metallization is performed, a reoxidation process occurs after the gate patterning, thereby causing an abnormal oxidation of tungsten. In this case, there is a problem in that the edge portion of the gate oxide film becomes weak, thereby reducing the reliability of the gate oxide film.
따라서, 본 발명의 목적은 금속게이트를 갖는 소자의 게이트산화막의 신뢰성 및 소자의 성능을 개선시킨 것으로서 종래의 기술에서 텅스텐 게이트에서의 텅스텐 이상산화문제로 인한 재산화공정(reoxidation)을 생략하는 것에 비해 본 발명에서는 게이트 형성을 위한 폴리실리콘 패터닝 후 재산화공정을 진행하므로서 텅스텐의 이상산화문제를 해결하는 모스소자 제조방법을 제공하는데 있다.Accordingly, an object of the present invention is to improve the reliability of the gate oxide film and the device performance of a device having a metal gate, as compared to the conventional technique of eliminating reoxidation due to the problem of tungsten abnormal oxidation in a tungsten gate. The present invention provides a method for manufacturing a MOS device that solves the problem of abnormal oxidation of tungsten by proceeding the reoxidation process after polysilicon patterning for gate formation.
상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 제조방법은 반도체기판에 필드산화막을 형성하여 소자의 활성영역과 격리영역을 형성하고 채널을 형성하는 단계와, 기판의 표면에 게이트 제 1 산화막을 형성하는 단계와, 필드산화막 및 게이트 제 1 산화막위에 도전층을 형성하는 단계와, 도전층 위에 질화막을 형성하는 단계와, 질화막과 도전층 그리고 게이트 제 1 산화막의 소정부위를 제거하여 게이트를 패터닝함과 동시에 기판 표면을 노출시키는 단계와, 노출된 기판의 표면과 잔류한 도전층의 측면에 제 2 산화막을 형성하는 단계와, 기판 표면에 층간절연층을 형성한 다음 층간절연층의 표면과 잔류한 질화막의 표면을 평탄화시키는 단계와, 잔류한 질화막을 제거하는 단계와, 노출된 도전층의 표면에 배리어용 제 1 금속층을 형성하는 단계와, 제 1 금속층의 표면에 제 2 금속층을 형성하는 단계와, 잔류한 층간절연층을 제거하는 단계와, 기판의 소정 부위에 소스/드레인을 형성하는 단계로 이루어진 공정을 구비한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object is to form a field oxide film on a semiconductor substrate to form an active region and an isolation region of the device, and to form a channel, and to form a gate first oxide film on the surface of the substrate. Forming a layer, forming a conductive layer on the field oxide film and the gate first oxide film, forming a nitride film on the conductive layer, and removing a predetermined portion of the nitride film, the conductive layer, and the gate first oxide film to pattern the gate. Simultaneously exposing the substrate surface, forming a second oxide film on the exposed surface of the substrate and the side of the remaining conductive layer, forming an interlayer dielectric layer on the substrate surface and then remaining with the surface of the interlayer dielectric layer. Planarizing the surface of the nitride film, removing the remaining nitride film, and forming a barrier first metal layer on the exposed surface of the conductive layer. And a step consisting of a system and comprising the steps of: forming a second metal layer on the surface of the first metal layer and the step of removing the residual inter-layer insulating layer, and forming a source / drain to a predetermined portion of the substrate.
도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 제조공정도1A to 1D are manufacturing process diagrams of a semiconductor device according to the prior art.
도 2a 내지 도 2e는 본 발명에 따른 반도체장치의 제조 공정도2A to 2E are manufacturing process diagrams of a semiconductor device according to the present invention.
본 발명은 폴리실리콘을 먼저 식각하여 패터닝 한 다음 폴리실리콘의 노출된 표면에 재산화공정을 실시하므로서 게이트산화막의 모서리 부분을 보완해줄 수 있으며 질화막의 두께를 조절하여 T 자형 게이트를 형성할 수 있다.According to the present invention, the polysilicon may be etched and patterned first, and then a reoxidation process may be performed on the exposed surface of the polysilicon to compensate for the corner portion of the gate oxide layer and to control the thickness of the nitride layer to form a T-shaped gate.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 따른 반도체장치의 제조공정도이다.2A to 2E are manufacturing process diagrams of a semiconductor device according to the present invention.
도 2a를 참조하면, P형의 반도체기판(21)의 소정 부분에 LOCOS 방법 또는 STI (Shallow Trench Isolation) 등의 소자격리방법에 의해 필드산화막(22)을 형성하여 소자의 활성영역과 소자격리영역을 형성하고 채널을 형성한다.Referring to FIG. 2A, a
그리고 반도체기판(21)의 표면을 열산화하여 게이트산화막(23)을 형성한다. 그리고, 필드산화막(22) 및 게이트산화막(23)의 상부에 불순물이 도핑되지 아니한 비정질 실리콘층(24)을 증착한 다음 실리콘층(24) 위에 질화막(25)을 증착하여 형성한다.The surface of the
도 2b에 있어서, 실리콘층(24)에 도전성을 주기 위하여 형성될 소자의 종류에 따라 각각 다른 도전형의 불순물로 이온주입한 후 어닐링을 실시하여 불순물 이온이 실리콘층(24)내로 충분히 확산되도록 한다.In FIG. 2B, ions are implanted with impurities of different conductivity types according to the type of devices to be formed to give conductivity to the
도 2c에 있어서, 게이트를 패터닝하기 위하여 포토레지스트를 질화막(25)상에 도포한 후 사진공정을 실시하여 포토레지스트패턴을 형성한 다음 이로 부터 보호되지 아니하는 부위의 질화막(25)과 실리콘층(24) 그리고 게이트산화막(23)을 제거하여 게이트를 패터닝함과 동시에 기판(21) 표면을 노출시킨다. 따라서 이때 노출된 부분은 게이트(24)를 이루는 잔류한 실리콘층(24)의 측면과 기판(21)의 표면 일부이다. 그리고 포토레지스트패턴을 제거한 다음 노출된 기판의 표면과 잔류한 실리콘층(24)의 측면에 재산화(reoxidation)공정을 실시하여 산화막(26)을 성장시켜 형성한다.In FIG. 2C, a photoresist is applied onto the
도 2d에 있어서, 게이트 패터닝으로 발생한 기판(21) 표면의 단차를 없애고 층간절연을 위하여 기판 표면에 PSG층(27)을 증착하여 형성한 다음 씨엠피 공정을 실시하여 잔류한 질화막(25)의 표면과 PSG층(27)의 표면의 단차를 줄이는 평탄화공정을 실시한다.In FIG. 2D, the
그리고 잔류한 질화막(25)을 습식식각으로 제거하여 게이트를 이루는 잔류한 실리콘층(24)의 표면을 노출시킨다.The
도 2e에 있어서, 선택적 화학기상증착법을 이용하여 질화막(25)이 제거된 부위 즉 노출된 실리콘층(24)의 표면에 배리어금속인 TiN 층(28) 및 텅스텐층(29)을 차례로 증착하여 형성한 다음 잔류한 PSG층(27)을 식각하여 완전히 제거하므로서 최종적으로 텅스텐층/TiN층/실리콘층으로 이루어진 게이트(29, 28, 24)를 완성한다.In FIG. 2E, a
그리고 도시되지는 않았으나 이후 일반적인 공정을 거쳐 모스 트렌지스터를 완성한다.Although not shown, the MOS transistor is completed through a general process.
즉, 게이트를 마스크로 사용하여 반도체기판에 아세닉(As) 또는 인(P) 등의 N형 또는 붕소 등의 P형 불순물을 저농도로 이온 주입하여 LDD 구조를 형성하기 위한 저농도영역을 형성한 다음 게이트의 측면에 측벽을 형성하고In other words, using a gate as a mask, a low concentration region for forming an LDD structure is formed by ion implanting N-type or P-type impurities such as boron (such as boron) or phosphorous (P) into a semiconductor substrate at low concentration. Form sidewalls on the sides of the gate
게이트와 측벽을 마스크로 사용하여 반도체기판에 각각의 저농도 불순물을 형성한 이온과 동일한 이온을 고농도로 이온주입하여 소오스 및 드레인영역으로 이용되는 고농도영역을 저농도영역과 중첩되게 형성하여 모스트렌지스터를 형성한다.Using a gate and sidewalls as a mask, ion implants are implanted at high concentrations with the same ions as each of the low-concentration impurities formed on the semiconductor substrate, so that a high concentration region used as a source and a drain region overlaps with the low concentration region to form a MOS transistor. .
따라서, 본 발명은 게이트를 이루는 실리콘층의 노출된 측면을 보호하기 위한 재산화공정으로 산화막을 형성한 후에 배리어금속층과 텅스텐층을 형성하므로서 게이트산화막의 신뢰성을 향상시킬 수 있고 또한 질화막의 형성 크기에 따라 T 자형 게이트를 제조할 수 있는 효과가 있다.Accordingly, the present invention can improve the reliability of the gate oxide film by forming the barrier metal layer and the tungsten layer after the oxide film is formed by the reoxidation process to protect the exposed side surface of the silicon layer forming the gate, and the formation size of the nitride film. Therefore, there is an effect that can produce a T-shaped gate.
Claims (6)
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