KR100606952B1 - Method for Forming Transistor Of Semi-conductor Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a transistor of a semiconductor device in which a gate is wet-etched in order to minimize damage to an active region in a transistor fabrication process, and a low source / drain resistance is obtained by applying a Ge implant. Sequentially depositing a buffer film and a silicon nitride film on the semiconductor substrate, etching the silicon nitride film, the buffer film, and the semiconductor substrate to form a trench having a predetermined depth, depositing a front surface oxide film including the trench, and depositing a front surface. Etching to form a first sidewall spacer in the trench; sequentially forming a gate oxide film and a gate in the trench; etching the silicon nitride film; and etching the first sidewall spacer as a mask. Forming an LDD region by injecting a dopant; And forming a second sidewall spacer on the outer sidewall of the wall spacer, and implanting a high concentration of impurities using the second sidewall spacer as a mask to form a source / drain region.

Transistor, Gate, Short Channel Phenomenon

Description

Method for Forming Transistor of Semiconductor Device {Method for Forming Transistor Of Semi-conductor Device}

1A to 1E are cross-sectional views illustrating a method of forming a transistor of a semiconductor device according to the prior art.

2A to 2I are cross-sectional views illustrating a method of forming a transistor in a semiconductor device according to the present invention.

* Explanation of symbols on the main parts of the drawings

201: semiconductor substrate 202: buffer film

203 silicon nitride film 204 trench

205: oxide film 206: first sidewall spacer

207: gate insulating film 208: gate

211: LDD area 212: HDD area

215: second sidewall spacer 230: salicide layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a transistor of a semiconductor device which is intended to improve the reliability of a device by removing damage of an active region by dry etching and minimizing a short channel phenomenon.

At present, semiconductor devices are required to form transistors, bit lines, capacitors, etc. of semiconductor devices for miniaturization, high capacity, and high integration, and thereafter, a subsequent process for forming multilayer wirings such as metal wirings to electrically connect the respective devices. I'm asking.

At this time, the transistor of the semiconductor device is composed of a MOS transistor having a short channel length to prevent short-channel effect, the source / drain region is generally a lightly doped drain (LDD) region and a heavily doped drain (HDD) region It is manufactured to have.

LDD regions have lower dopant concentrations and lower depths than HDD regions. However, the LDD region may be further adjacent to the gate electrode, setting the channel length of the MOS transistor. In contrast, the HDD area has a lower connection resistance.

As described above, in order to fabricate a MOS transistor having an LDD region and an HDD region, a gate dielectric and a gate electrode are first formed on a substrate, ion implanted using the gate electrode as a mask to form an LDD region, and then formed on the gate electrode sidewall. A spacer is formed and ion implanted to form an HDD region.

Hereinafter, a method of forming a transistor of a semiconductor device according to the prior art will be described in detail with reference to the accompanying drawings.

1A to 1E are cross-sectional views illustrating a method of forming a transistor of a semiconductor device according to the prior art.

First, as shown in FIG. 1A, the gate oxide layer 103 is formed on the entire surface of the semiconductor substrate 101 in which the device isolation process and the well process are performed by being divided into a logic region and a cell region. The polysilicon layer 104 is formed on the gate oxide film 103.

Thereafter, a photoresist (not shown) is applied and patterned on the polysilicon layer 104, and the polysilicon layer 104 and the gate oxide film 103 are selectively dried using the patterned photoresist as a mask. By etching, the gates 107 are formed on the logic regions, respectively, as shown in FIG. 1B.

At this time, since the etching selectivity of the polysilicon layer and the gate oxide film is different, the gate oxide film 103 is over-etched ("A") by dry etching using plasma.

Accordingly, as illustrated in FIG. 1C, the oxide film 118 is formed on the entire surface including the gate 107 to compensate for the over-etched gate oxide film 103.

Next, an LDD process and an HDD process are performed to form a source / drain region. An LDD process is first performed to form a junction of a source / drain region of a peripheral circuit device.

That is, as shown in FIG. 1D, n-impurity ions are implanted using the gate 107 as a mask to form a low concentration doped region to form the LDD region 108. At this time, the oxide film 118 serves as a buffer film.

Subsequently, as shown in FIG. 1E, an insulating layer is formed on the entire surface including the gate 107 to etch back the insulating layer to form sidewall spacers 109 on both side walls of the gate 107.

Subsequently, n + impurity is ion-implanted into the semiconductor substrate 101 using the gate 107 and the sidewall spacer 109 as a mask to form the HDD region 102 which is a highly doped region, thereby completing the source / drain region.

Although not shown, an interlayer insulating film is formed on the entire surface including the gate, and a source / drain electrode contacting the HDD region is formed through the interlayer insulating film to complete the transistor of the semiconductor device. The logic process is complete.

However, the conventional method of forming a transistor of a semiconductor device as described above has the following problems.

In other words, the drain caption and the gate overlap each other, where unwanted capacitance occurs, thereby reducing the performance of the device. When the gate patterning is performed, plasma damage is applied to the gate oxide edge portion “A”, thereby degrading the reliability of the device, such as deterioration of the gate oxide film due to hot carriers.

Accordingly, the present invention has been made to solve the above problems, in order to minimize the damage to the active region during the transistor fabrication process, by patterning the gate by wet etching and applying a Ge implant (low implant / source) An object of the present invention is to provide a method for forming a transistor of a semiconductor device to obtain a resistance.

Transistor formation method of a semiconductor device of the present invention for achieving the above object is a step of sequentially depositing a buffer film and a silicon nitride film on a semiconductor substrate, by etching the silicon nitride film, the buffer film and the semiconductor substrate of a predetermined depth Forming a trench, depositing a front oxide film including the trench and etching the entire surface to form a first sidewall spacer in the trench, sequentially forming a gate oxide film and a gate in the trench, and forming the silicon nitride film Forming a LDD region by implanting low concentration impurities using the first sidewall spacer as a mask, forming a second sidewall spacer on an outer sidewall of the first sidewall spacer, and forming a second sidewall spacer. High concentration impurities are implanted using the spacer as a mask to form source / drain regions. It characterized by comprising the steps:

As described above, the present invention is characterized in that the gate pattern is wet-etched in order to minimize damage to the active region during transistor fabrication.

Hereinafter, a method of forming a transistor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2I are cross-sectional views illustrating a method of forming a transistor of a semiconductor device according to the present invention.

First, although not shown, a trench is formed by applying a patterned photoresist on the semiconductor substrate and anisotropically etching the semiconductor substrate using the photoresist as a mask.

Thereafter, an insulating film is deposited on the entire silicon substrate to fill the trench, and then planarized to form a field oxide film to define an element formation region.

Next, as shown in FIG. 2A, the buffer layer 202 is formed using a thermal oxidation method to act as a buffer on the semiconductor substrate 201 where the device isolation process is performed to divide the logic region and the cell region. ) Is thinly formed and a thick silicon nitride film 203 is formed thereon.

Subsequently, as illustrated in FIG. 2B, photolithography and an etching process are applied to pattern the silicon nitride layer 203, the buffer layer 202, and the semiconductor substrate 201 to form a trench 204 of about 500 mW. This depth is a target that takes into account the final section depth created after all thermal processes, and the depth may be modified according to the characteristics of the device and the final section depth.

Subsequently, as shown in FIG. 2C, after the oxide film 205a is formed on the entire surface including the trench 204, the first sidewall spacer 206 is formed through the entire surface etching. After the step of forming the first sidewall spacer 206, channel implantation may be further performed as necessary.

As shown in FIG. 2D, an oxide material is deposited on the bottom surface of the trench 204 in which the first sidewall spacers 206 are formed to form a gate oxide layer 207, and polysilicon doped with impurities thereon. A conductive material 208a or the like is embedded.

Thereafter, as illustrated in FIG. 2E, the gate 208 is formed by performing a chemical mechanical polishing (CMP) process on the conductive material using the silicon nitride film 203 as an end point.

As described above, a trench is formed without patterning the gate by dry etching using plasma to form a first sidewall spacer, and then a gate is formed therein, thereby damaging plasma damage to the gate oxide edge portion. You can stop it. Therefore, the film quality of the gate oxide film is improved, and the resistance to hot carriers is higher than that of the gate oxide film subjected to plasma damage, thereby improving the reliability of the device.

Further, after forming the sidewall spacers in the trench formed by etching the semiconductor substrate, a gate having a small size can be formed more easily by forming a gate therein.

Subsequently, as illustrated in FIG. 2F, the silicon nitride film 203 formed on the buffer film 202 is etched by wet etching.

Next, as shown in FIG. 2G, LDD is implanted into the semiconductor substrate 201 by ion implantation of low concentration N-type impurities using the first sidewall spacer 206 and the gate 208 protruding between the semiconductor substrate 201 as a mask. Area 211 is formed. LDD regions are for source / drain junction formation. In this case, it is a general matter for a person skilled in the art to diffuse the low concentration N-type impurities to the edge of the gate electrode. Generally, the doping amount is controlled to diffuse impurities. As shown in FIG. 2G, the doping amount may be adjusted according to the width of the first sidewall spacer or the depth of the gate into the semiconductor substrate. Here, the buffer layer 202 serves as a buffer layer in the implantation process for forming the LDD region.

In this manner, by implanting impurities into the first sidewall spacers formed on both sidewalls of the gate without implanting impurity ions using the gate as a mask, the junction region can be prevented from overlapping under the gate.

As illustrated in FIG. 2H, a nitride film is deposited on the entire surface including the gate 208, and then second sidewall spacers 215 are formed on both sidewalls of the first sidewall spacer using a front surface etching method. When the second sidewall spacers 215 are formed, the buffer layer 202 serves as an etch stop layer.

Subsequently, a high concentration n-type impurity is ion-implanted into the semiconductor substrate 201 using the first and second sidewall spacers 206 and 215 and the gate 208 as a mask to form an HDD region 212 as a source / drain region. Here, the buffer film 202 is used as a buffer film in an ion implantation process for forming source / drain regions.

As shown in FIG. 2I, the second sidewall spacer 215 is removed, and the buffer film 202 on the upper surface of the semiconductor substrate is also removed by cleaning or etching.

Next, after depositing a high melting point metal, a heat treatment is performed to form the salicide layer 230 by allowing the metal, the semiconductor substrate, and the metal and the gate to react with each other. Then, a gap metal-filled gap is formed between the gate and the gate using a poly metal dielectric material (PMD).

Here, after forming the source / drain regions, the oxide layer may be cleaned and removed after removing the second sidewall spacer, and then a salicide layer may be formed. However, the second sidewall spacer may be removed to remove the gate and the gate. By securing the space between, the gap-fill capability of the PMD can be improved to prevent void formation between the gate and the gate.

Although not shown, an interlayer insulating film is formed on the entire surface including the gate, and a source / drain electrode contacting the HDD region is formed through the interlayer insulating film to complete the transistor of the semiconductor device. The logic process is complete.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

The transistor forming method of the semiconductor device of the present invention as described above has the following effects.

First, when the transistor is formed by the process proposed by the present invention, plasma damage to the edge portion of the gate oxide layer may be prevented, thereby improving the quality of the gate oxide layer. Therefore, the resistance to hot carriers is higher than that of the gate oxide film subjected to plasma damage, thereby improving the reliability of the device.

Second, after forming the sidewall spacer in the trench formed by etching the semiconductor substrate, the gate can be formed more easily by forming a gate.

Third, after the gate is formed inside the first sidewall spacer, an impurity for forming a source / drain region is implanted using the first sidewall spacer as a mask, thereby preventing the junction region from overlapping the gate.                     

Fourth, since the bridge between the gate and the active can be prevented by the first sidewall spacer when the salicide layer is formed, the second sidewall spacer can be removed, and thus, the gap between the gate and the gate can be increased, thereby increasing the gap of the PMD. Improve fill capability to prevent void formation between gates.

Claims (8)

Sequentially depositing a buffer film and a silicon nitride film on a semiconductor substrate; Etching the silicon nitride film, the buffer film and the semiconductor substrate to form a trench having a predetermined depth; Depositing a front oxide layer including the trench and etching the entire surface to form a first sidewall spacer in the trench; Sequentially forming a gate oxide film and a gate in the trench; Etching the silicon nitride film; Forming a LDD region by implanting low concentration impurities using the first sidewall spacer as a mask; Forming a second sidewall spacer on the outer sidewall of the first sidewall spacer; And forming a source / drain region by implanting a high concentration of impurities using the second sidewall spacer as a mask. The method of claim 1, After forming the source / drain regions, Removing the buffer layer; Depositing a metal on the semiconductor substrate and then performing heat treatment to form a salicide layer; And depositing a poly metal dielectric material (PMD) between the gate and the gate. The method of claim 2, Before removing the buffer layer, And removing the second sidewall spacers. The method of claim 1, After forming the first sidewall spacer, The method of forming a transistor of a semiconductor device, characterized in that to further perform channel implantation (channel implantation). The method of claim 1, Forming a gate oxide film and a gate in the trench, Forming a gate oxide film in the trench; Forming a polysilicon layer in the trench above the gate oxide layer; And forming a gate by performing a chemical mechanical polishing (CMP) process using the silicon nitride film as an end point. The method of claim 1, And the nitride film is etched by a wet etching method. The method of claim 1, And the first sidewall spacer is formed of an oxidizing material. The method of claim 1, And the second sidewall spacer is formed of silicon nitride.

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