KR100967485B1 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device according to an embodiment includes forming a first insulating film, a second insulating film, and a third insulating film on a semiconductor substrate; Forming a first trench in a third insulating film to expose the second insulating film; Forming a second trench having a narrower width than the first trench in the second insulating layer to expose the first insulating layer, and forming a spacer on the second insulating layer exposed by the first trench and on the sidewalls of the first trench. ; Forming an implant region in the semiconductor substrate region under the second trench and removing the spacers; Forming a third trench in the first insulating layer that is wider than the second trench so that the semiconductor substrate is exposed; Forming a gate oxide layer on the third trench and forming a gate conductor on the second trench and the first trench; And removing the second insulating layer and the third insulating layer, and forming a source region and a drain region on the semiconductor substrate using the gate conductor as an ion implantation mask.

Semiconductor device, implant region, gate oxide, gate conductor, short channel

Description

Semiconductor device and manufacturing method of semiconductor device

The embodiment relates to a semiconductor device and a method for manufacturing the semiconductor device.

As high integration of semiconductor devices proceeds, performance becomes increasingly difficult. For example, in the case of a MOS transistor, the channel length is also reduced because the size of the gate / source / drain electrodes is reduced.

In general, a semiconductor device has a lightly doped drain (LDD) structure, in which a spacer is formed on both sidewalls of a gate electrode, and the LDD region is formed to partially overlap the source / drain region.

At this time, sidewalls are formed on both sides of the gate electrode to relieve stress between the spacer and the electrode and to increase adhesiveness, and then spacers are formed through a process such as deposition, etching, and cleaning.

Since such semiconductor devices require a number of additional processes including a mask process, there is a high probability that a process error occurs and a lot of difficulty in forming a short channel.

For example, when various devices such as a plurality of PMOS transistors and NMOS transistors are integrated, the process is repeatedly performed such as formation of an n-type LDD pattern, n-type ion implantation, cleaning, formation of a p-type LDD pattern, p-type ion implantation, and cleaning. Should be dealt with.

In addition, defects are generated in the substrate and semiconductor layers during the ion implantation process to form the LDD region, the ion implantation equipment is expensive, the configuration of the equipment is complicated and difficult to operate, and the manager is exposed to poison gas and high voltage. There is a problem such as that.

In addition, when the n-type LDD region is formed and the cleaning process is performed, part of the oxide film of the polysilicon layer is lost, and therefore the oxidation process must be processed before the p-type ion is implanted.

As such, a general semiconductor device requires a complicated process, a lot of process efficiency is reduced, and production time and cost are high.

The embodiment provides a semiconductor device and a method of manufacturing the semiconductor device that can easily implement a short channel through a simple process and can minimize defects that may occur in the semiconductor layer during the process.

A method of manufacturing a semiconductor device according to an embodiment includes forming a first insulating film, a second insulating film, and a third insulating film on a semiconductor substrate; Forming a first trench in a third insulating film to expose the second insulating film; Forming a second trench having a narrower width than the first trench in the second insulating layer to expose the first insulating layer, and forming a spacer on the second insulating layer exposed by the first trench and on the sidewalls of the first trench. ; Forming an implant region in the semiconductor substrate region under the second trench and removing the spacers; Forming a third trench in the first insulating layer that is wider than the second trench so that the semiconductor substrate is exposed; Forming a gate oxide layer on the third trench and forming a gate conductor on the second trench and the first trench; And removing the second insulating layer and the third insulating layer, and forming a source region and a drain region on the semiconductor substrate using the gate conductor as an ion implantation mask.

In an embodiment, a semiconductor device may include a gate oxide film formed on a portion of a semiconductor substrate; A first insulating film formed on the remaining region of the semiconductor substrate on which the gate oxide film is not formed; A gate conductor including a first gate conductor formed on the gate oxide layer and a second gate conductor formed on the first gate conductor and wider than the first gate conductor; An implant region formed in the semiconductor substrate region below the first gate conductor; A source region and a drain region formed in the semiconductor substrate region outside the first gate conductor.

According to the embodiment, the following effects are obtained.

First, the short channel can be easily implemented through a simple process, and the width of the short channel can be finely adjusted.

Second, defects that may occur in the semiconductor layer during the process may be minimized.

Third, it is not necessary to operate additional equipment, such as an ion implantation device, the operation is easy, and the task manager can prevent the risk of exposure to poison gas and high voltage.

Fourth, since the manufacturing process of the semiconductor device can be significantly reduced, the process efficiency is increased, the production time and cost can be reduced.

A semiconductor device and a method of manufacturing the semiconductor device according to the embodiment will be described with reference to the accompanying drawings.

First, the shape of a semiconductor device completed by the method of manufacturing a semiconductor device according to the embodiment is shown in FIG.

Referring to FIG. 8, the semiconductor device according to the embodiment may include a semiconductor substrate 100, a gate oxide film 170 formed on a portion of the semiconductor substrate 100, and the semiconductor on which the gate oxide film 170 is not formed. An implant region formed in the first insulating layer 110 formed in the remaining region of the substrate 100, the gate conductor 180 formed on the gate oxide layer 170, and the semiconductor substrate 100 under the gate conductor 180. 160, a source region 192 and a drain region 194 formed at both sides of the implant region 160, respectively.

In addition, the gate conductor 180 is formed on the first gate conductor 182 and the first gate conductor 182 formed in the center portion of the gate oxide film 170 and is wider than the first gate conductor 182. And a two gate conductor 184.

Thus, the gate conductor 180 has a "T" shape.

In addition, the implant region 160 is formed in an area of the semiconductor substrate 100 under the first gate conductor 182, and the source region 192 and the drain region 194 are formed of the first gate conductor ( 182 is formed in an area of the semiconductor substrate 100 outside.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment will be described in detail with reference to the accompanying drawings.

FIG. 1 is a side cross-sectional view illustrating a shape of a semiconductor device after a first trench 135 is formed according to an embodiment.

First, the first insulating film 110, the second insulating film 120, and the third insulating film 130 are sequentially stacked on the semiconductor substrate 100, for example, a single crystal silicon substrate.

In this case, the first insulating film 110 is formed of an oxide film, the second insulating film 120 is formed of a nitride film, and the third insulating film 130 has an etching selectivity different from that of the first insulating film 110. It is formed of an oxide film.

For example, the first insulating layer 110 and the third insulating layer 130 may be formed of an oxide layer such as BSG (Boro-Silicate Glass) or Phosphos-Silicate Glass (PSG) having different etching selectivity.

Subsequently, a photoresist layer is formed on the third insulating layer 130, and a photoresist pattern 140 having an opening of the first trench 135 region is formed through a photolithography process.

When the photoresist pattern 140 is formed, the first trench 135 is formed in the third insulating layer 130 by performing an etching process using the photoresist pattern 140 as an etching mask.

For example, the first trench 135 may be formed through a dry etching process.

Therefore, a portion of the second insulating layer 120 is exposed by the first trench 135. Thereafter, the photoresist pattern 140 is removed.

2 is a side cross-sectional view illustrating the shape of a semiconductor device after the spacer layer 150 is formed according to the embodiment.

When the first trench 135 is formed, a spacer layer 150 is formed along an inner surface of the first trench 135 and an upper surface of the third insulating layer 130.

That is, the spacer layer 150 is formed along the surface of the third insulating layer 130 and the surface of the second insulating layer 120 exposed by the first trench 135, and the first trench 135. It may have a trench structure corresponding to.

Hereinafter, the trench reflected when the spacer layer 150 is stacked is referred to as a “spacer trench”.

For example, the spacer layer 150 may be formed of SiN material.

3 is a side cross-sectional view illustrating the shape of a semiconductor device after the spacer 155 and the second trench 125 are formed according to the embodiment.

Subsequently, a part of the spacer layer 150 and the second insulating layer 120 are removed by exposing the entire surface etching process to expose a part of the first insulating layer 110.

In this case, the spacer layer 150 formed on the third insulating layer 130, the spacer layer 150 corresponding to the bottom surface of the spacer trench and the second insulating layer 120 are etched together to form a second trench 125. ) And a spacer 155 are formed.

That is, a portion of the first insulating layer 110 may be exposed by the second trench 125, and the second trench 125 may be formed to have a narrower width than the first trench 135.

Accordingly, the spacer 155 may be formed on the second insulating layer 120 and the sidewalls of the first trench 135 that are exposed by the first trench 135 and formed in the second trench 125. .

In addition, due to the etching characteristic of the edge portion of the spacer trench, the spacer 155 has a rounded shape.

Thereafter, an ion implantation process is performed using the spacer 155 and the third insulating layer 130 as an ion implantation mask.

Accordingly, the implant region 160 is formed by implanting impurity ions into the semiconductor substrate 100 between the spacers 155.

The implant region 160 may be formed through at least one implant process among a pocket implant and a channel implant, and form a short channel region of a semiconductor device according to an embodiment.

In this case, the first insulating layer 110 may be used as a buffer layer in an ion implantation process.

4 is a side cross-sectional view illustrating the shape of a semiconductor device after the spacer 155 is removed according to the embodiment.

The spacer 155 defines the size of the implant region 160 and is used as an ion implantation mask. After the implant region 160 is formed, the spacer 155 is removed as shown in FIG. 4.

The spacer 155 may be removed by a wet etching process using a nitride film etching solution, such as a phosphoric acid solution, and thus the third insulating layer 130 may be preserved without being removed.

5 is a side cross-sectional view illustrating the shape of a semiconductor device after the third trench 115 is formed according to the embodiment.

Subsequently, a part of the first insulating layer 110 is removed by performing a wet etching process using an oxide film etching solution. Thus, a third trench 115 is formed in the first insulating layer 110.

In this case, as described above, since the etching selectivity of the first insulating layer 110 and the third insulating layer 130 are different from each other, only the first insulating layer 110 may be etched, and the second insulating layer 120 is a nitride layer. ) Is not etched and is preserved.

Accordingly, as illustrated in FIG. 5, the third trench 115 having a width similar to that of the first trench 135 and having a width wider than that of the second trench 125 may be formed.

6 is a side cross-sectional view illustrating the shape of a semiconductor device after the gate conductor 130 according to the embodiment is formed.

When the third trench 115 is formed, a gate oxide film 170 is formed by forming an oxide film on the third trench 115 in an oxidation process.

The gate oxide film 170 may be formed of a material such as SiO ₂ .

Next, a polysilicon layer is stacked on the third insulating layer 130 by filling the first trench 135 and the second trench 125, and using the third insulating layer 130 as an etch stop layer. As a result, the polysilicon layer on the third insulating layer 130 is planarized.

The planarization process may be performed through a polishing process such as chemical mechanical polishing (CMP).

As such, the polysilicon layer on the third insulating layer 130 is planarized to form the gate conductor 180 as shown in FIG. 6.

The polysilicon layer embedded in the second trench 125 has a narrower width than the polysilicon layer embedded in the first trench 135 and supports a polysilicon layer embedded in the first trench 135. Has

Therefore, the gate conductor 180 has a "T" shape.

Hereinafter, the polysilicon layer formed on the second trench 125 is referred to as “first gate conductor 182”, and the polysilicon layer formed on the first trench 135 is referred to as “second gate conductor 184”. do.

7 is a side cross-sectional view illustrating the shape of a semiconductor device after the second insulating film 120 and the third insulating film 130 are removed according to the embodiment.

When the gate conductor 180 is formed, the third insulating layer 130 is removed by performing a wet etching process using an oxide film removing solution, and the second insulating layer 120 is performed by performing a wet etching process using a nitride removing solution. Remove it.

For example, the second insulating layer 120 may be removed through a phosphoric acid solution.

Therefore, the first insulating layer 110 formed of an oxide layer may be used as an etch stop layer of the second insulating layer 120.

Through this process, as shown in FIG. 7, only the gate conductor 180 remains.

8 is a side cross-sectional view illustrating the shape of a semiconductor device after the source region 192 and the drain region 194 are formed in the semiconductor substrate 100 according to the embodiment.

Subsequently, using the gate conductor 180 as an ion implantation mask, P-type impurities such as boron (B) ions are implanted in the active region of the semiconductor substrate 100 with ion implantation energy of 3 to 20 KeV, and 1 × 10 ¹⁵ ~ then implanted at an ion implantation density of 5 × 10 ¹⁵ ions / cm ^2.

Thus, the source region 192 and the drain region 194 are formed.

For reference, in the case of forming the source region 192 and the drain region 194 of the NMOS transistor, for example, arsenide (As) ions may be ion implanted.

In this case, the source region 192 and the drain region 194 are thickened by transferring ions to an area outside the second gate conductor 184.

In addition, a portion of the ions enter the space between the first gate conductor 182 and the second gate conductor 184, so that the ends of the source region 192 and the drain region 194 are curved. The first gate conductor 182 may be formed to both sides.

As such, according to the exemplary embodiment, the profile of the source region 192 and the drain region 194 may be finely controlled by adjusting the thickness and width of the first gate conductor 182 and the second gate conductor 184. Can be.

For example, the thickness of the first gate conductor 182 and the second gate conductor 184 by adjusting the size of the first trench 135, the second trench 125, and the spacer layer 150. And width can be adjusted.

In addition, the size of the gate conductor 180 may be adjusted according to the type of semiconductor device according to the embodiment, and as described above, various profiles of the source region 192 and the drain region 194 may be formed. .

In addition, according to the embodiment, since the source / drain region having the sophisticated short channel structure can be directly formed without the need for separately forming the LDD region, defects that may occur in the semiconductor layer during the process can be minimized, and the semiconductor device It is possible to significantly reduce the manufacturing process of the.

Thereafter, the semiconductor device according to the embodiment as shown in FIG. 8 is completed by treating the subsequent thermal process.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications other than those described above are possible. For example, each component specifically shown in the embodiments of the present invention can be modified and implemented. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

1 is a side cross-sectional view illustrating the shape of a semiconductor device after a first trench is formed in accordance with an embodiment.

2 is a side cross-sectional view illustrating the shape of a semiconductor device after the spacer layer according to the embodiment is formed.

3 is a side cross-sectional view illustrating the shape of a semiconductor device after the spacer and the second trench are formed according to the embodiment;

4 is a side cross-sectional view illustrating the shape of a semiconductor device after the spacer according to the embodiment is removed.

FIG. 5 is a side cross-sectional view illustrating a shape of a semiconductor device after a third trench according to the embodiment is formed. FIG.

6 is a side cross-sectional view illustrating the shape of a semiconductor device after the gate conductor according to the embodiment is formed.

7 is a side cross-sectional view illustrating the shape of a semiconductor device after the second insulating film and the third insulating film are removed according to the embodiment;

8 is a side cross-sectional view illustrating the shape of a semiconductor device after source and drain regions are formed in a semiconductor substrate according to the embodiment;

Claims (8)

Forming a first insulating film, a second insulating film, and a third insulating film on the semiconductor substrate; Forming a first trench in a third insulating film to expose the second insulating film; Forming a second trench having a narrower width than the first trench in the second insulating layer to expose the first insulating layer, and forming a spacer on the second insulating layer exposed by the first trench and on the sidewalls of the first trench. ; Forming an implant region in the semiconductor substrate region under the second trench and removing the spacers; Forming a third trench in the first insulating layer that is wider than the second trench so that the semiconductor substrate is exposed; Forming a gate oxide layer on the third trench and forming a gate conductor on the second trench and the first trench; And Removing the second insulating layer and the third insulating layer, and forming a source region and a drain region on the semiconductor substrate using the gate conductor as an ion implantation mask. The method of claim 1, wherein the forming of the first trench Forming a photoresist layer on the third insulating film; Patterning the photoresist layer to form a photoresist pattern in which the first trench regions are opened; Etching the first trench in the third insulating layer using the photoresist pattern as an etching mask; And Removing the photoresist pattern. The method of claim 1, wherein the forming of the second trench and the spacer is performed. Forming a spacer layer along a surface of the third insulating film and a surface of the second insulating film exposed by the first trench; And And forming the second trench and the spacer by removing a portion of the spacer layer and the second insulating layer through an entire surface etching process and exposing a portion of the first insulating layer. The method of claim 1, wherein in the step of removing the spacer And wherein the implant region is formed by subjecting the semiconductor substrate between the spacers to a process of at least one implant of a pocket implant or a channel implant. The method of claim 1, And the first insulating film is an oxide film, the second insulating film is a nitride film, and the third insulating film is an oxide film having an etching selectivity different from that of the first insulating film. The method of claim 1, wherein the forming of the gate conductor Forming a polysilicon layer on the third insulating layer by filling the first trench and the second trench; And And forming the gate conductor by planarizing the polysilicon layer on the third insulating layer by using the third insulating layer as an etch stop layer. The method of claim 5, wherein the forming of the source region and the drain region is performed. And the second insulating film is removed using a phosphoric acid solution. A gate oxide film formed in a portion of the semiconductor substrate; A first insulating film formed on the remaining region of the semiconductor substrate on which the gate oxide film is not formed; A gate conductor formed on the gate oxide film and having a narrower width than the gate oxide film, and a second gate conductor formed on the first gate conductor and wider than the first gate conductor; An implant region formed in the semiconductor substrate region below the first gate conductor; And a source region and a drain region formed in the semiconductor substrate region outside the first gate conductor.

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