KR20050118548A - Method for manufacturing self-aligned recess channel mosfet - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a self-aligned recess channel MOSFET, and more particularly, to form a hard mask and a buffer layer pattern that opens a channel region of a MOSFET on a semiconductor substrate, and to form a spacer on a pattern sidewall of the hard mask and the buffer layer. Forming a recess region by forming and etching the semiconductor substrate exposed by the hard mask pattern and the spacer to a predetermined depth; forming a gate insulating film on the entire surface of the structure after removing the spacer; Gap-filling a conductive film in the recess region and performing a chemical mechanical polishing process; and removing a portion of the gate insulating layer, a hard mask, and a buffer layer to form an etched gate insulating layer and a gate electrode on the semiconductor substrate in the recess region. It is made to include. Therefore, the present invention can use the spacer as a mask to etch the recessed region, facilitate alignment between the gate electrode and the channel, and prevent etch damage of the gate electrode.

Description

METHOD FOR MANUFACTURING SELF-aligned recess channel MOSFET

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a self-aligned recess channel MOSFET applicable to a semiconductor device, a semiconductor memory device, and the like.

In general, a MOSFET is a field effect transistor in which a gate electrode formed on a semiconductor substrate is separated by a thin insulating film, and is a semiconductor device having characteristics suitable for high density integration without a decrease in impedance, such as a junction transistor.

However, in recent years, as the integration of semiconductor devices increases, the size of the devices decreases, so that the threshold voltage of the transistors decreases, resulting in short channel effects or at the edges of the active regions during shallow trench isolation processes. Inverse Narrow Width Effect (INWE) due to the problem is intensified. This results in leakage current characteristics in the sub-threshold and off-regions of the MOSFET and causes deterioration of the characteristics of the semiconductor device. For example, it causes a refresh or degradation of data retention time characteristics of the DRAM.

Therefore, there is a method of increasing the doping concentration of the semiconductor substrate as a method for suppressing the reduction of the threshold voltage of the highly integrated MOSFET, but this causes another problem of increasing the leakage current of the impurity junction.

Recently, recess channel MOSFETs have been introduced that can reduce the threshold voltage by increasing the channel length without increasing the doping concentration of the semiconductor substrate. In the method of manufacturing the recess channel MOSFET, the channel length is increased in the vertical direction by etching the semiconductor substrate serving as the channel region to form a recess region and forming a gate electrode on the semiconductor substrate of the recess region. In other words, since the effective channel length is increased by the length of the vertically etched semiconductor substrate, it is possible to secure the short channel without increasing the doping concentration in the channel region, thereby preventing degradation of characteristics such as the DRAM release or data retention time. do.

However, the conventional method of manufacturing a recess channel MOSFET requires a photolithography and an etching process to form a recess region in the semiconductor substrate, and even when the gate electrode is formed in the semiconductor substrate of the recess region, the gap between the gate electrode and the channel is lost. The phosphorus must be precisely aligned.

SUMMARY OF THE INVENTION An object of the present invention is to form a recess region by etching a semiconductor substrate exposed by sidewall spacers of an etch pattern in order to solve the problems of the prior art as described above. By using a spacer as a mask, the recess region can be etched, and a method of fabricating a self-aligned recess channel MOSFET capable of facilitating alignment between the gate electrode and the channel and preventing etch damage of the gate electrode is provided. It is.

In accordance with an aspect of the present invention, a method of manufacturing a recess channel MOSFET includes: forming a hard mask and a buffer layer pattern on a semiconductor substrate to open a channel region of the MOSFET; Forming a recess on the pattern sidewalls of the hard mask and the buffer layer, and etching the semiconductor substrate exposed by the hard mask pattern and the spacer to a predetermined depth to form a recessed region; Performing a chemical mechanical polishing process by gap-filling a conductive film between the pattern of the hard mask and the buffer layer and in the recess region, and removing a portion of the gate insulating layer and the hard mask and the buffer layer to etch the upper portion of the recessed semiconductor substrate. Forming a gate insulating film and a gate electrode; It is done.

According to another aspect of the present invention, there is provided a method of manufacturing a recess channel MOSFET, the method including forming a hard mask and a buffer layer pattern on the semiconductor substrate to open a channel region of the MOSFET; Forming a recessed region by forming a spacer on the sidewalls of the hard mask and the buffer layer and etching the semiconductor substrate exposed by the hard mask pattern and the spacer to a predetermined depth, forming a gate insulating layer on the entire surface of the structure; Gap-filling the conductive film between the hard mask and buffer layer patterns and in the recess region, and performing a chemical mechanical polishing process, and removing a portion of the gate insulating layer, the spacer, the hard mask and the buffer layer, and etching the gate over the semiconductor substrate in the recess region. And forming an insulating film and a gate electrode. Characterized in that byte having a side wall electrode and the gate insulating film below.

In accordance with still another aspect of the present invention, there is provided a method of manufacturing a recess channel MOSFET, including forming a hard mask and a buffer layer pattern on the semiconductor substrate to open a channel region of the MOSFET. Forming a recessed region by forming a spacer on the sidewalls of the hard mask and the buffer layer and etching the semiconductor substrate exposed by the hard mask pattern and the spacer to a predetermined depth, and forming a gate insulating layer on the entire surface of the structure; Gap-filling the conductive film between the hard mask and buffer pattern patterns and in the recess region, and performing a chemical mechanical polishing process, and removing a portion of the gate insulating layer and the spacer, the hard mask and the buffer layer, and etching the upper portion of the recessed semiconductor substrate. A gate insulating film and a gate electrode are formed, and the It comprises the step leaves the document.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1H are process flowcharts for sequentially explaining a method of manufacturing a self-aligned recess channel MOSFET according to an embodiment of the present invention. Referring to these drawings, the MOSFET manufacturing method of the self-aligned recess channel according to the exemplary embodiment of the present invention proceeds as follows.

First, as shown in FIG. 1A, as a semiconductor substrate 10, a thin silicon oxide film SiO 2 is deposited as a buffer layer 12 on a silicon substrate and a hard mask 14 thereon. As a result, a thick silicon nitride film (Si3N4) is deposited.

Then, a photoresist is applied on the hard mask 14 and the photoresist pattern 16 is formed by performing an exposure and development process using a mask defining a channel region of the MOSFET.

As shown in FIG. 1B, the hard mask 14 and the buffer layer 12 corresponding to the channel region of the MOFET opened by the photoresist pattern 16 are sequentially dry-etched and patterned. As a result, the hard mask 14 and the buffer film 12 pattern under the photoresist pattern 16 are formed.

As shown in FIG. 1C, when the photoresist pattern is removed by an ashing process, the surface of the semiconductor substrate 10 corresponding to the channel region of the MOSFET is exposed by the pattern of the hard mask 14 and the buffer layer 12. do.

As shown in FIG. 1D, a silicon oxide film (SiO 2) is deposited as an insulating film on the entire surface of the structure and etched by an etch back process to form a spacer on the pattern sidewalls of the hard mask 14 and the buffer film 12. spacer 18). In this case, the spacer 18 may be formed of another film having an etching selectivity with respect to the hard mask 14, for example, a polysilicon film, instead of the silicon oxide film, and may be formed of the same material as the hard mask 14. . In the present invention, the width of the spacer 18 is preferably adjusted according to the size of the recess region of the MOSFET to be formed on the semiconductor substrate.

Subsequently, the dry etching process using the hard mask 14 pattern and the spacer 18 is performed to etch the semiconductor substrate 10 to a predetermined depth, for example, 1000 °. Etch as much as As a result, a recess region 20 of a groove in which the semiconductor substrate 10 exposed by the spacer 18 is etched to a predetermined depth is formed.

As shown in FIGS. 1E and 1F, after the spacers are removed, a thin silicon oxide film SiO 2 is deposited as the gate insulating film 22 on the entire surface of the structure.

As shown in FIG. 1G, a doped polysilicon film 24 is deposited as a conductive film so as to sufficiently gap-fill between the patterns of the hard mask 14 and the buffer film 12 and between the recess regions. . Then, the chemical mechanical polishing (CMP) process is performed to etch the doped polysilicon layer 24 until the surface of the gate insulating layer 22 is exposed. As a result, a gate electrode of the doped polysilicon film 24 gap-filled between the patterns of the hard mask 14 and the buffer film 12 and in the recess region is formed.

Then, when the dry etching process of a portion of the gate insulating film 22, the hard mask 14 and the buffer film 12 is performed, as shown in Figure 1h, the gate insulating film etched on the semiconductor substrate 10 of the recess region Only 22a and the gate electrode 24 are sequentially stacked.

Subsequently, although not shown in the drawings, an LDD and source / drain ion implantation process is performed to form an LDD and source / drain junction region on the side of the semiconductor substrate 10 of the recess region in which the gate electrode 24 is provided. Complete the MOSFET of the channel structure.

2A to 2G are process flowcharts for sequentially explaining a method of manufacturing a self-aligned recess channel MOSFET according to another exemplary embodiment of the present invention. Referring to these drawings, a method of fabricating a MOSFET of a self-aligned recess channel according to another exemplary embodiment of the present invention proceeds as follows.

As shown in FIG. 2A, as the semiconductor substrate 10, a thin silicon oxide film SiO 2 is deposited as a buffer film 102 on the silicon substrate, and a silicon nitride film Si 3 N 4 is thickly deposited as a hard mask 104 thereon. do.

The photoresist is applied on the hard mask 104 and the photoresist pattern 106 is formed by performing an exposure and development process using a mask defining a channel region of the MOSFET.

As shown in FIG. 2B, the hard mask 104 and the buffer film 102 corresponding to the channel region of the MOFET opened by the photoresist pattern 106 are sequentially dry-etched and patterned. As a result, the hard mask 104 and the buffer film 102 patterns under the photoresist pattern 106 are formed.

As shown in FIG. 2C, when the photoresist pattern is removed by an ashing process, the surface of the semiconductor substrate 100 corresponding to the channel region of the MOSFET is exposed by the patterns of the hard mask 104 and the buffer layer 102.

As shown in FIG. 2D, a silicon oxide film (SiO 2) is deposited as an insulating film on the entire surface of the structure and etched by an entire etching process to form spacers 108 on the pattern sidewalls of the hard mask 104 and the buffer film 102. do. In the present invention, the width of the spacer 108 is preferably adjusted to the recess region of the MOSFET to be formed on the semiconductor substrate.

Subsequently, the dry etching process using the hard mask 104 pattern and the spacer 108 is performed to etch the semiconductor substrate 100 to a certain depth, for example, 1000 °. Etch as much as As a result, the recess region 110 of the groove in which the semiconductor substrate 100 exposed by the spacer 108 is etched to a predetermined depth is formed.

Subsequently, as illustrated in FIG. 2E, a thin silicon oxide film (SiO 2) is deposited as the gate insulating layer 112 on the entire structure.

As shown in FIG. 2F, a doped polysilicon film 24 is deposited as a conductive film so as to sufficiently fill the gap between the patterns of the hard mask 14 and the buffer film 12 and between the recessed regions, and chemical mechanical polishing ( CMP) process is performed to etch the doped polysilicon film 114 until the surface of the gate insulating film 112 is exposed. As a result, a gate electrode of the doped polysilicon film 114 gap-filled between the patterns of the hard mask 104 and the buffer film 102 and in the recess region is formed.

Thereafter, a portion of the gate insulating layer 112, the spacer 108, the hard mask 104, and the buffer layer 102 are subjected to dry etching using the gate electrode 114 as a mask. Then, as illustrated in FIG. 2G, the etched gate insulating layer 112a and the gate electrode 114 are stacked on the semiconductor substrate 100 in the recess region. In this case, the gate insulating layer 112a of the recess region is vertically formed on the side surface of the gate electrode 114.

Next, although not shown in the drawings, a self-aligned recess channel is formed by forming an LDD and a source / drain junction region in the semiconductor substrate 100 on the side of the gate electrode 114 by performing an LDD and source / drain ion implantation process. Complete the MOSFET of structure.

Since the MOSFET according to another embodiment does not remove the gate insulating layer 112a at the side of the gate electrode 114, the inner gate having a smaller size than the channel of the recess region in which the semiconductor substrate is etched is formed. (inner gate) has an electrode structure.

3 is a vertical cross-sectional view illustrating a method of manufacturing a self-aligned recess channel MOSFET according to still another embodiment of the present invention. Referring to FIG. 3, in the manufacturing method according to another exemplary embodiment of the present invention, a dry etching process is performed using the gate electrode 114 as a mask in the above-described embodiment of FIG. 2F to form a portion of the gate insulating layer 112 and a hard mask ( The spacer 108a is partially left on the sidewalls of the gate electrode 114 while the 104 and the buffer layer 102 are removed.

Therefore, in the MOSFET according to another embodiment of the present invention, the gate insulating layer 112a and the spacer 108a remain on the sidewall of the gate electrode 114 having the recess channel structure to be used as an offset of the gate electrode 114. Can be.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

As described above, the present invention uses the spacer as a mask by etching the semiconductor substrate exposed by the sidewall spacer of the etch pattern to form a recessed region, and removing the spacer, forming a gate insulating film and a gate electrode in the recessed region. The recess region may be etched, and the alignment between the gate electrode and the channel may be easily facilitated, and the etching damage of the gate electrode may be prevented.

1A to 1H are process flowcharts for sequentially explaining a method of manufacturing a self-aligned recess channel MOSFET according to an embodiment of the present invention;

2A to 2G are process flowcharts for sequentially explaining a method of manufacturing a self-aligned recess channel MOSFET according to another embodiment of the present invention;

3 is a vertical cross-sectional view for explaining a method of manufacturing a self-aligned recess channel MOSFET according to still another embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

10 semiconductor substrate 12 buffer film

14 Hard Mask 16 Photoresist Pattern

18: spacer 20: recessed area

22, 22a: gate insulating film 24: gate electrode

Claims (3)

In the method of manufacturing the MOSFET of the recess channel, Forming a hard mask and a buffer film pattern on the semiconductor substrate to open the channel region of the MOSFET; Forming a recess on the pattern sidewalls of the hard mask and the buffer layer, and etching the semiconductor substrate exposed by the hard mask pattern and the spacer to a predetermined depth to form a recess region; Forming a gate insulating film on the entire surface of the structure after removing the spacers; Gap-filling a conductive film for a gate electrode between the pattern of the hard mask and the buffer layer and in the recess region, and performing a chemical mechanical polishing process; And And removing a portion of the gate insulating layer, the hard mask, and the buffer layer to form an etched gate insulating layer and a gate electrode on the semiconductor substrate in the recess region. . In the method of manufacturing the MOSFET of the recess channel, Forming a hard mask and a buffer film pattern on the semiconductor substrate to open the channel region of the MOSFET; Forming a recess on the pattern sidewalls of the hard mask and the buffer layer, and etching the semiconductor substrate exposed by the hard mask pattern and the spacer to a predetermined depth to form a recess region; Forming a gate insulating film on the entire surface of the structure; Gap-filling a conductive film for a gate electrode between the pattern of the hard mask and the buffer layer and in the recess region, and performing a chemical mechanical polishing process; And And removing a portion of the gate insulating layer, the spacer, the hard mask, and the buffer layer to form an etched gate insulating layer and a gate electrode on the semiconductor substrate in the recess region. And a gate insulating film formed on sidewalls of the gate electrode and under the gate electrode. In the method of manufacturing the MOSFET of the recess channel, Forming a hard mask and a buffer film pattern on the semiconductor substrate to open the channel region of the MOSFET; Forming a recess on the pattern sidewalls of the hard mask and the buffer layer, and etching the semiconductor substrate exposed by the hard mask pattern and the spacer to a predetermined depth to form a recess region; Forming a gate insulating film on the entire surface of the structure; Gap-filling a conductive film for a gate electrode between the pattern of the hard mask and the buffer layer and in the recess region, and performing a chemical mechanical polishing process; And Removing the gate insulating layer and a portion of the spacer, the hard mask and the buffer layer to form an etched gate insulating layer and a gate electrode on the semiconductor substrate in the recess region, and leaving a spacer on the sidewall of the gate electrode. Self-aligned recess channel MOSFET manufacturing method.