KR100817712B1 - Method of forming a high voltage MOS device - Google Patents

Method of forming a high voltage MOS device Download PDF

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KR100817712B1
KR100817712B1 KR1020020010910A KR20020010910A KR100817712B1 KR 100817712 B1 KR100817712 B1 KR 100817712B1 KR 1020020010910 A KR1020020010910 A KR 1020020010910A KR 20020010910 A KR20020010910 A KR 20020010910A KR 100817712 B1 KR100817712 B1 KR 100817712B1
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forming
nitride film
trench
high voltage
ion implantation
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KR20030071275A (en
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주재일
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]

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Abstract

본 발명은 집적도가 높은 조건에서도 효과적으로 채널길이를 확보할 수 있는 고전압 모스 소자의 제조 방법에 관한 것이다. 이를 위해, 먼저, 반도체 기판 위에 절연막을 형성하고, 사진공정 및 이온주입을 반복하여 서로 다른 웰 영역을 형성하며, 상기 절연막 위에 질화막을 증착하고, 포토공정을 수행하여 상기 질화막을 건식식각한 후 트렌치를 형성한다. 상기 트렌치 형성 후 게이트 산화를 실시하고 폴리실리콘을 반도체 기판 전면에 걸쳐서 증착하여 게이트 전극을 형성하며, 포토레지스트를 도포하여 필드산화막 형성을 위한 사진공정을 실시하고, 상기 포토레지스트에 의해 노출된 질화막을 식각한다. 그리고, 상기 질화막에 의해 노출된 부분에 필드산화막을 형성한 후 상기 질화막을 제거하고, 이온주입에 의해 소스 및 드레인 영역 형성을 위한 제 1 불순물을 주입하며, 상기 제 1 불순물 영역 위에 제 2 불순물 영역 형성을 위한 이온주입이 이루어지게 된다.The present invention relates to a method for manufacturing a high voltage MOS device capable of effectively securing a channel length even under high integration conditions. To this end, first, an insulating film is formed on a semiconductor substrate, and the photo well process and ion implantation are repeated to form different well regions, a nitride film is deposited on the insulating film, and a photo process is performed to dry-etch the nitride film, followed by a trench. To form. After the trench is formed, gate oxidation is performed, polysilicon is deposited over the entire surface of the semiconductor substrate to form a gate electrode, a photoresist is applied to perform a photo process for forming a field oxide film, and a nitride film exposed by the photoresist is formed. Etch it. After forming the field oxide film on the portion exposed by the nitride film, the nitride film is removed, a first impurity for implanting the source and drain regions is implanted by ion implantation, and a second impurity region is formed on the first impurity region. Ion implantation is made for formation.

이에 따라, 트렌치 구조를 적용하여 게이트 전극을 형성함으로써 소자 사이즈 대비 채널 길이를 효과적으로 확대할 수 있으며, 고밀도 소자설계에 의한 집적도를 높이는 효과가 있다.Accordingly, by forming a gate electrode by applying a trench structure, the channel length can be effectively enlarged compared to the device size, and the integration density due to the high density device design can be increased.

고전압소자, 모스, 트렌치, 소자분리, 채널길이, 반도체High voltage device, MOS, trench, device isolation, channel length, semiconductor

Description

고전압 모스 소자의 제조 방법{Method of forming a high voltage MOS device}Method of manufacturing a high voltage MOS device

도 1은 종래의 고전압 소자 중 수평형 이중확산 모스 소자의 구조를 보여주는 도면이다.1 is a view showing the structure of a horizontal double diffusion MOS device of the conventional high voltage device.

도 2는 종래의 고전압 소자 중 수직형 이중확산 모스 소자의 구조를 보여주는 도면이다.2 is a view showing the structure of a vertical double diffusion MOS device of the conventional high voltage device.

도 3a 내지 도 3h는 본 발명의 실시예에 의한 고전압 모스 소자의 제조 과정을 보여주는 공정 단면도이다.3A to 3H are cross-sectional views illustrating a manufacturing process of a high voltage MOS device according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

50 : 반도체 기판 52 : 실리콘 산화막50 semiconductor substrate 52 silicon oxide film

54 : N웰 영역 56 : P웰 영역54: N well area 56: P well area

58 : 질화막 62 : 트렌치58: nitride film 62: trench

64 : 게이트 전극 68 : 필드산화막64 gate electrode 68 field oxide film

72, 74, 78, 82 : 불순물 영역72, 74, 78, 82: impurity region

본 발명은 고전압 모스 소자의 제조 방법에 관한 것으로, 보다 상세하게는, 집적도가 높은 조건에서도 효과적으로 채널길이를 확보할 수 있는 고전압 모스 소자의 제조 방법에 관한 것이다.The present invention relates to a manufacturing method of a high voltage MOS device, and more particularly, to a manufacturing method of a high voltage MOS device capable of effectively securing a channel length even under high integration conditions.

근래 반도체 칩 사이즈가 더욱 축소되면서 고집적화되고, 고밀도 형성기술이 발전됨에 따라 고전압 소자의 크기를 효과적으로 축소하는 것 또한 중요한 요소로 작용하고 있다.In recent years, as semiconductor chip sizes have been further reduced, high integration and high density forming technologies have been developed, effectively reducing the size of high voltage devices is also an important factor.

종래의 고전압 소자는 모스 트랜지스터의 주요 파라미터인 Vtext, Idsat, BVdss 등 만족할 수 있는 소자 특성을 얻기 위해 효과적인 채널길이의 확보는 매우 중요한 요소이다. 그런데, 종래의 고전압 소자는 그 크기가 커서 고밀도 설계를 위한 문제점이 있었으며, 그에 따라 칩의 크기를 줄이는데 어려운 점이 있다.In the conventional high voltage device, it is very important to secure effective channel length in order to obtain satisfactory device characteristics such as Vtext, Idsat, BVdss, which are main parameters of the MOS transistor. However, the conventional high voltage device has a large size and has a problem for high-density design, which makes it difficult to reduce the size of the chip.

이러한 종래의 고전압 소자의 예로서, 먼저 도 1을 참조하면, 수평형 이중확산 모스 소자(LDMOS ; Lateral Double Diffused MOS)가 도시되어 있다.As an example of such a conventional high voltage device, first referring to FIG. 1, a horizontal double diffusion MOS device (LDMOS) is illustrated.

이 소자는 반도체 기판(10) 위에 N- 웰(12)이 형성되고, 여기에 게이트 영역(14), 소스 영역(16)과 드레인 영역(18)이 형성되어 있다. 그리고, 그 위에는 게이트 전극(20)이 형성되어 있다.In this device, an N-well 12 is formed on a semiconductor substrate 10, and a gate region 14, a source region 16, and a drain region 18 are formed thereon. The gate electrode 20 is formed thereon.

상기 이중확산 모스 소자의 채널길이는 l1이다.The channel length of the double diffusion MOS device is l1.

그리고, 도 2를 참조하면, 수직형 이중확산 모스 소자(VMOS ; Vertical Double Diffused MOS)가 도시되어 있다.In addition, referring to FIG. 2, a vertical double diffusion MOS device (VMOS) is illustrated.

이 소자는 기판 저부에 N+ 드레인 영역(30)이 형성되어 있고, 그 위에는 N- 영역(32)이 형성되어 있다. 상기 N- 영역에는 P 불순물 영역(34)들이 형성되어 있 고, P 불순물 영역(34) 내에는 N+ 불순물 영역(36)이 형성되어 있다. 그리고, 바디와 소스 전극 형성을 위한 폴리실리콘(38, 40)들이 형성되며, 또한 게이트 전극(42)이 형성된다. 이 경우의 채널길이는 l2이다.In this device, an N + drain region 30 is formed at the bottom of a substrate, and an N− region 32 is formed thereon. P impurity regions 34 are formed in the N− region, and N + impurity regions 36 are formed in the P impurity region 34. In addition, polysilicon layers 38 and 40 are formed to form a body and a source electrode, and a gate electrode 42 is formed. The channel length in this case is l2.

상기 수평형 및 수직형 이중확산 모스 소자의 예와 같이, 종래의 고전압 소자는 그 구조가 평면적인 구조를 취하고 있으므로 소자의 크기 축소에 어려운 부분이 있다. 즉, 상기한 채널길이 l1 및 l2와 같이 채널길이가 짧은 것과 같이, 효과적인 채널 길이를 확보하기가 어려우며, 그에 따라 고밀도로 집적된 소자를 확보하기가 용이하지 않다. 또한 채널 길이를 확보하기 위해서는 그에 따른 칩 사이즈가 커지게 되는 문제점이 있다.As in the above example of the horizontal and vertical double diffusion MOSFETs, the conventional high voltage device has a flat structure, and thus, there is a difficulty in reducing the size of the device. That is, it is difficult to secure an effective channel length, such as the short channel length, such as the channel lengths l1 and l2, and thus it is not easy to secure a high-density integrated device. In addition, to secure the channel length, there is a problem in that the chip size increases.

이와 같은 종래의 문제점을 해결하기 위한 본 발명의 목적은, 단위 소자 크기가 축소되면서도 소자의 특성이 유지되는 고전압 모스 트랜지스터를 얻기 위한 고전압 모스 소자의 제조 방법을 제공하는 것이다.SUMMARY OF THE INVENTION An object of the present invention for solving such a conventional problem is to provide a method for manufacturing a high voltage MOS device for obtaining a high voltage MOS transistor in which the characteristics of the device are maintained while the unit device size is reduced.

본 발명의 다른 목적은, 소자의 크기를 줄이는 상태에서도 트렌치 구조를 적용하여 채널길이가 확보되도록 하는 고전압 모스 소자의 제조 방법을 제공하는 것이다.It is another object of the present invention to provide a method of manufacturing a high voltage MOS device in which the channel length is secured by applying a trench structure even in a state in which the size of the device is reduced.

상기 목적을 달성하기 위한 본 발명에 의한 고전압 모스 소자의 제조 방법은, 반도체 기판 위에 절연막을 형성하고, 사진공정 및 이온주입을 반복하여 서로 다른 웰 영역을 형성하는 단계와, 상기 절연막 위에 질화막을 증착하고, 포토공정 을 수행하여 상기 질화막을 건식식각한 후 트렌치를 형성하는 단계와, 상기 트렌치 형성 후 게이트 산화를 실시하고, 폴리실리콘을 반도체 기판 전면에 걸쳐서 증착하여 게이트 전극을 형성하는 단계와, 포토레지스트를 도포하여 필드산화막 형성을 위한 사진공정을 실시하고, 상기 포토레지스트에 의해 노출된 질화막을 식각하는 단계와, 상기 질화막에 의해 노출된 부분에 필드산화막을 형성한 후 상기 질화막을 제거하고, 이온주입에 의해 소스 및 드레인 영역 형성을 위한 제 1 불순물을 주입하는 단계, 그리고, 상기 제 1 불순물 영역 위에 제 2 불순물 영역 형성을 위한 사진공정이 실시된 후 이온주입이 이루어지는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a high voltage MOS device according to the present invention includes forming an insulating film on a semiconductor substrate, repeating a photo process and ion implantation to form different well regions, and depositing a nitride film on the insulating film. Forming a trench after dry etching the nitride film by performing a photo process, performing gate oxidation after forming the trench, and depositing polysilicon over the entire surface of the semiconductor substrate to form a gate electrode; Performing a photolithography process to form a field oxide film by applying a resist; etching the nitride film exposed by the photoresist; forming a field oxide film on the portion exposed by the nitride film, removing the nitride film, and Implanting a first impurity for source and drain region formation by implantation, and Characterized in that the group includes a first impurity region formed of the second impurity region ion implantation step after the photolithography process carried out for the formation over.

상기 트렌치는 상기 서로 다른 웰 영역에 각각 형성되는 것이 바람직하며, 이로써 상기 소스와 드레인 사이의 채널길이가 확대되도록 한다.The trenches are preferably formed in the different well regions, thereby allowing the channel length between the source and the drain to be enlarged.

이하, 본 발명의 실시예에 대한 설명은 첨부된 도면을 참조하여 더욱 상세하게 설명한다. 아래에 기재된 본 발명의 실시예는 본 발명의 기술적 사상을 예시적으로 설명하기 위한 것에 불과한 것으로, 본 발명의 권리범위가 여기에 한정되는 것으로 이해되어서는 안될 것이다. 아래의 실시예로부터 다양한 변형, 변경 및 수정이 가능함은 이 분야의 통상의 지식을 가진 자에게 있어서 명백한 것이다.Hereinafter, an embodiment of the present invention will be described in more detail with reference to the accompanying drawings. The embodiments of the present invention described below are merely for illustrating the technical idea of the present invention by way of example, it should not be understood that the scope of the present invention is limited thereto. Various modifications, changes and variations are possible in the following examples which will be apparent to those of ordinary skill in the art.

먼저, 도 3a를 참조하면, 반도체 기판(50) 위에 실리콘 산화막(SiO2, 52)을 형성하여 산화시키고, 포토레지스트를 도포한다. 이때 사진공정에 의해 N웰 영역(54)을 형성하기 위한 포토레지스트를 제거하고 이 영역에 이온을 주입한다. 그리고, 이와 같은 순서에 의해 다시 포토레지스트 도포, 이온주입 및 확산을 통해 P웰 영역(56)을 형성한다. First, referring to FIG. 3A, silicon oxide films SiO 2 and 52 are formed and oxidized on the semiconductor substrate 50, and a photoresist is applied. At this time, the photoresist for forming the N well region 54 is removed by a photolithography process and ions are implanted into the region. In this order, the P well region 56 is formed again by photoresist coating, ion implantation, and diffusion.                     

도 3b를 참조하면, 상기 실리콘 산화막(52) 위에 질화막(Si3N4, 58)을 증착하고, 트렌치 형성을 위한 포토공정이 이루어진 후 먼저 상기 질화막(58)을 건식식각한다. 즉, 도 3b에는 트렌치 형성을 위한 건식식각을 수행하여 형성된 트렌치(62) 구조가 도시되어 있다.Referring to FIG. 3B, nitride layers Si 3 N 4 and 58 are deposited on the silicon oxide layer 52, and after the photo process for forming trenches is performed, first, the nitride layer 58 is dry-etched. That is, FIG. 3B illustrates a trench 62 structure formed by performing dry etching for trench formation.

도 3c를 참조하면, 상기 트렌치(62) 형성 후 포토레지스트막(60)을 제거하고 게이트 산화막을 형성한다. 그리고, 게이트 형성을 위해 폴리실리콘을 반도체 기판(50) 전면에 걸쳐서 증착하고, 화학기계적 연마에 의한 에치백을 실시하여 게이트 전극(64)을 형성한다.Referring to FIG. 3C, after the trench 62 is formed, the photoresist layer 60 is removed to form a gate oxide layer. Then, polysilicon is deposited over the entire surface of the semiconductor substrate 50 to form the gate, and the gate electrode 64 is formed by performing etch back by chemical mechanical polishing.

그리고, 도 3d를 참조하면, 그 위에 포토레지스트(66)를 도포하여 필드산화막 형성을 위한 사진공정을 실시하고, 그 후 상기 포토레지스트(66)에 의해 노출된 질화막(58)을 식각한다.Referring to FIG. 3D, a photoresist 66 is applied thereon to perform a photolithography process for forming a field oxide film, and then the nitride film 58 exposed by the photoresist 66 is etched.

도 3e를 참조하면, 상기 질화막(58)이 노출된 부분에 필드산화막(68)을 형성하고, 상기 질화막(58)을 제거한다. 그후 포토공정을 통해 N 마이너(Minor) 영역 형성을 위한 이온주입이 이루어지고, 또한 P 마이너 영역 형성을 위한 이온주입이 이루어진다.Referring to FIG. 3E, the field oxide film 68 is formed on the exposed portion of the nitride film 58, and the nitride film 58 is removed. Thereafter, ion implantation for forming a N minor region is performed through a photo process, and ion implantation for forming a P minor region is performed.

그리고, 도 3f 및 도 3g에 의하면, 확산에 의해 N- 및 P- 불순물 영역(72, 74)을 형성하고, N 플러스(Plus) 영역 형성을 위한 사진공정이 실시된 후 이온주입이 이루어진다. 또한, P 플러스 영역 형성을 위한 사진공정이 실시된 후 이온주입이 이루어진다.3F and 3G, N- and P- impurity regions 72 and 74 are formed by diffusion, and ion implantation is performed after a photolithography process for forming an N plus region is performed. In addition, ion implantation is performed after the photo process for forming the P plus region is performed.

그 결과 도 3h에서 볼 수 있는 바와 같이, 불순물 영역(78, 82)이 형성된 고 전압 모스 형성을 위한 공정이 완료되고, 그 후 전극을 형성하게 된다.As a result, as shown in FIG. 3H, the process for forming the high voltage MOS in which the impurity regions 78 and 82 are formed is completed, and then the electrode is formed.

이상과 같은 공정을 통해 알 수 있는 바와 같이, 트렌치 구조의 게이트 전극(64)에 의해 채널길이가 효과적으로 확대되는 것을 확인할 수 있다.As can be seen through the above process, it can be seen that the channel length is effectively enlarged by the gate electrode 64 of the trench structure.

따라서, 본 발명에 의하면, 트렌치 구조를 적용하여 게이트 전극을 형성함으로써 소자 사이즈 대비 채널 길이를 효과적으로 확대할 수 있으며, 고밀도 소자설계에 의한 집적도를 높이는 효과가 있다.Therefore, according to the present invention, by forming a gate electrode by applying a trench structure, the channel length can be effectively enlarged compared to the device size, and the integration density due to the high density device design can be increased.

Claims (3)

반도체 기판 위에 절연막을 형성하고, 사진공정 및 이온주입을 반복하여 서로 다른 웰 영역을 형성하는 단계와;Forming an insulating film on the semiconductor substrate, and repeating the photolithography process and ion implantation to form different well regions; 상기 절연막 위에 질화막을 증착하고, 포토공정을 수행하여 상기 질화막을 건식식각한 후 트렌치를 형성하는 단계와;Depositing a nitride film on the insulating film, performing a photo process to dry-etch the nitride film, and then forming a trench; 상기 트렌치 형성 후 게이트 산화를 실시하고, 폴리실리콘을 반도체 기판 전면에 걸쳐서 증착하여 게이트 전극을 형성하는 단계와;Performing gate oxidation after the trench formation, and depositing polysilicon over the entire surface of the semiconductor substrate to form a gate electrode; 포토레지스트를 도포하여 필드산화막 형성을 위한 사진공정을 실시하고, 상기 포토레지스트에 의해 노출된 질화막을 식각하는 단계와;Applying a photoresist to perform a photo process for forming a field oxide film, and etching the nitride film exposed by the photoresist; 상기 질화막에 의해 노출된 부분에 필드산화막을 형성한 후 상기 질화막을 제거하고, 이온주입에 의해 소스 및 드레인 영역 형성을 위한 제 1 불순물을 주입하는 단계; 그리고,Forming a field oxide film on the portion exposed by the nitride film, removing the nitride film, and implanting first impurities for forming source and drain regions by ion implantation; And, 상기 제 1 불순물 영역 위에 제 2 불순물 영역 형성을 위한 사진공정이 실시된 후 이온주입이 이루어지는 단계;Performing ion implantation after the photolithography process is performed on the first impurity region to form a second impurity region; 를 포함하는 것을 특징으로 하는 고전압 모스 소자의 제조 방법.Method of manufacturing a high voltage MOS device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 트렌치는,The trench, 상기 서로 다른 웰 영역에 각각 형성되는 것을 특징으로 하는 고전압 모스 소자의 제조 방법.The method of manufacturing a high voltage MOS device, characterized in that each formed in the different well region. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 트렌치는,The trench, 상기 소스와 드레인 사이의 채널길이가 확대되도록 하는 것을 특징으로 하는 고전압 모스 소자의 제조 방법.And a channel length between the source and the drain is enlarged.
KR1020020010910A 2002-02-28 2002-02-28 Method of forming a high voltage MOS device KR100817712B1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970004063A (en) * 1995-06-30 1997-01-29 김주용 MOS transistor manufacturing method
KR970063782A (en) * 1996-02-24 1997-09-12 김광호 High-voltage transistor
KR20010090148A (en) * 2000-03-23 2001-10-18 박종섭 Fabricating method of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970004063A (en) * 1995-06-30 1997-01-29 김주용 MOS transistor manufacturing method
KR970063782A (en) * 1996-02-24 1997-09-12 김광호 High-voltage transistor
KR20010090148A (en) * 2000-03-23 2001-10-18 박종섭 Fabricating method of semiconductor device

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