JP2705583B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MOS type semiconductor device, and more particularly to a method of manufacturing a highly integrated MOS type semiconductor device in which the current driving capability of a transistor is enhanced. 2. Description of the Related Art Conventionally, an M type semiconductor device has been developed.
Among the OS transistors, the surface channel type PM
An OS transistor has a source,
A method of forming the drain diffusion layer and implanting impurities into polycrystalline silicon serving as a gate electrode by the same ion implantation is often adopted. A method for manufacturing such a conventional MOS type semiconductor device will be described with reference to the drawings. First, as shown in FIG. 3A, a selective thermal oxidation method (LOCOS) is formed on an N-type semiconductor substrate 11 composed of an N-type region formed on an N-type silicon substrate or a P-type silicon substrate. Method), a field oxide film 12 is formed, and then a gate oxide film 13 is formed as a gate insulating film by thermal oxidation. Next, polycrystalline silicon is grown on the entire surface by CVD to a thickness of about 2000 to 3000 °, and after photoresist 14 is patterned thereon, anisotropic reactive dry etching is performed using the photoresist 14 as a mask. Is performed, the polycrystalline silicon is patterned, and a gate electrode (poly gate) 15 is formed. Next, as shown in FIG. 3B, after the photoresist 14 is peeled off, a silicon oxide film is formed by a CVD method.
After the growth of about 00 to 3000 °, the silicon oxide film is etched back by anisotropic dry etching to leave the silicon oxide film 16 only on the side wall of the gate electrode 15. Then, as shown in FIG. 3C, a P-type impurity such as boron or boron fluoride (BF ₂ ) is ion-implanted at a dose of, for example, 10 ¹⁵ to 10 ¹⁶ cm ^-2 . It is introduced into the semiconductor substrate 11 and the gate electrode 15. After the ion implantation, a heat treatment of about 900 ° C. is performed in a nitrogen atmosphere, so that a source, a high-concentration P-type impurity diffusion layer,
Each of the drain diffusion layers 18 and the gate electrode 15 made of polycrystalline silicon doped with a P-type impurity are formed. After that, a metal such as titanium, molybdenum, or platinum may be reacted with silicon to form an alloy layer with silicon in order to reduce the resistance of the source, drain, and gate diffusion layers. [0006] By the way, this kind of M
In the OS transistor, as the gate electrode length becomes smaller, the controllability of the channel gate deteriorates due to the influence of the depletion layer extending from the high-concentration impurity layer forming the drain, the threshold voltage decreases, and the transistor is turned off. When the gate voltage is 0 V, the leak current tends to increase.
In order to suppress the extension of the depletion layer from the drain high concentration diffusion layer in the channel direction, it is necessary to form the high concentration diffusion layer shallow from the surface of the semiconductor substrate. However, if the implantation energy at the time of ion implantation is reduced and the time or temperature of the heat treatment after the ion implantation is reduced for the purpose of forming the high-concentration impurity diffusion layer shallowly, the polycrystalline silicon as the gate electrode is reduced. The distribution of impurities therein is biased, and in particular, the concentration of impurities in the vicinity of the gate insulating film tends to decrease. This causes a phenomenon that a depletion layer extends in polycrystalline silicon as a gate electrode during operation of a transistor (a state in which a voltage is applied to the gate), and as a result, an effective reduction in gate capacitance occurs. This is because the current driving capability of the transistor is reduced. SUMMARY OF THE INVENTION It is an object of the present invention to form a shallow source / drain high-concentration diffusion layer without lowering the impurity concentration in the vicinity of a gate insulating film in a gate electrode.
Accordingly, a method of manufacturing a semiconductor device including a MOS transistor which prevents a decrease in threshold voltage and an increase in leak current even when the gate electrode length is reduced, and does not reduce the current driving capability of the transistor. Is to provide. According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a gate made of polycrystalline silicon on a semiconductor substrate;
Forming a gate electrode and performing ion implantation under predetermined conditions.
The peak of the impurity concentration in the formed gate electrode is
Near the gate insulating film, and the same
So that the source / drain diffusion layers that are sometimes formed become shallower
Forming a thick insulating film on the semiconductor substrate,
Performing the ion implantation through the insulating film.
In. Note that the insulating film is not provided on the gate electrode.
Good. Further , the insulating film is formed on the gate electrode.
The first region is formed by a liquid phase growth method in a region excluding the provided mask layer.
Forming an insulating film, and removing the mask layer.
And forming a second layer on the gate electrode and the first insulating film.
Forming an insulating film; and forming the first film on the gate electrode.
Etching back until the insulating film is removed, and
May be formed. Here, the insulating film may be formed of an oxide film.
Is preferred. An impurity is ion-implanted into a gate electrode and a source / drain formation region in a state where an oxide film does not exist on a gate electrode or is thinner than an oxide film on a semiconductor substrate in a source / drain formation region. By doing so, it becomes possible to introduce a sufficiently deep impurity into the gate electrode and to form a shallow diffusion layer in the source / drain formation region. Next, an embodiment of the present invention will be described with reference to the drawings. 1 and 2 are sectional views showing an embodiment in which the present invention is applied to a PMOS transistor in the order of manufacturing steps. First, as shown in FIG. 1A, a field oxide film 2 is formed on an N-type semiconductor substrate 1 by a selective thermal oxidation method to define an element formation region. Thereby, gate oxide film 3 having a thickness of about 100 ° is formed.
Then, as shown in FIG. 1 (b), polycrystalline silicon is grown on the gate oxide film 3 to a thickness of about 2000 to 3000.degree. Polycrystalline silicon is anisotropically dry-etched using the resist 4 as a mask to form a gate electrode 5. Next, as shown in FIG. 1C, a silicon oxide film 6 is grown on the surface of the semiconductor substrate liquid 1 by a liquid phase growth method while the photoresist 4 is left. The growth of a silicon oxide film in the liquid phase is performed, for example, by adding a boric acid aqueous solution to a saturated aqueous solution obtained by melting silicon dioxide in hydrosilicic acid, thereby creating a supersaturated state, and depositing the silicon oxide film to form a semiconductor substrate. There is a method of depositing on top.
If an oxide film is grown in such a liquid phase, the silicon oxide film 6 will not grow on the photoresist 4, and therefore only on the side surfaces of the gate electrode 5 and on the gate oxide film 3 and the field oxide film 2. Grow selectively. The thickness of the silicon oxide film 6 deposited at this time is about 程度 or １ ／ of the thickness of the gate electrode 5. Next, as shown in FIG.
After the upper photoresist 4 is removed, a silicon oxide film 7 is grown on the entire surface of the semiconductor substrate 1 by several thousand ＣＶＤ by a CVD method. As a result, the silicon oxide film existing on the semiconductor substrate 1 is formed on the gate electrode 5 as a silicon oxide film corresponding to the thickness of the silicon oxide film 7 grown by the CVD method. Above, the silicon oxide film is formed as a silicon oxide film having the thickness of the sum of the silicon oxide film 6 formed by the liquid phase growth method and the silicon oxide film 7 formed by the CVD method. Next, as shown in FIG. 2B, the silicon oxide film on the semiconductor substrate 1 is etched back by anisotropic dry etching. At this time, the etching processing conditions are set so as to etch only the silicon oxide film existing on the gate electrode 5, that is, the thickness of the silicon oxide film 7 grown by the CVD method. Almost all of the silicon oxide film 7 on the gate electrode 5 is removed, and a silicon oxide film corresponding to the silicon oxide film 6 formed by the liquid phase growth method is not removed on the semiconductor substrate 1 other than the gate electrode 5. Will be left behind. Then, as shown in FIG. 2C, the semiconductor substrate 1 and the gate electrode 5 are ion-implanted.
10 P-type impurities such as boron and boron fluoride (BF ₂ )
^{Implant at} a dose of ¹⁵ to 10 ¹⁶ cm ^-2 . As a result, the P-type impurity is introduced at a high concentration into the polycrystalline silicon constituting the gate electrode 5, and at the same time, the P-type impurity is introduced at a high concentration into the semiconductor substrate in each of the source and drain regions. Then, by performing activation by a predetermined heat treatment,
The source / drain diffusion layer 8 is formed shallowly in the source / drain region. Thereafter, although not shown, an interlayer insulating film is formed by a conventional method, a contact hole is opened, and a source / drain electrode is formed, thereby completing a PMOS transistor. Thus, in the manufacturing process of this embodiment,
In the step of FIG. 2C, the silicon oxide film 7 on the gate electrode 5 is almost removed, and the silicon oxide film 6 on the semiconductor substrate 1 in the source / drain region is left with a high concentration of P-type impurities. By performing ion implantation, the gate electrode 5
Impurities are directly ion-implanted into the
Ion implantation is performed on the semiconductor substrate 1 in the drain region via the silicon oxide film 6. Therefore, even if the ion implantation energy is set so that the concentration peak of the ion-implanted impurity comes to a region near the gate oxide film 3 of the gate electrode 5, the silicon oxide is not formed in the semiconductor substrate 1 in the source and drain regions. Since the ion implantation is performed through the film, the concentration peak of the ion-implanted impurity is not formed at a deep position in the semiconductor substrate 1. Further, even if heat treatment is performed at a somewhat high temperature in a nitrogen atmosphere for activating the implanted P-type impurity, the concentration peak of the ion-implanted impurity is formed at a position shallow from the surface of the semiconductor substrate 1. Therefore, the shallow formation of the high concentration diffusion layer (source, drain) 8 becomes possible. As a result, high-concentration impurities exist in the gate electrode 5 up to a region near the gate oxide film 3, while the source / drain diffusion layer 8 is formed to be high-concentration and shallow. Even when the size is reduced, it is possible to suppress the extension of the depletion layer in the channel direction from the drain diffusion layer to prevent the threshold voltage from decreasing and the leakage current from increasing, and at the same time, to deplete the gate electrode 5 during the operation of the transistor. It is possible to prevent the layer from being elongated and to increase the current driving capability of the transistor. Here, in the above-described embodiment, the silicon oxide film formed by the liquid phase growth method is used, so that the silicon oxide film on the gate electrode and the source / drain region have a difference in film thickness. However, by forming a silicon oxide film by a lift-off method using the photoresist used when forming the gate electrode, the oxide film on the gate electrode and the source / drain region have a thickness difference. It may be. Alternatively, a technique for selectively forming a silicon oxide film can be used. Further, in the above embodiment, the silicon oxide film on the gate electrode is entirely removed. However, the difference in film thickness between the silicon oxide film on the source / drain regions is sufficient. A thin silicon oxide film may be left. In the above-described embodiment, an example is shown in which the present invention is applied to a PMOS transistor in which impurities are simultaneously introduced into the gate electrode and the source / drain regions. The invention is equally applicable. As described above, according to the present invention, the oxide film on the gate electrode is removed or the oxide film on the source / drain region is made thicker than the gate electrode and the source / drain region. Even if a sufficient concentration of impurities is implanted into the gate electrode by implanting impurities into the region, the impurities are implanted through the thick oxide film in the source / drain regions. The layer is formed as a diffusion layer having a concentration peak at a position shallow from the semiconductor substrate surface. Therefore,
The impurity concentration in the gate electrode increases near the gate insulating film, while the source / drain diffusion layers in the semiconductor substrate can be formed shallower. As a result, it is possible to prevent the depletion layer from extending into the gate electrode during the operation of the transistor, thereby increasing the transistor current driving capability. Short channel effects such as a decrease in threshold voltage, which are caused by miniaturization, can be prevented. As a result, good subthreshold characteristics can be obtained, and leakage current during standby can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a first sectional view showing one embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of manufacturing steps. FIG. 2 is a second sectional view showing the embodiment of the present invention in the order of the manufacturing steps. FIG. 3 is a cross-sectional view showing a conventional manufacturing method in the order of steps. [Description of Reference Numerals] 1 semiconductor substrate 3 gate oxide film 4 photoresist 5 gate electrode (polycrystalline silicon) 6 liquid phase grown silicon oxide film 7 CVD silicon oxide film 8 source / drain diffusion layer

Claims (1)

(57) [Claims] [Claim 1] Polysilicon is formed on a semiconductor substrate.
For forming gate electrode and ion implantation under predetermined conditions
Impurity concentration peak in the gate electrode formed by
In the vicinity of the gate insulating film, and
Source / drain diffusion layers formed simultaneously
Forming an insulating film having such a thickness on the semiconductor substrate
And a step of performing the ion implantation through the insulating film.
A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein the insulating film is not provided on the gate electrode.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: [Claim 3] The insulating film is provided on the gate electrode.
In the area excluding the mask layer, the first
Kneading to form an edge film and a step of removing the mask layer
And a second insulator on the gate electrode and the first insulating film.
Forming an edge film; and forming the first film on the gate electrode.
Etching back until the insulating film is removed
3. The method for manufacturing a semiconductor device according to claim 2, wherein the semiconductor device is formed by : 4. The method according to claim 1, wherein said insulating film is an oxide film.
4. The method for manufacturing a semiconductor device according to claim 1, 2, 3, or 4 .