JPH0738095A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PURPOSE:To provide a semiconductor device having groove gate type MOSFETs whose switching delay time is short. CONSTITUTION:This is a semiconductor device having at least one field effect transistor in which the source and drain regions are formed by a high concentration diffused layer 13' and a low concentration diffused layer 13, a groove part is provided in the channel part between the source and drain regions, the gate electrode 10 is provided via the gate insulator film 9 in the groove part, and the gate electrode 10 is placed on the surface of the substrate outside the groove region via a nitride film 5 which is thicker than the gate insulator film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal-oxide-semiconductor type field effect transistor (Metal Oxide Semiconducto).
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an r field effect transistor;

[0002]

2. Description of the Related Art A dynamic random access memory, which is a typical example of an integrated circuit using a MOSFET, is currently mass-produced at 4 megabits using a 0.8-micron technology. In addition, mass production of 16-megabit, which uses the next-generation 0.5 micron technology, has started even though it is small. There is no doubt that semiconductor devices will be reduced in size and the degree of integration will be improved in combination with advances in fine processing technology.

By the way, the miniaturization of semiconductor elements such as MOSFET has been achieved not only by simply reducing the size but also by a short channel effect (conducting the MOSFET in conduction) which becomes remarkable as the size of the gate electrode is reduced. (The phenomenon that the gate voltage required for abruptly drops from a certain gate size)
Also, undesirable phenomena such as punch-through (a phenomenon in which the current cannot be controlled by the gate) have been suppressed.

The guideline in this case is the proportional reduction rule. According to this, as the size is reduced, the impurity concentration of the substrate is increased, the gate oxide film is thinned, and the diffusion layer of the source drain is formed. I've been shallow. In order to miniaturize semiconductor devices, especially MOSFETs, it is inevitable to follow this guideline, but the gate electrode size is 0.2
When it becomes less than μm, only by the guideline of miniaturization so far,
It is difficult to suppress the short channel effect and punch through.

This is because the source / drain diffusion layer serving as a current inlet / outlet exists inside the substrate with a certain depth, and the depth has a limit determined by process conditions such as ion implantation. As the size of the gate electrode becomes smaller, the depletion layer extending from the drain region reaches the source region, and as a result, the potential barrier between the source and channel lowers, causing a phenomenon in which a current that cannot be controlled by the gate flows. . In order to suppress the extension of the depletion layer, various measures have been taken such as providing a high-concentration region inside the substrate, or using the periphery of the groove provided in the substrate as a channel, that is, a so-called trench gate type MOSFET.

FIG. 2 shows a sectional view of a conventional trench gate type MOSFET. A high-concentration region (3) having the same conductivity type as the substrate and a high conductivity is formed as a channel stopper layer around the region of the element isolation oxide film (2) of the semiconductor substrate (1). Region, the groove (6) formed between the diffusion layers (13, 13 ′) forming the drain region, the gate electrode (1) via the gate oxide film (9).
0) is provided. With this structure, the extension of the depletion layer can be suppressed. Incidentally, as the prior art relating to this, Japanese Patent Laid-Open Nos. 50-8483 and 56-8397.
4 etc. are mentioned.

[0007]

The above-mentioned conventional technique has a problem that the gate oxide film around the groove is thin, the overlapping capacitance between the gate electrode and the drain region is large, and therefore, the switching delay time of the MOSFET is long. .

A first object of the present invention is a groove gate type MOS.
An object of the present invention is to provide a semiconductor device having an FET and having a short switching delay time. A second object of the present invention is to provide a semiconductor device manufacturing method suitable for manufacturing such a semiconductor device.

[0009]

In order to achieve the first object, the semiconductor device of the present invention, as shown in FIG. 1, has source and drain regions composed of a high concentration layer and a low concentration layer, A recess is provided in the channel portion between the source and drain regions, and a gate electrode is provided in the recess via a gate insulating film,
Further, a field effect transistor is configured by laminating a gate electrode on a desired portion of the substrate surface outside the recess via a first insulating film thicker than the gate insulating film.

The gate electrode of this field effect transistor may be made of a refractory metal such as W or Mo.
This is preferable because the gate electrode can have low resistance. In addition, in the vicinity of the surface of the source and drain regions, a metal film such as W or W,
It is preferable that a silicide film of a metal such as Mo, Ni, Ti, or Co is arranged. Further, it is preferable to form the high-concentration region only under the gate electrode inside the substrate. Furthermore, a p-type MOS of a semiconductor device having a complementary MOS
The field effect transistor described above may be used for each of the FET and the n-type MOSFET.

In order to achieve the above second object,
A method for manufacturing a semiconductor device of the present invention provides a semiconductor substrate having a first insulating film having a desired thickness on a surface thereof and having a low-concentration layer serving as a source and drain regions at a desired depth,
A hole is provided in a desired portion of the insulating film, a recess is formed in the semiconductor substrate from the hole, a gate insulating film is formed in the recess, and a gate electrode having a desired shape is formed on the gate insulating film and the first insulating film. Is formed, the first insulating film is removed using the gate electrode as a mask, and at least on the sidewalls of the first insulating film and the gate electrode,
The sidewall insulating film is formed in a self-aligning manner, and further, the high-concentration layer forming the source and drain regions is formed using at least the sidewall insulating film as a mask.

Further, in order to achieve the second object, the method of manufacturing a semiconductor device according to the present invention prepares a semiconductor substrate having a first insulating film having a desired thickness on a surface thereof, and the desired insulating film is obtained. A hole is formed in the portion, a recess is formed in the semiconductor substrate from the hole, a gate insulating film is formed in the recess, and a gate electrode having a desired shape is formed on the gate insulating film and the first insulating film, The first insulating film is removed using the gate electrode as a mask, and low-concentration layers forming source and drain regions are provided in the portion where the first insulating film is removed, and at least the first insulating film and the gate electrode A side wall insulating film is formed on the side wall of the substrate in a self-aligning manner, and at least the side wall insulating film is used as a mask to form a high-concentration layer forming a source and drain regions.

Further, in order to achieve the second object, the method for manufacturing a semiconductor device of the present invention has a first insulating film having a desired thickness on the surface, and a first conductivity type region and the first conductivity type region. A semiconductor substrate having second conductivity type regions different from each other and having a low concentration layer which is a conductivity type different from each conductivity type at a desired depth of each region and which serves as a source / drain region. A hole is formed in a desired portion of the insulating film on each region, a recess is formed in the semiconductor substrate from the hole, a gate insulating film is formed in each recess, and the gate insulating film and the first insulating film are formed. A gate electrode having a desired shape is formed on each of the films, the first insulating film is removed by using the gate electrode as a mask, and at least the side walls of the first insulating film and the gate electrode are self-aligned. A side wall insulating film is formed on the Type or second conductivity type region is covered with a mask, and in the other region, at least the sidewall insulating film is used as a mask to form a high-concentration layer forming source and drain regions. The region is covered with a mask, and at least the side wall insulating film is used as a mask to form the high concentration layer forming the source and drain regions in the one region.

[0014]

The groove gate type structure effectively suppresses the depletion layer from the drain region from entering the source region, so that the short channel effect can be suppressed. Further, by stacking the gate electrode on the substrate surface outside the recess via the first insulating film that is thicker than the gate insulating film, the overlapping capacitance between the gate electrode and the drain region is reduced, and the switching delay time of the MOSFET is reduced. Get smaller. The switching delay time τ is approximately represented by the following equation.

Τ = (CV) / I where C is the gate capacitance, V is the voltage, and I is the current. The smaller the gate capacitance C, the smaller the delay time τ.

Further, when a high melting point metal such as tungsten is used for the gate electrode, the gate resistance becomes small, and as a result, the low resistance of the gate electrode, which is typified by the salicide process, used in the conventional MOSFET. It is not necessary to carry out the crystallization process.

[0017]

<Embodiment 1> Hereinafter, a first embodiment of the present invention will be described in detail with reference to FIGS. The first embodiment is an example of forming a diffusion layer in advance. Also, n-type M
An explanation will be given by taking the OSFET as an example.
It goes without saying that this can be achieved by changing the conductivity type of the substrate and the type of impurities.

First, as shown in FIG. 3A, a pattern (not shown) of a nitride film is formed on the surface of a p-type semiconductor substrate (1) and boron is implanted using this as a mask.
After thermal diffusion, the element isolation oxide film (2) is grown by the selective oxidation method. Although the impurity concentration of the semiconductor substrate depends on the size of the MOSFET to be realized, it is set to 6 × 10 ¹⁶ / cm ³ used in the 0.5 μm technology in this embodiment. This is because, in the semiconductor device of this embodiment, the short channel effect is suppressed by the groove gate structure, and it is not necessary to increase the impurity concentration of the substrate. The film thickness of the element isolation oxide film (2) was 400 nm. The implanted boron forms a high-concentration region (3) covering the periphery of the element isolation oxide film (2). This region improves element isolation characteristics.

Next, as shown in FIG. 3 (b), an arsenic is grown to grow an oxide film (4) of about 20 nm on the surface of the semiconductor substrate and to form a diffusion layer (13) in the substrate surface region. At a high concentration (1 × 10 ²⁰ / cm ³ ). The depth is 0.05 μm. After removing the contaminants due to the ion implantation, as shown in FIG.
The nitride film (5) is deposited by vapor deposition. The film thickness is 120n
m. Next, as shown in FIG. 3D, by using the lithography technique and the dry etching technique, only the nitride film (5) substantially in the center of the active region surrounded by the element isolation oxide film (2) is removed. . Although not visible in this cross-sectional view, a part of the groove formed in the nitride film extends in the direction perpendicular to the plane of the drawing and extends over the region of the element isolation oxide film (2) in that direction.
The processing of the nitride film (5) is stopped at the underlying oxide film (4).

Further, as shown in FIG. 3E, a sidewall nitride film (5 ') is formed only around the formed groove.
This sidewall nitride film can be realized by etching a newly deposited nitride film on the entire surface of the substrate by anisotropic dry etching. The dimension of the nitride film on the sidewall depends on the film thickness of the deposited film, but in the present embodiment, the thickness was set to 0.1 μm. Since the size of the groove is 0.3 μm which can be easily achieved by the current i-line lithography,
Due to the formation of the sidewall nitride film (5 '), the finished groove dimension becomes 0.1 μm. Thus, by using a self-aligned process, dimensions not achievable with conventional lithographic techniques can be achieved.

Next, as shown in FIG. 4 (a), using the nitride film (5) and the side wall nitride film (5 ') as a mask, a groove (6) is dug in the substrate by a dry etching method to be preliminarily formed. The previously set diffusion layer (13) is separated into a set of diffusion layer regions.
By this step, the diffusion layer is separated into the source and the drain of the MOSFET.

The dry etching creates a damaged region on the surface of the substrate, which causes deterioration of the characteristics of the semiconductor device. Therefore, in order to remove this region and use it as a protective film in the subsequent ion implantation step, FIG.
An oxide film (7) is grown as shown in FIG. Since the damaged region is several nm from the surface, the thickness of the grown oxide film was 10 nm. And through this oxide film,
Ions are implanted to adjust the threshold voltage of the MOSFET to form a high concentration region (8). The ion species is boron, and the implantation amount is 1 × 10 ¹² to 1 × 10.
¹³ / cm ² , and the implantation energy is 20K
eV.

After the ion implantation is completed, the oxide film (7) which has become the protective film is removed by a solution containing hydrofluoric acid, and further, as shown in FIG. 4C, the gate oxide film (9) of the MOSFET is formed. ) Becomes an oxide film. The thickness of the oxide film was 5 nm, and the oxidation temperature was 850 ° C.

Next, as shown in FIG. 4D, tungsten (10) to be the gate electrode was deposited by the sputtering method, and further an oxide film (11) made of silicon dioxide was deposited. Since tungsten is easily oxidized in a high temperature oxidizing atmosphere, a low temperature oxide film deposition method utilizing the reaction between ozone and TEOS (tetraethoxy orthosilicate) was used for depositing the oxide film (11). Next, FIG.
As shown in (e), the photoresist (12) is formed into a gate electrode shape by using a lithography technique, and the underlying oxide film (11) is processed by a dry etching method using this as a mask.

Further, as shown in FIG. 5A, the underlying tungsten (10) of the oxide film (11) is processed.
At this time, the nitride film (5) which is the base of tungsten is abraded by several tens of nm, but the element isolation oxide film (2) is not exposed. Next, as shown in FIG. 5B, the nitride film (5) which is the base of the tungsten processing is etched by using the dry etching method, but it is under the gate electrode (10) of tungsten. Part of the nitride film (5) remains. The reason why the nitride film is used as the underlayer of tungsten is to prevent the element isolation oxide film from being scraped by utilizing the selection ratio with the element isolation oxide film when removing the nitride film.

Further, as shown in FIG. 5C, a sidewall oxide film (14) is formed around the gate electrode. This sidewall oxide film (14) is formed by depositing an oxide film and a full-scale etching method using anisotropic dry etching, similarly to the formation of the sidewall nitride film of the trench shown in FIG. 3 (e). It was realized. Further, using the gate electrode and the sidewall oxide film as a mask, a diffusion layer (13 ') is formed again. The implanted ions are arsenic, and the implantation amount is 3 × 10 ¹⁵ / cm ² .
Further, the substrate surface is exposed by the entire surface etching at the time of forming the sidewall oxide film.

Next, after removing the contamination due to the ion implantation, as shown in FIG. 5D, tungsten (15) is selectively grown on the surface of the diffusion layer. WF ₆ and S
By reacting with iH ₄ , tungsten was selectively grown only on the substrate surface. Finally, Figure 5
As shown in (e), an interlayer insulating film (16) is deposited, a contact hole is opened, the contact hole is backfilled with tungsten (18) using a plug forming technique, and finally a wiring (19) is formed. ) Is formed of a metal whose main component is aluminum. Further, when increasing the number of wiring layers, this process is repeated.

Even if molybdenum was used as the gate electrode instead of tungsten, the same effect could be obtained. Tungsten formed on the surface of the diffusion layer (15)
Instead of, a similar effect could be obtained by using a silicide of a metal such as tungsten, molybdenum, nickel, titanium, or cobalt.

In this embodiment, a method of forming a diffusion layer in advance and separating it by digging a groove in the substrate is adopted. In this method, the side wall of the groove is always in contact with the diffusion layer, so that there is no gap between the gate electrode and the diffusion layer, which is a so-called offset state. If this gap is created, a region having high resistance is connected in series to the diffusion layer, which causes deterioration of the characteristics of the MOSFET.

Further, in this embodiment, since the nitride film (5) necessary for forming the concave portion serves as a base for processing the tungsten which is the gate electrode, such metal is used as the gate electrode without scraping the substrate. Can be used. Further, since the high concentration region (8) formed inside the substrate is formed only directly under the gate electrode, it has an effect of suppressing an increase in diffusion capacitance. The same applies to the following examples.

<Embodiment 2> In the method of forming the diffusion layer in advance as in Embodiment 1, the depth of the groove must be adjusted according to the depth of the diffusion layer, and as described later, n Mold,
When both p-type MOSFETs are formed on the same substrate, different types of impurity diffusion layers must be formed, so it is very difficult to separate the diffusion layers only by adjusting the groove depth.

Therefore, in the second embodiment, the conventional MOS
Similar to the FET, the ion implantation for forming the diffusion layer is performed after the gate electrode is formed. For this purpose, an oblique ion implantation method is used in which ions are obliquely incident on the substrate.

Similar to the first embodiment, the element isolation oxide film (2) and the high concentration region (3) are formed on the semiconductor substrate (1) as shown in FIG.
It is formed as shown in FIG. Then, as shown in FIG. 6B, an oxide film (4) is grown on the surface of the substrate. The film thickness is the same as in Example 1.

In this embodiment, the ion implantation for forming the diffusion layer is not carried out, and the rest is the same as in the first embodiment, as shown in FIG.
As shown in FIGS. 6 (e) to 6 (e), after forming the nitride film (5) and the sidewall nitride film (5 ′), as shown in FIG. 7 (a), a groove (6) is formed on the substrate. ) Dig. After that, the steps of forming the gate electrode (FIGS. 7B to 7E) and FIG.
(A)) is exactly the same as the first embodiment.

Next, proceeding to the step of forming a diffusion layer, as shown in FIG. 8B, the tungsten (10) which is the gate electrode has an umbrella-like shape that spreads upward. Therefore, when ions are implanted vertically, the gate electrode and the diffusion layer are offset as described above, and the normal M
OSFET operation cannot be expected. Therefore, in this embodiment, as shown in the figure, a method of implanting ions obliquely is adopted. Specifically, 30 to 40 on each side
Implantation is performed with a gradient of degrees so that the impurities reach the gate oxide film region. Furthermore, in order to prevent offset by adding lateral diffusion by heat treatment,
Phosphorus was used as an impurity. Driving amount is 1 × 10 ¹⁵ / c
m ² and the implantation energy were 40 KeV.

The subsequent steps are shown in FIGS.
As shown in (e), since it is exactly the same as that of the first embodiment, it is omitted.

<Third Embodiment> In a third embodiment, the MOSFET of the present invention is a complementary MOS in which n-type and p-type coexist.
An example applied to the FET will be described. Complementary MOSFE
At T, it is necessary to form regions of different conductivity types (hereinafter referred to as wells) on the same substrate. In addition, MOSF
Although the method described in the first embodiment is adopted for creating the ET, it goes without saying that the method of the second embodiment can be used.

In order to form well regions having different conductivity types, first, as shown in FIG. 9A, an oxide film (4 ') is grown on the surface of a p-type semiconductor substrate (1), and further, ,
A nitride film (5 ″) is deposited. The oxide film (4 ′) has a film thickness of 1
0 nm, and the film thickness of the nitride film (5 ″) is 150 nm.

As shown in FIG. 9B, this nitride film (5 ″) is processed into a desired shape by a dry etching method using a mask of photoresist (12). It is necessary to leave the membrane (4 ').

Next, except for the photoresist (12), as shown in FIG.
As shown in (c), using the nitride film (5 ″) as a mask
To form an n-type well region (21).
Ion implant. Driving energy is 125K
eV, implant amount is 1 × 10 ¹³/ Cm³Is. this
At this time, the remaining nitride film (5 ") is the ion-implanted mass.
In the area where the nitride film is present, phosphorus
Is not driven.

Further, when contaminants and the like due to ion implantation are removed and the substrate is placed in an oxidizing atmosphere, as shown in FIG. 9D, a region without the nitride film (5 ″), that is,
Selective oxidation occurs in which the oxide film (4 ″) grows only in the region where phosphorus is ion-implanted. In this embodiment, the oxide film has a film thickness of 100 nm. It is set according to the ion implantation conditions.

Then, as shown in FIG. 9 (e), after selectively removing the nitride film, BF ₂ is 60 KeV and 1 × 10 ¹³ / cm ₂ to form a p-type well region (22). ^{About 3} ions were implanted. Since the n-type well region (21) in which phosphorus is implanted is masked by the oxide film (4 ″), boron is not implanted.

When this substrate is heat-treated, the implanted impurities diffuse toward the inside of the substrate, so that FIG.
Well regions (21, 22) are formed as shown in FIG. The depth of the well is 3 to 4 μm.

Next, in order to grow an element isolation oxide film, the oxide film (4 ′, 4 ″) is once removed, and the surface is oxidized by about 10 nm as shown in FIG. (4 ′) is formed, and a nitride film (5 ″) is further deposited. As shown in FIG. 10 (c), the photoresist (1
Using the mask of 2), the nitride film is processed into a desired active region shape. Further, as shown in FIG. 10D, when an oxide film is grown, the oxidation selectively progresses, and a nitride film (5 ″) is formed.
An element isolation oxide film (2) grows in a region not covered with. The film thickness is 400 nm.

In this embodiment, the method of forming the diffusion layer in advance, which is shown in the first embodiment, is adopted, so that FIG.
As described above, a mask of photoresist (12) that opens the n-type well region (21) is formed, and BF ₂ is added to 20 Ke.
Implanted under the conditions of V, 1 × 10 ¹⁵ / cm ² , and the diffusion layer (1
3 ') was formed. In addition, before that, in order to improve the element isolation characteristics, phosphorus is ion-implanted under the condition that the peak concentration position comes to the interface between the element isolation oxide film (2) and the substrate,
A high concentration region (3 ') was formed. Specifically, divalent phosphorus ions were implanted at 200 KeV and 2 × 10 ¹³ / cm ² . This is 400 KeV for monovalent phosphorus ion, 1
Corresponding to × 10 ¹³ / cm ² , the peak position is near the interface of the element isolation oxide film (2). Further, in the silicon substrate, since phosphorus penetrates deeper than in the element isolation oxide film,
The distribution shown in the figure is obtained.

In order to do the same in the p-type well region, as shown in FIG. 11A, the n-type well region is covered with the photoresist mask (12), and the high concentration region (3 ") is first formed. ) And arsenic to form the diffusion layer (13 ″).

From this point onward, the process is the same as that of the first embodiment, and the nitride film (5) is provided as shown in FIG.
A groove is formed in this, a sidewall nitride film (5 ′) is formed on the sidewall of the groove as shown in FIG. 11C, and as shown in FIG.
A groove (6) is dug in the substrate to separate the diffusion layer. Next, FIG.
1 (e), the surface of the groove is oxidized, and ion implantation for adjusting the threshold voltage of the MOSFET is performed through the oxide film (7) to form a high concentration region (8 ″). Then, as shown in FIGS. 12A to 12C, formation of the gate electrode (10), sidewall oxide film (14)
, The diffusion layers (13a, 13b) are formed, and the final wiring (19) is formed to complete the complementary MOSFET.

By the way, if a groove is formed too deep with respect to the diffusion layer, a problem occurs that the current decreases. Therefore, in the first embodiment in which the diffusion layer is formed in advance, the depth of the groove is the diffusion. It is almost the same as the layer depth. Also,
Even when a diffusion layer is formed later as in the second embodiment, ions are implanted from an oblique direction, so the ion implantation conditions are controlled so that the junction interface is located at the corner of the trench gate.

It should be noted that by the conventional method, the complementary MO
When manufacturing SFET, n-type MOSFET and p-type M
The gate electrode of the OSFET also uses polycrystalline silicon containing a large amount of impurities of the same conductivity type. With this combination, it was difficult to adjust the threshold voltage because of the difference in work functions. Changing the conductivity of the impurities by the respective gate electrodes in order to eliminate the work function difference is
Since the gate electrodes are separately formed for the p-type MOSFET and the p-type MOSFET, the manufacturing process becomes complicated. According to the present embodiment, it is not necessary to separately form gate electrodes, the number of steps can be reduced, and the work function differences between tungsten and p-type or n-type substrates can be made substantially equal, so that the threshold voltage for each MOSFET can be set. Easier to do.

[0050]

EFFECT OF THE INVENTION By using the trench gate structure, the MOSF
It is possible to suppress the occurrence of the short channel effect of ET.
This is because the shallow diffusion layer is effectively formed by forming the recess. Further, by stacking the gate electrode on the surface of the substrate outside the recess via the first insulating film which is thicker than the gate insulating film, the overlapping capacitance between the gate electrode and the drain region is reduced, and the MOSFET
The switching delay time is reduced. Furthermore, when using a refractory metal such as tungsten for the gate electrode,
It is possible to realize a gate resistance which is about 1/10 that of a gate electrode mainly made of polycrystalline silicon. Further, when the above configuration is applied to each MOSFET of complementary MOSFETs and a refractory metal such as tungsten is used for its gate electrode,
Since the difference in work function between these metals and the n-type substrate and the p-type substrate is substantially equal, it becomes easy to set the threshold voltage for each MOSFET.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a conventional semiconductor device.

FIG. 3 is a manufacturing process diagram of the first embodiment of the present invention.

FIG. 4 is a manufacturing process diagram of the first embodiment of the present invention.

FIG. 5 is a manufacturing process drawing of the first embodiment of the present invention.

FIG. 6 is a manufacturing process drawing of the second embodiment of the present invention.

FIG. 7 is a manufacturing process drawing of the second embodiment of the present invention.

FIG. 8 is a manufacturing process drawing of the second embodiment of the present invention.

FIG. 9 is a manufacturing process diagram of the complementary MOSFET according to the third embodiment of the present invention.

FIG. 10 is a complementary MOSFET according to a third embodiment of the present invention.
Manufacturing process drawing.

FIG. 11 is a complementary MOSFET according to a third embodiment of the present invention.
Manufacturing process drawing.

FIG. 12 is a complementary MOSFET according to a third embodiment of the present invention.
Manufacturing process drawing.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Element isolation oxide film 3, 3 ', 3 "... High concentration region 4, 4', 4" ... Oxide film 5, 5 "... Nitride film 5 '... Sidewall nitride film 6 ... Trench 7 ... Oxidation High-concentration region 9 ... Gate oxide film 10 ... Gate electrode 11 ... Oxide film 12 ... Photoresist mask 13, 13 ′, 13 ″, 13a, 13b ... Diffusion layer 14 ... Sidewall oxide film 15, 18 ... Tungsten 16 ... Interlayer insulating film 19 ... Wiring 21, 22 ... Impurity layer

Claims (9)

[Claims] 1. A source / drain region comprises a high-concentration layer and a low-concentration layer, a recess is provided in a channel portion between the source / drain regions, and a gate electrode is provided in the recess via a gate insulating film, and The semiconductor device is characterized in that a desired portion of the substrate surface outside the recess has at least one field effect transistor in which the gate electrode is laminated via a first insulating film thicker than the gate insulating film. 2. One of said field effect transistors is a p-channel insulated gate field effect transistor, and the other one.
The semiconductor device according to claim 1, wherein the individual ones are n-channel insulated gate field effect transistors. 3. The semiconductor device according to claim 1, wherein the gate electrode is made of a refractory metal. 4. The semiconductor device according to claim 3, wherein the refractory metal is W or Mo. 5. Near the surface of the source and drain regions,
The semiconductor device according to claim 1, wherein a metal film or a metal silicide film is arranged. 6. The semiconductor according to claim 1, wherein a second insulating film having the same planar shape as that of the gate electrode is arranged on the gate electrode. apparatus. 7. A surface having a first insulating film having a desired thickness,
And, a first step of preparing a semiconductor substrate having a low-concentration layer to be a source / drain region at a desired depth, a hole is formed in a desired portion of the insulating film, and a recess is formed in the semiconductor substrate from the hole. Second step, third step of forming a gate insulating film in the recess, fourth step of forming a gate electrode of a desired shape on the gate insulating film and the first insulating film, masking the gate electrode Then, the fifth step of removing the first insulating film,
A sixth step of forming a side wall insulating film in a self-aligning manner on at least the side wall of the first insulating film and the gate electrode, and forming a high-concentration layer forming source and drain regions using at least the side wall insulating film as a mask. 7. A method for manufacturing a semiconductor device, which has the step of 7. 8. A first step of preparing a semiconductor substrate having a first insulating film having a desired thickness on the surface, a hole is formed in a desired portion of the insulating film, and a recess is formed in the semiconductor substrate from the hole. A second step of forming a gate insulating film in the recess, a fourth step of forming a gate electrode having a desired shape on the gate insulating film and the first insulating film, and a gate electrode. A fifth step of removing the first insulating film using the mask, a sixth step of providing a low-concentration layer forming source and drain regions in the portion where the first insulating film is removed, at least the first step. The seventh step of forming a sidewall insulating film on the sidewalls of the insulating film and the gate electrode in a self-aligned manner and the eighth step of forming a high-concentration layer forming a source / drain region using at least the sidewall insulating film as a mask. A method for manufacturing a semiconductor device having the same. 9. A surface having a first insulating film having a desired thickness,
There are a first conductivity type region and a second conductivity type region different from the first conductivity type region, and at a desired depth of each region, a conductivity type different from the respective conductivity types and a source and drain region are formed. A first step of preparing a semiconductor substrate having a concentration layer, a second step of forming a hole in a desired portion of an insulating film above each region and forming a recess in the semiconductor substrate from the hole, in each recess Forming a gate insulating film on the third
Step of forming a gate electrode having a desired shape on the gate insulating film and the first insulating film, respectively, and a fifth step of removing the first insulating film using the gate electrode as a mask. A step of forming a sidewall insulating film in a self-aligned manner at least on the sidewalls of the first insulating film and the gate electrode;
Of the first conductivity type or the second conductivity type is covered with a mask, and the high concentration layer forming the source and drain regions is formed in the other region by using at least the sidewall insulating film as a mask. A semiconductor device having a seventh step and an eighth step of covering the other region with a mask and forming a high-concentration layer forming source and drain regions in the one region by using at least the sidewall insulating film as a mask. Manufacturing method.