KR100483564B1 - MOSFET and manufacturing method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and a method for manufacturing the same, and by using a silicon-on-insulator (SOI) substrate, a device having a T-shaped gate shape is manufactured, thereby providing a gate length L ₁ ), and the gate length L ₂ viewed from the channel region is relatively short, so that a small channel can be easily formed, and the delay and resistance of the gate can be reduced to speed up the operation of the device.

In addition, the silicon layer thickness T ₀ of the source and drain regions 3a and 3b is thicker than the thickness T ₂ of the channel, so that the source / drain can be operated with low resistance.

Description

Field effect transistor and manufacturing method thereof

The present invention relates to a field effect transistor and a method for manufacturing the same. More specifically, the gate shape is formed in a 'T' shape using a silicon-on-insulator (hereinafter, referred to as SOI) substrate. Accordingly, the present invention relates to a field effect transistor and a method of manufacturing the same, which are capable of forming a small channel easily and reducing the signal propagation delay and resistance of the gate to speed up the operation of the device.

In general, metal-oxide-semiconductor field effect transistors (hereinafter referred to as 'MOSFETs') have been reduced in device size as part of high performance and high integration.

In the future, in order to implement a transistor having a minimum channel length to be used, it is essential to effectively suppress a short channel effect in which the potential of the channel region is affected by the drain voltage.

In recent years, many studies have been conducted to reduce the gate length to several tens of nm in order to realize high performance field effect transistor devices.

However, semiconductor devices published as a result of research have problems inherent in manufacturing process complexity and high production cost.

Therefore, in order to realize a high performance field effect transistor with short channel effect suppressed and excellent field effect characteristics, it is necessary to improve the device structure.

Therefore, in the case of using a scale-down device of a planar structure as it is in conventional bulk silicon, it is difficult to expect stable device operation. Thus, an electric field effect on an SOI substrate is an alternative to bulk silicon. How to make transistors has been studied for years.

In the case of a field effect transistor (hereinafter, referred to as a MOSFET) fabricated on an SOI substrate, the structure of the device may vary depending on the fully depleted type and partially depleted type operating modes. .

First, a device having a fully depleted mode of operation does not generate floating body characteristics such as a kink effect due to the substrate floating as a channel is completely depleted, and a subthreshold characteristic and a short channel characteristic are not generated. This is excellent.

In addition, the drain saturation current is increased due to an increase in channel mobility due to a lower vertical electric field.

However, the device having this fully depleted mode of operation has a very small source / drain resistance in the thin SOI substrate used for the fully depleted operation, resulting in a small drain current. It is difficult to apply due to the thin SOI substrate, but rather has the disadvantage that the junction breakage can occur.

In contrast, a device having a partially depleted mode of operation has the opposite characteristics of the advantages and disadvantages of the device having a fully depleted mode of operation described above. In addition, in a device having a partially depleted mode of operation, the body is floated and the substrate voltage becomes unstable, thereby adversely affecting the circuit design of the MOSFET.

As a result, a method for fabricating a MOSFET in an SOI substrate must be studied based on the device fabrication technology in bulk silicon while performing a fully depletion operation.

On the other hand, the method of forming the gate of the MOSFET has been proposed for several years ago, in addition to forming the gate through the optical method, using a side wall made in the channel direction to form a gate structure shorter than the originally designed gate length, In terms of manufacturing method and device structure, there was room for improvement to be utilized in actual device fabrication.

Accordingly, the present invention has been made to solve the above problems, by forming the gate through the side wall made in the channel direction, while solving the fine gate implementation and gate resistance and delay problems, while at the same time the resistance of the source / drain The purpose of the present invention is to provide a structure of a field effect transistor that is self-aligned, does not have a junction breakdown problem, and is self-aligned.

A preferred aspect for achieving the above object of the present invention is a source region 3a and a drain region formed on both sides of a silicon layer of a silicon on insulator (SOI) substrate 10 and spaced apart from each other. 3b);

A pair of insulating first sidewalls (14a, 14b) spaced between said source and drain regions (3a, 3b) and formed on top of a silicon layer as a channel region;

A gate (16 ") formed over said pair of first sidewalls (14a, 14b) and a silicon layer;

A gate insulating film (15) interposed between said gate (16 "), a pair of first sidewalls (14a, 14b), and a silicon layer;

A second sidewall 17a formed around the gate 16 ", a pair of first sidewalls 14a and 14b, and a side surface of the gate insulating layer 15, and formed on upper portions of the source and drain regions 3a and 3b, respectively. 17b);

A field effect transistor is provided, which is composed of silicide layers 18, 19, and 20 formed on the source and drain regions 3a, 3b and the gate 16 ", respectively.

Another preferred embodiment for achieving the object of the present invention described above is on top of the SOI substrate 10 composed of the first silicon layer 1, the silicon oxide film 2 and the second silicon layer 3. A first step of sequentially depositing the oxide film 11 and the nitride film 12;

A second step of sequentially removing the nitride film (12) and the oxide film (11) to expose a portion of the second silicon layer (3) and to form a region (13) in which a gate is to be formed;

A third step of partially etching the second silicon layer (3) exposed to the region (13) where the gate is to be formed by using the nitride film (12) as a mask to remove the film by a predetermined thickness;

The pair of first sidewalls 14a and 14b spaced apart from each other in the region 13 in which the gate is to be formed is covered from both sides of the exposed second silicon layer 3 to a part of the nitride film 12. Forming and reducing the exposed silicon layer by a fourth step;

A fifth step of covering the first sidewalls (14a, 14b) and the second silicon exposed portion (3a) of a reduced size to form a gate insulating film (15);

Forming a polycrystalline silicon layer 16 on the nitride film 12 and the gate insulating film 15, and removing and planarizing the polycrystalline silicon layer 16 to expose the upper surface of the nitride film 12; ;

The nitride film 12 and the oxide film 11 are removed by an etching process, and the dopant is doped by ion implantation to form source and drain regions 3a and 3b in the second silicon layer 3, and the polycrystalline silicon layer A seventh step of forming 16 'as a gate 16 ";

And an eighth step of forming silicide layers 18, 19, and 20 on the source and drain regions 3a, 3b and the gate 16 ", respectively. Is provided.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a cross-sectional view of a field effect transistor according to the present invention, formed on both sides of a silicon layer of an SOI substrate 10, and having source and drain regions 3a and 3b spaced apart from each other; A pair of insulating first sidewalls (14a, 14b) spaced between said source and drain regions (3a, 3b) and formed on top of a silicon layer as a channel region; A gate 16 "formed over said pair of first sidewalls 14a and 14b and a silicon layer; between said gate 16" and a pair of first sidewalls 14a and 14b and a silicon layer A gate insulating film 15 interposed therebetween; surrounding the side surfaces of the gate 16 ", the pair of first sidewalls 14a and 14b, and the gate insulating film 15, and forming the source and drain regions 3a and 3b. Second sidewalls 17a and 17b formed at upper portions thereof, and silicide layers 18, 19 and 20 formed at upper portions of the source and drain regions 3a and 3b and the gate 16 ", respectively.

Here, the gate 16 ″ is formed in a 'T' shape having a short gate length viewed from the channel region, thereby providing a gate length L _{1 of a} wide design window, and a gate length L viewed from the channel region. ₂ ) is relatively short, so the channel formation is easy, so the delay and resistance of the gate can be reduced.

2A to 2K are manufacturing process diagrams of the field effect transistor according to the present invention. First, the oxide film 11 and the nitride film 12 are sequentially deposited on the SOI substrate 10 (FIG. 2A).

At this time, the SOI substrate 10 has a structure in which the first silicon layer 1, the silicon oxide film 2 and the second silicon layer 3 are sequentially formed, and the SOI substrate 10 has a thickness of 30 to 80 nm. It is preferable to use as a substrate.

Thereafter, a photolithography process is performed to sequentially remove the nitride layer 12 and the oxide layer 11 to expose a portion of the second silicon layer 3 to form a region 13 on which a gate is to be formed. 2b)

Here, the width L ₁ of the region 13 in which the gate is to be formed is preferably 0.04 to 1.0 μm in consideration of the sidewall and gate length to be formed in a subsequent process.

Subsequently, using the nitride film 12 as a mask, the second silicon layer 3 of the SOI substrate 10 exposed to the region 13 on which the gate is to be formed is partially etched and removed by a thickness 'T ₁ '. (FIG. 2C)

At this time, after the partial etching process, the thickness T ₂ of the second silicon layer 3 remaining in the channel region is preferably in the range of 5 to 50 nm for the fully depleted operation.

In FIG. 2D, a portion of the nitride film 12 is disposed on both sides of the second silicon layer 3 exposing the pair of first sidewalls 14a and 14b spaced apart from each other in the region 13 in which the gate is to be formed. It is formed to wrap up to reduce the exposed silicon layer.

The first sidewalls 14a and 14b are subjected to a chemical vapor deposition (CVD) process to deposit an insulating film, and a second silicon layer is formed on the central portion of the deposited insulating film by an etch-back process. It is formed by removing so that the top of (3) is exposed (the exposed top surface is 3 ').

Here, the width L ₃ of the first sidewall has an important influence on determining the length L ₂ of the gate formed in a subsequent process.

Next, after the first sidewalls 14a and 14b are formed, the gate sidewalls 15 may be wrapped around the first sidewalls 14a and 14b and a part of the second silicon exposed portion 3 ′ having a reduced size. (Fig. 2e).

The gate insulating film 15 is formed through a thermal oxidation process, and thus is not formed on the nitride film 12.

Subsequently, a polycrystalline silicon layer 16 for forming a gate electrode is formed on the nitride film 12 and the gate insulating film 15 (FIG. 2F).

Thereafter, the polycrystalline silicon layer 16 is removed and planarized so that the upper surface of the nitride film 12 is exposed (FIG. 2G).

Here, the removal and planarization of the polycrystalline silicon layer 16 may be performed by a chemical mechanical polishing (CMP) or etch-back process.

When the polycrystalline silicon layer 16 is removed in this way, it is formed in a 'T' shape. This 'T' shaped gate structure provides the advantage of easy channel formation due to the gate length (L ₂ ), and provides a wide design window with the gate length (L ₁ ), thereby reducing the delay and resistance of the gate. Provide advantages.

Therefore, in the MOSFET of the present invention, since the length L ₂ of the gate electrode viewed from the channel region is shortened, the length of the channel region is also shortened.

Therefore, the short channel region has the advantage that the operation speed of the device can be increased, and a high-performance MOSFET can be realized.

In addition, if the width L ₁ of the region 13 in which the gate is to be formed is formed at 0.15 μm, and the length L ₃ of the first side walls 14a and 14b is formed at 0.03 μm, 0.15- (0.03 x 2 It is possible to manufacture a MOSFET having a gate length L ₂ viewed in a channel region of) = 0.09 mu m.

In FIG. 2H, the nitride film 12 and the oxide film 11 used for the gate formation are removed by an etching process, and the etching process is advantageous in terms of selectivity in that the wet etching process is performed rather than the dry etching process. The nitride film 12 is removed using a H ₃ PO ₄ solution at a temperature of 160 ° C., and the oxide film 11 is removed with a buffered HF solution at room temperature.

Next, the silicon layer exposed on the SOI substrate and the polycrystalline silicon layer 16 ′ used as the gate are doped with an n-type or p-type dopant by ion implantation to form a second silicon layer of the SOI substrate. Source and drain regions 3a and 3b are formed in (3), and polycrystalline silicon layer 16 'is formed as gate 16 "(FIG. 2I).

Here, since the silicon layer thickness T ₀ of the source and drain regions 3a and 3b is thicker than the channel thickness T ₂ , the MOSFET of the present invention provides the advantage of making a low resistance source / drain. do.

Subsequently, an insulating film is deposited on top of the source and drain regions 3a and 3b, and the insulating film is etched back to the pair of first sidewalls 14a and 14b and the gate 16 ". A pair of second sidewalls 17a and 17b are formed on the outside of each other (Fig. 2J).

Here, this process may be selectively performed in the present invention, and the insulating property of the source and drain 3a, 3b and the gate 16 "in the silicide process which is subsequently performed to the second sidewalls 17a and 17b. To keep it more secure.

Finally, a silicide process and an annealing process are performed to form a source silicide layer 19 on the source 3a, and a drain silicide layer 20 on the drain 3b. The MOSFET of the present invention is completed by forming the gate silicide layer 18 on the gate 16 ". (FIG. 2K)

Therefore, in the MOSFET of the present invention, the silicide layer is formed only on the top of the source 3a / drain 3b and the gate 16 " in the silicide process and the annealing process.

As described in detail above, the present invention forms a gate shape in a 'T' shape to provide a gate length L _{1 of a} wide design window, and the gate length L ₂ viewed from the channel region is relatively short, It is easy to form a very small channel and reduce the delay and resistance of the gate to speed up the operation of the device.

In addition, the silicon layer thickness T ₀ of the source and drain regions 3a and 3b is thicker than the thickness T ₂ of the channel, so that the source / drain can be operated with low resistance.

In addition, the manufacturing technology of the present invention has an effect that can be applied to the next-generation semiconductor technology for SOC (System-On-a-Chip), including high-speed, high-performance ultra-fine semiconductor device fabrication and design and fabrication of the corresponding semiconductor device structure Occurs.

Although the invention has been described in detail only with respect to specific examples, it will be apparent to those skilled in the art that various modifications and variations are possible within the spirit of the invention, and such modifications and variations belong to the appended claims.

1 is a cross-sectional view of a field effect transistor according to the present invention.

2A to 2K are manufacturing process diagrams of the field effect transistor according to the present invention.

<Description of the symbols for the main parts of the drawings>

1,3 first and second silicon layers 2: silicon oxide film

3a, 3b: source and drain regions 10: SOI substrate

11 oxide film 12 nitride film

13 regions 14a and 14b in which gates are to be formed, first sidewalls

15 gate insulating film 16 polycrystalline silicon layer

16 ": gates 17a, 17b: second sidewall

18,19,20: silicide layer

Claims (11)

delete delete A first step of sequentially depositing an oxide film (11) and a nitride film (12) on top of the SOI substrate (10) consisting of the first silicon layer (1), the silicon oxide film (2), and the second silicon layer (3); A second step of sequentially removing the nitride film (12) and the oxide film (11) to expose a portion of the second silicon layer (3) and to form a region (13) in which a gate is to be formed; A third step of partially etching the second silicon layer (3) exposed to the region (13) where the gate is to be formed by using the nitride film (12) as a mask to remove the film by a predetermined thickness; Partial surfaces of the nitride film 12 on both sides of the second silicon layer 3 exposing a pair of spaced apart first sidewalls 14a and 14b made of an insulating film inside the region 13 where the gate is to be formed. Forming a wrap so as to reduce the exposed silicon layer; A fifth step of forming a gate insulating film (15) surrounding the first sidewalls (14a, 14b) and a portion of the second silicon exposed portion (3 ') of a reduced size; Forming a polycrystalline silicon layer 16 on the nitride film 12 and the gate insulating film 15, and removing and planarizing the polycrystalline silicon layer 16 to expose the upper surface of the nitride film 12; ; The nitride film 12 and the oxide film 11 are removed by an etching process, and the dopant is doped by ion implantation to form source and drain regions 3a and 3b in the second silicon layer 3, and the polycrystalline silicon layer A seventh step of forming 16 'as a gate 16 "; And an eighth step of forming silicide layers (18, 19, 20) over the source and drain regions (3a, 3b) and gates (16 "), respectively. The method of claim 3, wherein Between the seventh and eighth stages, An insulating film is deposited on the source and drain regions 3a and 3b, and the insulating film is etched back to the outside of the pair of first sidewalls 14a and 14b and the gate 16 ". And forming a pair of second sidewalls (17a, 17b), respectively. The method according to claim 3 or 4, The SOI substrate (10) is a method of manufacturing a field effect transistor, characterized in that the thickness of 30 ~ 80nm. The method according to claim 3 or 4, The width L ₁ of the region (13) in which the gate of the second step is to be formed is 0.04 to 1.0 μm. The method according to claim 3 or 4, The first sidewalls 14a and 14b of the fourth step are subjected to a chemical vapor deposition (CVD) process to deposit an insulating film, and the center portion of the deposited insulating film is subjected to an etch-back process. And removing the upper part of the second silicon layer (3) so as to be exposed. The method according to claim 3 or 4, And the gate insulating film (15) of the fifth step is formed through a thermal oxidation process. The method according to claim 3 or 4, The removal and planarization of the polycrystalline silicon layer (16) of the sixth step is performed by a chemical mechanical polishing (CMP) or an etch-back process. The method according to claim 3 or 4, The polycrystalline silicon layer 16 is formed in a 'T' shaped gate structure by removing and planarizing the polycrystalline silicon layer 16 in the sixth step. . The method according to claim 3 or 4, The etching process of the nitride film 12 and the oxide film 11 of the fifth step, A method of manufacturing a field effect transistor comprising removing the nitride film (12) using a H ₃ PO ₄ solution at a temperature of 160 ° C. and removing the oxide film (11) with a buffered HF solution at room temperature.