JP2000022158A - Field effect transistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent deterioration in a field effect transistor which is formed at a semiconductor layer (SOI) on an embedded insulating layer. SOLUTION: In a field effect transistor, a semiconductor layer 103 made of single-crystal silicon of 10 nm in thickness is formed on a silicon substrate 101 with a hollow space 102 of 20 nm in thickness in between. An n+ polysilicon gate electrode 105 is formed on the semiconductor layer 103 via a gate insulating film 104 of 3 nm thickness in between. In addition, source drain regions 106 are formed so as to sandwich the lower part of the gate electrode 105.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor formed on a semiconductor layer (SOI) on a buried insulating layer and a method for manufacturing the same.

[0002]

2. Description of the Related Art It is well known that miniaturization of transistors is effective for high integration and high speed of LSI.
A field effect transistor is used in many LSIs. However, when the field effect transistor is miniaturized, a problem that a threshold voltage and an S factor change (performance degradation such as a short channel effect) occurs. Here, the threshold voltage is a gate voltage at which switching between a conductive state and a non-conductive state of the transistor occurs, and it is desirable that the threshold voltage does not change even when the size of the transistor changes.

The S factor is the amount of change in gate voltage required to change the magnitude of current flowing through a transistor by one digit when the gate voltage does not reach the threshold voltage. It is desirable that the S factor does not change even if the transistor is miniaturized. Note that the change (deterioration) of the threshold voltage or the S factor is mainly caused by a two-dimensional electric field (arrow A in FIG. 15) from the drain region to the channel region, which changes the potential of the channel formation region. Get up.

To solve this problem, for example, FIG.
It is reported that the field-effect transistor shown in FIG. 5 is effective (Literature: Omura et al., 1991, IEDM, Technical Digest, p. 679 (IED
M, Tech.Dig.)). In this element, the support substrate 150
1, a buried insulating layer 1502 is provided, and an SOI layer 1503 made of a thin silicon single crystal is provided thereon. The gate insulating film 1 is formed on the SOI layer 1503.
504 and a gate electrode 1505 are formed.
In the I layer 1503, an n ^{+ type} source region 1506 and a drain region 1507 are formed.

In the SOI layer 1503, the gate electrode 15
A channel is formed in a region located below the source region 05 and between the source region 1506 and the drain region 1507.
This region is hereinafter referred to as a channel formation region. In this element, the vertical depth X _j of the source region 1506 and the drain region 1507 is determined by the thickness of the SOI layer 1503. Therefore, X _j can be reduced by reducing the thickness of the SOI layer 1503. As _Xj decreases, the electric field from the drain region toward the channel (FIG. 15)
The middle arrow A) is weakened and the effect of changing the potential of the channel region is reduced, so that the above-described deterioration in transistor characteristics is suppressed.

This will be described with reference to a model shown in FIG. In FIG. 16, the same components are denoted by the same reference numerals as in FIG. Potential variation due to the two-dimensional electric field from the drain region 1507 described above can be considered as caused by a virtual capacity C ₁ corresponding to the capacitance between points p and the drain region 1507 of the channel formation region. Here, when the thickness X _j of the drain region 1507 is reduced, the area of the capacitor forming the capacitance C ₁ is reduced, so that the capacitance C ₁ is reduced. As a result, since reducing the electrostatic coupling through a C _1, the potential variation in the results channel formation region is reduced.

[0007]

However, the above-described characteristic deterioration due to miniaturization is caused by an electric field (arrow B in FIG. 15) passing through the buried insulating layer, as in the case of the electric field indicated by arrow A. . As described above, the lateral electric field (the electric field indicated by arrow B) passing through the buried insulating layer is generated not only from the side surface of the drain region (the interface between the drain region and the channel region) but also from the lower interface of the drain region. However, it cannot be effectively reduced only by making the drain region thinner. These lateral electric fields will be described with reference to FIG. Here, C ₁ is a virtual capacitance between an arbitrary point p and the drain side surface in the channel formation region, and C ₂ is a virtual capacitance between the point p and the drain bottom surface.

The capacitance C ₁ represents the electrostatic coupling between the drain side surface and the channel forming region, and the capacitance C ₂ represents the electrostatic coupling between the drain bottom surface and the channel forming region. . And the capacity C ₁ and the capacity C ₂
Has a positive correlation with the magnitudes of the electric fields indicated by arrows A and B, respectively. Capacitance C ₁ is reduced because the cross-sectional area of the drain side Smaller X _j as described above is decreased, capacitance C ₂ is not decreased even by reducing the X _j. In other words, no matter how small X _j is, the electrostatic coupling (the electric field indicated by the arrow B in FIG. 15) through the capacitor C ₂ remains, so that the fluctuation of the channel potential and the resulting threshold voltage, and
Deterioration of characteristics such as S factor cannot be reduced sufficiently.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to suppress the characteristic deterioration of a field effect transistor formed in a semiconductor layer (SOI) on a buried insulating layer. Aim.

[0010]

According to the present invention, there is provided a field-effect transistor comprising: a buried insulating layer formed on a substrate;
A semiconductor layer formed in contact with the buried insulating layer;
A gate electrode formed on the semiconductor layer via a gate insulating film; and a source and drain region formed from the surface of the semiconductor layer so as to sandwich the region except for a region below the gate electrode. Part of the insulating layer below the semiconductor layer (channel forming region) sandwiched between the source and drain regions was a low dielectric constant layer having a lower dielectric constant than silicon oxide. This structure involves a lateral electric field through the buried insulating layer (FIG. 1).
A low dielectric constant layer is provided on at least a part of the path indicated by arrow B) in FIG. As a result, the electric field indicated by the arrow B is reduced, so that the above-described deterioration in characteristics (change in threshold voltage or S factor) can be suppressed. The electric field of the arrow B is reduced
Electrostatic coupling through a buried insulating layer (virtual capacitance C ₂
This is because it is represented by ").

Further, the low dielectric constant layer is constituted by a cavity. By using a cavity, the dielectric constant can be significantly reduced, the electric field passing through the buried insulating layer can be further reduced, and the characteristic deterioration can be further suppressed. Further, the source / drain regions were formed so as to be in contact with the buried insulating layer. If there is a silicon layer having a high dielectric constant under the drain, the electric field indicated by the arrow C in FIG. 17 becomes strong because the silicon layer has a high dielectric constant. Then, the effect obtained by providing the low dielectric constant layer in the buried insulating layer and relaxing the electric field indicated by the arrow B cancels out, and the effect cannot be sufficiently enjoyed. In the present invention, this problem is solved by providing the source / drain regions so as to reach the interface between the semiconductor layer and the buried insulating layer. In addition, the low dielectric constant layer is extended under the source / drain region. As a result, the path of the electric field from the lower part of the drain region to the channel is more occupied by the low dielectric constant material, and the electric field passing through the buried insulating layer can be further reduced.
Characteristic deterioration can be further suppressed. This can be explained to be due to virtual capacitance C ₂ is further reduced. The cavity was formed so as to be in contact with the lower surface of the semiconductor layer. As a result, the path of the electric field from the lower part of the drain region to the channel is more occupied by the low dielectric constant material, the electric field passing through the buried insulating layer can be further reduced, and the characteristic deterioration can be further suppressed. This is the virtual capacity C
2 can be further reduced. In addition to the effects described above, the low dielectric constant region provided below the channel region has an effect of reducing the parasitic capacitance between the gate and the substrate and between the channel and the substrate, and is provided below the source / drain region. The low dielectric constant layer is
It has the effect of reducing the parasitic capacitance between the substrates, and contributes to the speeding up of the circuit constituted by the elements of the present invention.

In the field effect transistor according to the present invention, a semiconductor layer is provided on a substrate at a predetermined interval, and a semiconductor layer formed on a side of the semiconductor layer is supported on the substrate at an interval. The semiconductor device includes a side wall, a gate electrode formed on the semiconductor layer with a gate insulating film interposed therebetween, and source and drain regions formed from the surface of the semiconductor layer so as to sandwich the gate electrode except for a region below the gate electrode. I made it. Therefore, the region below the semiconductor layer sandwiched between the source and drain regions has a lower dielectric constant than silicon oxide. Further, by using an insulator for the side wall, conduction between the semiconductor and the substrate is prevented.

Further, according to a method of manufacturing a field effect transistor of the present invention, a buried insulating layer substrate having a semiconductor film formed on a supporting substrate via a buried insulating layer is prepared, and the semiconductor film is selectively formed. The semiconductor layer on which the element is formed is formed by etching and removal. Next, the buried insulating layer around the semiconductor layer is selectively removed so as to leave a region below the semiconductor layer, and a sacrificial layer is formed below the semiconductor layer. Next, a side wall made of a material different from the sacrificial layer is formed on the side surfaces of the semiconductor layer and the sacrificial layer. Next, an opening is formed in part of the side wall or part of the semiconductor layer to expose the sacrificial layer. Next, the sacrifice layer is removed through the opening by etching for selectively removing the sacrifice layer with respect to the support substrate, the semiconductor layer, and the side wall, and a cavity is formed in at least a part of a region below the semiconductor layer. . If a field-effect transistor is formed on the semiconductor layer thus formed, the semiconductor device is formed in a state having a low dielectric constant.

According to a method of manufacturing a field effect transistor of the present invention, a buried insulating layer substrate having a semiconductor film formed on a supporting substrate via a buried insulating layer is prepared, and the semiconductor film is selectively formed. A semiconductor layer on which an element is formed by etching is formed. Next, a buried insulating layer below the periphery of the semiconductor layer is selectively removed so as to leave a region below the semiconductor layer, and a sacrificial layer is formed below the semiconductor layer. Next, sidewalls made of a material different from that of the sacrifice layer are formed on the side surfaces of the semiconductor layer and the sacrifice layer. Next, an opening is formed in a part of the side wall to expose the side surface of the sacrificial layer. Next, the sacrifice layer is removed through the opening by etching for selectively removing the sacrifice layer from the support substrate, the semiconductor layer, and the side wall, and a cavity is formed below the center of the semiconductor layer. Next, a gate electrode is formed over the semiconductor layer with a gate insulating film interposed therebetween. Then, source / drain regions are formed in the semiconductor layers on both sides of the gate electrode. As a result, a region below the semiconductor layer sandwiched between the source and drain regions is formed to have a lower dielectric constant than silicon oxide.

Further, according to the method of manufacturing a field effect transistor of the present invention, a buried insulating layer substrate having a semiconductor film formed on a supporting substrate via a buried insulating layer is prepared, and the semiconductor film is selectively formed. A semiconductor layer on which an element is formed by etching is formed. Next, a buried insulating layer below the periphery of the semiconductor layer is selectively removed so as to leave a region below the semiconductor layer, and a sacrificial layer is formed below the semiconductor layer. Next, sidewalls made of a material different from that of the sacrifice layer are formed on the side surfaces of the semiconductor layer and the sacrifice layer. Next, a gate electrode is formed over the semiconductor layer with a gate insulating film interposed therebetween. Next, source / drain regions are formed in the semiconductor layers on both sides of the gate electrode. Next, an opening is formed in a part of the side wall to expose the side surface of the sacrificial layer. Then, the sacrifice layer is removed through the opening by etching for selectively removing the sacrifice layer from the support substrate, the semiconductor layer, and the side wall, so that a cavity is formed below the semiconductor layer. As a result, a region below the semiconductor layer sandwiched between the source and drain regions is formed to have a lower dielectric constant than silicon oxide.

According to a method of manufacturing a field effect transistor of the present invention, a buried insulating layer substrate having a semiconductor film formed on a supporting substrate via a buried insulating layer is prepared, and the semiconductor film is selectively formed. The semiconductor layer on which the element is formed is formed by etching away. Next, a buried insulating layer below the periphery of the semiconductor layer is selectively removed so as to leave a region below the semiconductor layer, and a sacrificial layer is formed below the semiconductor layer. Next, sidewalls made of a material different from that of the sacrifice layer are formed on the side surfaces of the semiconductor layer and the sacrifice layer. Next, an opening is formed in a part of the semiconductor layer to expose the side surface of the sacrificial layer. Next, the sacrifice layer is removed through the opening by etching for selectively removing the sacrifice layer from the support substrate, the semiconductor layer, and the side wall, and a cavity is formed below the center of the semiconductor layer. Next, a gate electrode is formed over the semiconductor layer with a gate insulating film interposed therebetween. Then, source / drain regions are formed in the semiconductor layers on both sides of the gate electrode. As a result, a region below the semiconductor layer sandwiched between the source and drain regions is formed to have a lower dielectric constant than silicon oxide.

Further, according to the method of manufacturing a field effect transistor of the present invention, a buried insulating layer substrate having a semiconductor film formed on a supporting substrate via a buried insulating layer is prepared, and the semiconductor film is selectively etched. After removal, a semiconductor layer on which an element is formed is formed. Next, a buried insulating layer below the periphery of the semiconductor layer is selectively removed so as to leave a region below the semiconductor layer, and a sacrificial layer is formed below the semiconductor layer. Next, sidewalls made of a material different from that of the sacrifice layer are formed on the side surfaces of the semiconductor layer and the sacrifice layer. Next, a gate electrode is formed over the semiconductor layer with a gate insulating film interposed therebetween. Next, source / drain regions are formed in the semiconductor layers on both sides of the gate electrode. next,
An opening is formed in a part of the semiconductor layer to expose a side surface of the sacrificial layer. Then, the sacrifice layer is removed through the opening by etching for selectively removing the sacrifice layer from the support substrate, the semiconductor layer, and the side wall, so that a cavity is formed below the semiconductor layer. As a result, a region below the semiconductor layer sandwiched between the source and drain regions is formed to have a lower dielectric constant than silicon oxide.

In the method of manufacturing a field effect transistor according to the present invention, a high etching rate layer is formed on a silicon substrate. Next, a semiconductor layer is formed on the high etching rate layer. Next, a buried insulating layer is formed on the semiconductor layer. Next, a part of the buried insulating layer is etched to form a recess having a reduced thickness. next,
The supporting substrate is bonded to the insulating layer by heating. Next, the silicon substrate is removed. Next, the high etching rate layer is selectively removed from the semiconductor layer to expose the semiconductor layer surface. Next, a gate insulating film, a gate electrode, and source / drain regions are formed over the semiconductor layer. Here, the gate electrode is formed on the gate insulating film, and the source / drain regions are formed in the semiconductor on both sides of the gate electrode. At this time, the region of the semiconductor layer sandwiched between the source / drain regions was arranged on the recess. Therefore, a region below the semiconductor layer sandwiched between the source and drain regions is formed to have a lower dielectric constant than silicon oxide.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 Hereinafter, a first embodiment of the present invention will be described.
FIG. 1 is a sectional view showing a configuration of the field-effect transistor according to the first embodiment of the present invention. In this field-effect transistor, first, a silicon substrate 101 has a thickness of 10 nm through a cavity 102 having a thickness of 20 nm, for example.
The semiconductor layer 103 made of single crystal silicon is formed. A gate electrode 105 made of n ⁺ polysilicon is formed on the semiconductor layer 103 via a gate insulating film 104 having a thickness of 3 nm.

The semiconductor layer 103 has a gate electrode 1
05 so as to sandwich the lower region of the source / drain region 10
6 is formed, and a channel forming region 1 is formed in a region below the gate electrode 105 sandwiched between the source / drain regions 106.
07 is formed. Here, the source / drain region 106 is formed, for example, by introducing phosphorus at 1 × 10 ²⁰ cm ^−3, to be an n ^{+ type} region. Then, the source / drain region 106 is formed so as to reach the lower interface of the semiconductor layer 103.

Here, as shown in FIG. 17, if the source / drain regions 1706 on both sides of the gate electrode 1705 have not reached the lower interface of the semiconductor layer 1703, the semiconductor layer 1703 still remains under the source / drain region 1706. Will exist. Then, in addition to the electric field indicated by the arrow B in FIG. 15, from below the source / drain region 1706,
Channel formation region 1707 through semiconductor layer 1703
Is formed. MO of general SOI structure
In SFETs, the semiconductor layer is silicon and has a higher dielectric constant than SiO _2, which normally forms a buried insulating layer. Accordingly, the electrostatic coupling C ₃ via the layer having a high dielectric constant (the semiconductor layer 1703 below the source / drain region 1706) becomes large, and the influence of the electric field of the drain region on the potential of the channel region increases. Deterioration of characteristics due to the formation is enhanced.

Therefore, as described above, the source / drain region 106 is formed so as to reach the lower interface of the semiconductor layer 103. Further, a channel formation region 107, for example, boron of 2 × 10 ¹⁸ cm ^-3 is introduced, p ^- also region is formed, the semiconductor layer 103 is an insulator side wall made of Si ₃ N ₄ at its end By 108, it is held on the silicon substrate 101 via the cavity 102. The insulator side wall 108 has, for example, a height of 30 nm and a thickness (horizontal direction in FIG. 1) of 30 nm.

As described above, this field effect transistor has a structure in which the semiconductor layer 103 is formed in an SOI structure formed on the cavity 102 which is an insulator. Here, the thickness of the semiconductor layer 103 is not particularly limited, but is preferably 100 nm or less from the viewpoint that the source / drain region 106 can reach below the semiconductor layer 103. If the semiconductor layer 103 is thicker than this, it is necessary to diffuse impurities for forming the source / drain region 106 so that the source / drain region 106 reaches below the semiconductor layer 106. Since the impurities diffuse laterally and enter the channel formation region 107, it is difficult to form a transistor having a fine channel length.

In the field-effect transistor according to the first embodiment, at least a part of the region located below the channel formation region 107 under the semiconductor layer 103 has Si
The cavity 102 which is a region having a lower dielectric constant than O ₂ was provided. Whether the cavity 102 is filled with a gas such as air,
The inside of the cavity 102 is brought into a vacuum state. The dielectric constant of a gas such as air is as low as about 1 (about 3.9 for SiO ₂ ), and vacuum is the state where the dielectric constant is theoretically the lowest.

Electrostatic coupling through cavity 102 (FIG. 1)
Since C ₂ of 6 equivalent) is small, according to the first embodiment, it can be effectively suppressed and deterioration of the characteristics of the transistor.

As described above, the first embodiment
In the configuration of the field effect transistor of the above, since the influence of the electric field passing through the buried insulating layer is reduced, the influence of the electric field from the source / drain region 106 via the semiconductor layer 103 (the electric field indicated by arrow A) is small. When used for a field-effect transistor in which contribution of an electric field (the electric field indicated by arrow B) through the layer is large, the effect is remarkable. For example, SOI
A field-effect transistor in which the thickness of the layer (semiconductor layer 103) is 30 nm or less is given.

The thickness of the cavity 102, which is a buried insulating layer having a lower dielectric constant than silicon oxide, is not particularly limited. When the cavity 102 is thick, an effect of reducing the parasitic capacitance of the source / drain region 106 can be obtained.

The relative dielectric constant of the gate insulating film 104 is ε1 (3.9 in the case of a silicon oxide film), the thickness is T _OX, and the relative dielectric constant of the region below the semiconductor layer 103 (buried insulating layer) is ε2. , Its thickness (the semiconductor layer 103 and the silicon substrate 1
T _BGAP ), the relationship between T _OX and T _BGAP is given by K × T _BGAP / ε2> T _OX / ε1.
The capacitance on the buried insulating layer side, that is, the capacitance between the lower interface of the semiconductor layer 103 and the silicon substrate 101 can be made 1 / K or less of the gate capacitance. Usually the value of K is 8 to 2
00 (K = 8 at ε1 = ε2 for a combination of a gate oxide film thickness of 10 nm and a buried insulating layer thickness of 80 nm, and K = 200 at a combination of a gate oxide film thickness of 2 nm and a buried insulating layer thickness of 400 nm).

Here, when the thickness of the low dielectric constant layer (the cavity 102 in FIG. 1) is reduced to, for example, 100 nm or less, the ratio of the electric field from the source / drain region 106 that can be terminated by the silicon substrate 101 increases. The effect of reducing the short-channel effect by reducing the electric field indicated by the arrow B in FIG. 15 also becomes remarkable. In a SOI structure having a normal buried insulating layer, when the buried insulating layer is thinned to obtain the same effect, the parasitic capacitance between the source / drain region and the substrate increases.
However, since the dielectric constant of the cavity 102 of the field effect transistor according to the first embodiment is smaller than that of silicon oxide, there is an advantage that the parasitic capacitance does not increase. The same can be said for the channel-to-substrate capacitance which causes the characteristic degradation such as an increase in the substrate bias effect and an increase in the S factor. According to the field effect transistor of the first embodiment, the capacitance can be reduced.

Incidentally, the gate oxide film (gate insulating film 1)
In general, the film thickness of 04) is preferably 3 nm to 12 nm. The thickness is set to 3 nm or more to prevent leakage current due to band-to-band tunneling.
If the circuit is designed so as not to impair the operating characteristics of the device, the thickness may be 3 nm or less. In addition, the thickness is 12
The value of nm or less is generally for securing a drain current in an LSI, but in a high breakdown voltage element or the like, it is more important to secure a withstand voltage by thickening a gate oxide film than securing a drain current. May be thicker than this. Further, the width of the insulator side wall 108 may be larger than that of the gate insulating film 104. In addition, as shown below, it may be formed continuously with the field oxide film in the element isolation region. In this case, the field oxide film may be made of the same material as the insulator side wall, or may be made of a different material. In addition, the side wall and the field oxide film adjacent to the side wall also serve as a path for releasing heat in the semiconductor to the substrate side.

By the way, as shown in FIG.
, The lower part of the semiconductor layer 103 or the silicon substrate 10
1 may be provided with a thin insulating film 110. For example, if the cavity 102 is exposed to the atmosphere, a natural oxide film naturally grows in this region to form a thin insulating film 110 and stabilize the interface. Further, a more stable interface can be formed by forming the thin insulating film 110 by thermal oxidation. Further, the insulating film 110 may be formed by a CVD method. When stabilizing the interface by forming these thin insulating films 110 artificially,
The thickness is preferably equal to or smaller than the thickness (12 nm or less) usually formed in the gate oxide film forming step.

This is because, when a thick oxide film is formed under the semiconductor layer 101, the electric field from the source / drain regions goes around the channel formation region through the oxide film. That is, the electric field indicated by the arrow B is not sufficiently reduced. This effect is small if the oxide film is thin. The results of a simulation of the effect of oxide films present above and below the cavity will be described. The SOI film thickness is 10 nm, the gate oxide film thickness is 3 nm, the gate length is 0.06 μm, and the threshold voltage change (hereinafter referred to as ΔV _th1) that occurs when the drain voltage is changed from 0.1 V to 1.0 V. ). In a device having a channel width of 0.06 μm, 10 ⁻⁷ A
The gate voltage at which the drain current flows was defined as the threshold voltage. The entire thickness of the buried insulating layer was 400 nm, SiO ₂ was adhered to the inside of the buried insulating layer and both above and below the buried insulating layer, and the region sandwiched by the SiO ₂ was a cavity. The thickness of the SiO ₂ deposited on the top and bottom (hereinafter, T _box1 , the thickness on one side and not the sum of both) was the same for both, and ΔV _th1 when the thickness was changed was examined.

FIG. 18 shows the result. The horizontal axis is T _box1 , and when T _box1 increases, ΔV _th1 increases. When there was no oxide film in the cavity, ΔV _th1 was 63 mV. ΔV _th1 is 1.5 times or less (94.5 mV or less) of the case without an oxide film
In order to _{achieve this} , the oxide film thickness T _box1 in the buried insulating layer is 12
nm or less. In order to make ΔV _th1 twice or less (94.5 mV or less) as compared with the case without an oxide film, the oxide film thickness T _box1 in the buried insulating layer needs to be 34 nm or less. Therefore, from the viewpoint of improving the characteristics of the transistor by suppressing the influence of the oxide film in the buried insulating layer, the oxide film thickness in the buried insulating layer is preferably 34 nm or less, more preferably 11 nm or less. If the oxide film thickness in the buried insulating layer is a film thickness (12 nm or less) formed in the normal gate oxide film forming step, ΔV
_th1 is 1.5 times or less (94.5 mV)
The following condition can be satisfied. In a transistor having a gate length of 0.18 μm or less, the gate oxide film thickness is often 6 nm or less. Therefore, in a transistor having a gate length of 0.18 μm or less, the oxide film thickness in the buried insulating layer is reduced by the gate oxide film. The thickness may be twice or less of the film thickness.

Although the case where oxide films are formed above and below the buried insulating layer has been described above, the upper oxide film adjacent to the source / drain regions is important. The result of may be used as it is. Further, in the buried insulating layer, a structure in which the low dielectric constant layer and SiO ₂ are formed in a layer shape, or a structure in which the low dielectric constant layer is included in SiO ₂ may be used. In this condition,
_Assuming that T _box1 , ΔV _th1 defined above is 100 mV
It can be said that it can be suppressed as follows. Suppressing ΔV _th1 to 100 mV or less requires a circuit such as a CMOS circuit.
It is preferable from the viewpoint of suppressing leakage current.

Next, a method of manufacturing the field-effect transistor according to the first embodiment will be described with reference to FIGS. In FIG. 4, (b), (d),
(F) and (h) show AA 'cross sections of (a), and (c) and (h)
(E), (g), and (i) show BB 'cross sections of (a). First, as shown in FIG.
First, a substrate having an oxide film 301 with a thickness of 80 nm and a semiconductor layer 103a made of single crystal silicon thereon is prepared, and a resist pattern 302 is formed thereon so as to cover a predetermined region. This resist pattern 302
It may be formed by a known photolithography technique.

Next, as shown in FIG. 3B, using the resist pattern 302 as a mask, the semiconductor layer 103a and the oxide film 301 are removed by, for example, reactive ion etching (RIE), and the semiconductor layer 103 is sacrificed. The state is formed on the oxide film 301a (sacrifice layer). Next, after removing the resist pattern 302, FIG.
(C) As shown in FIG.
The Si ₃ N ₄ film is formed of, which by etched back by RIE, to form an insulator side wall 108. Then, the whole is covered with a CVD oxide film 303 having a thickness of 20 nm.

Next, as shown in the plan view of FIG.
An opening 303a is provided at an appropriate position on the VD oxide film 303. The opening 303a may be formed as follows. First, a resist pattern having an opening at the opening 303a is formed on the CVD oxide film 303 by photolithography or the like. Then, using the resist pattern as a mask, the CVD oxide film 303 is removed by RIE or wet etching. Here, the wet etching can reduce the damage to the semiconductor layer 103 (FIGS. 4B and 4C).

Next, as shown in FIGS. 4D and 4E,
Due to the heated phosphoric acid, Si
The ₃ N insulator sidewalls 108 made of ₄ is selectively removed to form an opening 108a. As a result, as shown in FIG. 4D, the side surface of the sacrificial oxide film 301a is exposed in the opening 108a. Next, the whole is immersed in an etchant such as diluted hydrofluoric acid or buffered hydrofluoric acid, so that the etchant penetrates through the openings 303a and 108a, and the sacrificial oxide film 301a is selectively removed. At this time, the CVD oxide film 303 is also removed at the same time. Then, after the etchant is washed away with pure water or the like, and dried, the sacrificial oxide film 30 is removed.
A cavity 102 is formed at the position where 1a is located, as shown in FIGS. 4 (f) and 4 (g).

After that, the opening 108a is covered with SiO ₂ by depositing and etching back SiO ₂ by CVD or depositing an insulating film such as SiO ₂ by sputtering, and then the gate insulating film 104, the gate electrode 105, When the source / drain regions 106 are formed, the field effect transistor shown in FIG. 1 is completed. In this case, the height of the cavity 102 is 80 nm. In the above description, the resist pattern 302 is directly applied to the semiconductor layer 103a.
Although it is formed above, it may be formed via an oxide film. In this case, in the step corresponding to FIG. 3B, the oxide film may be etched at the same time, and the patterned oxide film may be removed after the formation of the sidewall insulating film 108.

Here, for example, the gate insulating film 104
May be formed by thermally oxidizing the surface of the semiconductor layer 103. In addition, for example, polysilicon may be deposited and processed by a known photolithography technique and etching technique to form the gate electrode 104. The source / drain regions 1 are self-aligned by ion implantation using the gate electrode 104 as a mask.
06 may be formed. The reverse is also acceptable.

Here, another method for closing the opening will be described. First, referring to FIG.
A method of closing an opening with two layers of silicon oxide films deposited by the method will be described. In FIG. 5,
(A) is a plan view, and (b), (d), (f),
(H) shows an AA ′ section of (a), and (c), (e),
(G), (i) have shown the BB 'cross section of (a). First, a semiconductor substrate (SOI substrate) having a buried oxide film 301 formed on a silicon substrate 101 and a single crystal silicon 103a formed thereon is prepared.
01 and single-crystal silicon 103a as resist patterns 30
2 and patterning as shown in FIG.
It is assumed that the semiconductor layer 103 is formed on the sacrificial oxide film 301a. Next, after removing the resist pattern 302, a Si ₃ N ₄ film is formed on the entire surface by CVD,
By etching back with the IE, the insulator side wall 10 is formed.
Then, as shown in FIG. 5A, an opening 108a is formed in a part thereof, and a cavity 102 is formed below the semiconductor layer 103 from which the sacrificial oxide film has been removed. This is the same as the state shown in FIGS.

Next, as shown in FIGS. 5B and 5C,
SiO ₂ is deposited on the entire surface by sputtering, and the film thickness is 100
An oxide film 501 of about nm is formed. At this time, the oxide film 501 is hardly formed below the semiconductor layer 103 because the deposition does not easily reach the side portion by the sputtering method. As a result, there is an advantage that the cavity 102 below the semiconductor layer 103 is not reduced. However, since the oxide film formed by the sputtering method may be fragile, following this deposition, the oxide film in nitrogen, an inert gas, or oxygen may be used.
For example, it is preferable to perform a heat treatment at 850 ° C. for about 10 minutes. Subsequently, as shown in FIGS. 5D and 5E,
This time, SiO ₂ is deposited on the entire surface by the CVD method and has a thickness of 5 μm.
An oxide film 502 of about 0 nm is formed.

Next, the oxide film 501 and the oxide film 502 are etched back by RIE. This etch back is performed until the surface of the semiconductor layer 103 is exposed. At this time, the oxide film 502 disappears in the flattened region,
In a state where the oxide film 501 is etched, a part of the oxide film 502 remains particularly on the side of the semiconductor layer 103 in the opening 108 region. Therefore,
Even if the etch back is performed until the surface of the semiconductor layer 103 is exposed, the oxide film 501 under a part of the oxide film 502 remains without being etched.
As shown in (f), the opening 108 of the insulator side wall 108 is formed.
a is obtained. In addition, as shown in FIG. 5G, the insulator side wall 1 where the opening 108 is not formed.
A part of the oxide film 501 also remains outside the area 08.

Next, a method of closing an opening with a silicon oxide film deposited only by the CVD method will be described.
When a silicon oxide film is deposited only by the CVD method, FIG.
As shown in (a), the silicon substrate 101 and the semiconductor layer 1
The oxide film 601 is formed up to the inside of the cavity 102 between the gate electrode 03 and the gate electrode 03. However, it is sufficient that the oxide film 601 is not formed in the central portion below the semiconductor layer 103.
It should be noted that FIG. 6A and FIG.
(C) and (d) show locations corresponding to the AA ′ section in FIG. 5 (a). Note that in order to prevent an oxide film from penetrating into the cavity, the pressure of a gas used in the CVD method may be set higher than usual.

Further, by depositing only by the CVD method, the cavity 102 between the silicon substrate 101 and the semiconductor layer 103 is formed.
6B, an oxide film 602 is formed as shown in FIG. 6B, and the oxide film 602 may also be formed at the lower central portion of the semiconductor layer 103 in some cases. However, if the thickness of the oxide film 602 at the lower central portion of the semiconductor layer 103 is small, the same result as in the state of FIG. 2 described above is obtained. Here, as the film thickness increases, the effect of forming the cavity decreases, but the effect of the formation of the cavity can be obtained if the cavity remains even if it is slight. That is, in a structure in which the semiconductor layer 103 is formed on the silicon substrate 101 via a predetermined buried insulating layer, the buried insulating layer is partially formed of silicon oxide. Is replaced by a space, the dielectric constant of the buried insulating layer can be reduced. As a result, the effects of the short channel effect and the channel-substrate capacitance in the first embodiment can be obtained.

Here, as shown in FIG. 6C and FIG. 6D, the spacer 603 or the spacer 60 is formed in the opening.
5 may be formed to reduce the opening area. This makes it difficult for the deposit to enter the cavity 102 between the silicon substrate 101 and the semiconductor layer 103 even if the oxide film is deposited by CVD. As a result, FIG.
As shown in FIG. 6C and FIG. 6D, the oxide film 604 or the oxide film 606 can be formed in a state where the opening is almost closed. Here, for example, as shown in FIG. 5A, when the opening 108a is formed by removing a part of the insulator side wall 108 by etching, the etching is stopped halfway, so that the above-described spacer is formed. 605
May be formed. After the opening 108a is completely formed, the spacer 603 may be formed by newly depositing an insulator (to the extent that the opening is not completely closed by sputtering) and forming a pattern. .

In the above description, an opening is formed in a part of the insulator side wall formed on the side of the semiconductor layer having the SOI structure, and the sacrificial oxide film below the semiconductor layer is removed from the opening. It is not limited. An opening may be formed in a semiconductor layer having an SOI structure. That is, first,
As shown in FIG. 7A, in a state where the semiconductor layer 103 supported by the insulator side wall 108 is formed on the silicon substrate 101, a diameter of about 0.2 μm is formed at a location near the periphery of the semiconductor layer 103. Opening 701 is formed. Then, the cavity 102 may be formed below the semiconductor layer 103 by etching through the opening 701.

In this case, after the formation of the cavity 102, C
By depositing, for example, 100 nm of SiO ₂ by VD and etching it back, the opening 701 may be closed with an insulating film 702 as shown in FIG. As described above, the step of closing the opening may be performed immediately after formation of the cavity 102, or after formation of the transistor structure or during formation (for example, after gate oxidation).
In the step shown in FIG. 4, the buried oxide film of the SOI substrate is used as a sacrificial layer, and a cavity is provided below the semiconductor layer by extracting the sacrificial layer, so that the thickness of the semiconductor layer (SOI layer) and the thickness of the buried insulating film layer are reduced. Controllability with respect to thickness and uniformity in these film thicknesses are ensured. SOIMO
In an SFET, the thickness of a semiconductor layer (SOI layer)
It is desirable that the thickness of the buried insulating film layer be well controlled and that these film thicknesses be more uniform. Normal S
In the method of extracting a buried oxide film of an OI substrate (for example, SIMOX, lamination, etc.) and forming a cavity, a conventional SOI used as a raw material is used for the thickness of a semiconductor layer (SOI layer) and the thickness of a buried insulating film layer. The same good uniformity as the substrate is obtained.

Since dilute hydrofluoric acid hardly reacts with Si, the step of removing the buried oxide film using dilute hydrofluoric acid (HF, buffered hydrofluoric acid, etc.) to form a cavity may damage the semiconductor layer. The method of the present embodiment is also excellent in not giving A cavity may be formed by forming a transistor on a normal silicon substrate and removing the silicon substrate under the transistor by etching, but the cavity is formed by removing the buried oxide film shown in FIG. The process is performed, as described above, on the semiconductor layer (SO
It is excellent in the controllability with respect to the thickness of the I layer), the thickness of the buried insulating film layer, and the uniformity of these film thicknesses. Also,
Since the buried oxide film is subsequently removed from the opening after providing the insulator side wall serving as a support, the semiconductor layer does not peel off even if the buried oxide film is removed. Further, as described later, a method of extracting a buried oxide film after forming a structure required for a transistor such as a source / drain region involves a stress generated around a cavity due to a heat treatment for forming a source / drain region or the like. Can be reduced.

Second Embodiment Next, a method of manufacturing a field effect transistor according to a second embodiment of the present invention will be described. First, as in FIG. 3A of the first embodiment, a substrate having an oxide film 301 with a thickness of 80 nm on a silicon substrate 101 and a semiconductor layer 103a made of single crystal silicon thereon is prepared. Resist pattern 302 so as to cover a predetermined area.
To form This resist pattern 302 may be formed by a known photolithography technique. Next, similarly to FIG. 3B, using the resist pattern 302 as a mask, the semiconductor layer 103a and the oxide film 301 are removed by, for example, reactive ion etching (RIE), so that the semiconductor layer 103 becomes a sacrificial oxide film 301a ( (Sacrifice layer).

Next, after the resist pattern 302 is removed, as shown in FIG. 8C, a Si ₃ N ₄ film having a thickness of 30 nm is formed on the entire surface by CVD, and this is etched back by RIE. Then, an insulator side wall 108 is formed. Next, a gate insulating film 104 is formed over the semiconductor layer 103.
The gate electrode 105 is formed through the process. Next, the source / drain regions 106 are formed in a self-aligned manner by ion implantation using the gate electrode 105 as a mask. These may be performed by known processes (gate oxidation, deposition of gate polysilicon and patterning by RIE, formation of source / drain regions by ion implantation, impurity diffusion, and the like), and a field effect transistor is formed.

Next, a gate sidewall 802 is formed as shown in FIG. 8B by depositing a 10 nm-thick Si ₃ N ₄ film and etching it back. The gate insulating film 104 is protected by the gate side wall 802. Next, as shown in FIG.
An opening 803 is formed near the insulator side wall 108 of FIG. This is because of the well-known photolithography technology and RIE
And the like.

After forming the opening 803,
By immersing the silicon substrate 101 in dilute hydrofluoric acid,
Dilute hydrofluoric acid enters through the opening 803 to form a sacrificial oxide film 801.
Is removed. At the time of this etching, the gate insulating film 104 remains without being etched due to the presence of the gate sidewall 802 made of Si ₃ N ₄ . As a result, as shown in FIG. 8D, between the semiconductor layer 103 and the silicon substrate 101,
A cavity 102 will be formed. After the etching with the dilute hydrofluoric acid, the dilute hydrofluoric acid is removed from the silicon substrate 101 by rinsing with pure water or the like, and then dried.

Next, as shown in FIG. 8E, an interlayer insulating film 804 is formed by depositing silicon oxide to a thickness of about 500 nm by the CVD method. At this time, the deposited silicon oxide enters from the opening 803 to a part of the end region of the cavity 102 and closes the opening 803. As described above, a field-effect transistor having an SOI structure in which a buried insulating layer having a lower dielectric constant than silicon oxide is formed under the semiconductor layer 103 is formed. In the second embodiment, the opening for forming the cavity 102 is simultaneously closed at the time of forming the interlayer insulating film on the field-effect transistor.

In the above description, a cavity is formed from an opening formed in a semiconductor layer, and the opening is closed when an interlayer insulating film is formed. However, the present invention is not limited to this. As described below, a cavity may be formed from an opening formed in an insulator side wall supporting a semiconductor layer, and the opening may be closed when an interlayer insulating film is formed. That is, as shown in FIG. 9A, when a cavity 102 is formed by an opening formed on a side portion between a silicon substrate 101 and a semiconductor layer 103, silicon oxide is deposited to a thickness of about 500 nm by a CVD method. Thus, the interlayer insulating film 901 may be formed.
At this time, part of the interlayer insulating film 901 enters below the semiconductor layer 103 from the opening at the end of the semiconductor layer 103 and closes the opening.

As shown in FIG. 9B, a cavity 102 is formed by an opening formed on the side between the silicon substrate 101 and the semiconductor layer 103, and silicon oxide is formed to a thickness of about 500 nm by sputtering. By depositing, the interlayer insulating film 902 may be formed. According to the sputtering method, part of the interlayer insulating film 902 does not enter much below the semiconductor layer 103 from the opening at the end of the semiconductor layer 103,
The opening can be closed. Also, the silicon substrate 101
When a cavity 102 is formed by an opening formed in a side portion between the semiconductor layer 103 and the semiconductor layer 103 and silicon oxide is deposited to a thickness of about 500 nm by a CVD method, a spacer 90 is formed in the opening.
3 is formed and narrowed and then deposited to form an interlayer insulating film 9.
04 may be formed. When the opening is narrowed by the spacer 903 in this manner, the opening can be closed without a part of the interlayer insulating film 904 penetrating much below the semiconductor layer 103.

In FIG. 9, a gate electrode 105 is formed on the semiconductor layer 103 via a gate insulating film 104, and the gate electrode 10 is formed on the semiconductor layer 103.
5 so that the source / drain regions 106
Are formed to form a field-effect transistor. Here, a buried insulating layer having a dielectric constant lower than that of silicon oxide is provided between the semiconductor substrate 101 and the lower portion of the semiconductor layer 103, particularly, a region sandwiched between the source / drain regions 106. Instead of using the cavity 102 as it is, the inside of the cavity may be filled with a material having a lower dielectric constant than SiO ₂ , such as fluorinated amorphous carbon or SiOF. These materials may be formed by CVD or the like having good covering properties.

In the manufacturing method for forming a cavity after forming the gate or the source / drain regions, the interlayer insulating film is formed similarly to the manufacturing method described in the first embodiment (the method according to FIGS. 5, 6, and 7). The opening may be closed before the formation. If not all of the buried insulating layers are in the low-k region, at least the source
It is effective to provide a region having a lower dielectric constant than SiO2 in a region including a lower portion of a connection portion between the drain region and the channel formation region. Further, as shown in FIG. 9A, a region having a dielectric constant lower than that of SiO ₂ is provided in one continuous region including the lower part of the connection between the channel formation and the two source / drain regions sandwiching the channel. Is effective.

The electric field in the lateral direction passing through the buried insulating layer (B in FIG. 15) passes through the buried insulating layer located below the connection between the source / drain region and the channel forming region. It is effective to lower the dielectric constant of the buried insulating layer below the dielectric constant of SiO ₂ below the connection part of the drain region in order to reduce the influence of the lateral electric field. Further, with respect to two connection portions forming source / drain regions on both sides of the channel formation region, a region having a lower dielectric constant than SiO ₂ is formed in one continuous region including a lower portion of both connection portions. The method of providing is to replace all the paths of the electric field in the lateral direction passing through the buried insulating layer located under the channel forming region and under the connection portion with a material having a low dielectric constant. It is more effective to reduce the effect of the electric field.

Third Embodiment Next, a method of manufacturing a field-effect transistor according to a third embodiment of the present invention will be described. by the way,
As shown in FIG. 10, the formation region 1001 of the above-described field-effect transistor is surrounded by an element isolation region 1002 for element isolation. Then, for example, the gate electrode 105 is separated from the semiconductor layer 103 by the element isolation region 100.
2 and is formed to extend over. In FIG. 10, an insulator sidewall 108 is formed on the side surface of the semiconductor layer 103, and a gate sidewall 1102 is formed on the side surface of the gate electrode 105.
Are formed. In this element isolation region 1002,
A buried insulating layer exists in an SOIMOSFET in which a normal mesa isolation is performed, and a buried insulating layer and a field oxide film exist in a SOIMOSFET in which a normal LOCOS isolation is performed. However, since there is a thick insulating layer between the gate electrode and the silicon substrate, the parasitic capacitance hardly causes a problem.

However, in the state described above,
Except for the region 1001 where the field-effect transistor is formed, there is almost no insulating film covering the silicon substrate 101. For example, when the gate insulating film 104, the gate electrode 105, and the like are formed following FIGS. 4F and 4G, only the gate insulating film 104 is provided below the gate electrode 105 extending to the element isolation region 1002. Will not exist. As described above, in a state where the silicon substrate 101 and the gate electrode 105 are insulated only by the gate insulating film 104, the parasitic capacitance between them may adversely affect the operation characteristics of the field-effect transistor.
Therefore, it is better to newly form a field oxide film in the element isolation region 1002.

Hereinafter, the formation of the field oxide film will be described with reference to FIG. FIG. 11 shows a cross section taken along the line AA ′ of FIG. First, as shown in FIG. 11A, in a state where a semiconductor layer 103 having a cavity 102 below and supported by an insulator side wall 108 is formed on a silicon substrate 101, silicon oxide is formed to a thickness of about 150 nm over the entire area. Is deposited to form an insulating film. The insulating film is flattened and polished by chemical mechanical polishing (CMP) to expose the semiconductor layer 103, and its periphery is filled with a field oxide film 1101. After this, FIG.
As shown in (b), a gate electrode 105 is formed via a gate insulating film 104, and subsequently, a field effect transistor is formed by forming a source / drain region or forming a gate sidewall 1102. I just need.

As a result, as shown in FIG. 11B, since the gate electrode 104 extending from the semiconductor layer 103 and the silicon substrate 101 are separated from each other by the field oxide film 1101, the parasitic capacitance is almost a problem. Will not be. Although the flatness is inferior to the structure shown in FIGS. 11A and 11B,
A field oxide film 1101 is deposited by CVD in a state where a semiconductor layer 103 having a cavity 102 is formed below the semiconductor layer 103 and supported on the semiconductor layer. Then, a step of removing the field oxide film 1101 by photolithography and RIE may be used. In this case, the same effect can be obtained. This is shown in FIG.

Further, in the step of FIG. 3C, the Si ₃ N ₄ film deposited over the whole is made thicker, for example, to 200 nm. Then, after covering with a resist except the central part of the semiconductor layer,
After etching the Si3N4 film by RIE or the like, FIG.
(C) Side wall 108 and field insulating film 110
1 obtains a structure formed of an integral Si3N4 film. According to this method, the number of steps can be shortened as much as no field insulating film is deposited again. Further, the formation of the field oxide film 1101 described with reference to each drawing of FIG.
After the formation of the field oxide film, or further formation of the gate electrode and the source / drain regions, the cavities are removed after the cavities have been formed (the sacrifice layer has not been removed). May be formed. With this method, it is possible to prevent the thermal stress related to the formation of the field oxide film from affecting the periphery of the cavity.

Fourth Embodiment Next, a method of manufacturing a field-effect transistor according to a fourth embodiment of the present invention will be described. In the third embodiment, the field oxide film is newly formed. However, the present invention is not limited to this. First, FIG.
As shown in FIG. 1, an oxide film 301 is formed on a silicon substrate 101, and a semiconductor layer 10 made of single crystal silicon is formed thereon.
3a is formed, and a resist pattern 302 is formed thereon so as to cover a predetermined region. This resist pattern 302 may be formed by a known photolithography technique.

Up to this point, the manufacturing method is the same as that described with reference to FIG. However, in the fourth embodiment, as shown in FIG. 12B, only the semiconductor layer 103a is selectively etched using the resist pattern 302 to form the semiconductor layer 103. Next, this time, as shown in FIG. 12C, a resist pattern 1201 in which a region of a predetermined width around the semiconductor layer 103 is opened like a slit is provided. The resist pattern includes a resist pattern 1201 on the semiconductor and a resist pattern 1203 on the buried insulating layer, and the slit is provided between the two. The width of the slit is, for example, 2 μm
It should be about degree. Resist patterns 1201 and 12
03 may be formed simultaneously after the resist pattern 302 is removed. Alternatively, the resist pattern 302
Is left without being removed, and this is
The resist pattern 1201 may be formed by applying a resist thereon and performing exposure and development.

Next, by selectively etching the oxide film 301 using the resist pattern 1201 as a mask, a sacrificial oxide film 301a is formed below the semiconductor layer 103, as shown in FIG. , Semiconductor layer 103
A field oxide film 12 is formed on the surrounding silicon substrate 101.
02 is obtained. After that, the resist pattern 1201 is removed, and a thickness of 120 n
By depositing the the Si ₃ N ₄ film of m, is etched back, as shown in FIG. 12 (e), the insulator sidewalls 108
Is formed, and the subsequent steps may be performed in the same manner as in the first embodiment. As a result, according to the fourth embodiment, there is no need to newly form a field oxide film 1101 as described with reference to FIG. 11 of the third embodiment.

The manufacturing method 00 relating to the element isolation region described in the third and fourth embodiments is applied to a manufacturing method in which a cavity is opened after forming a gate or a source / drain region as in the second embodiment. May be. Further, the structure relating to the element isolation region described in the third and fourth embodiments may be applied to a structure obtained by opening a cavity after forming a gate or a source / drain region as in the second embodiment. For example, between the steps of FIGS. 8A and 8B, a step of forming a field similar to that of FIG. 11A or 11C may be inserted. After the structure of FIG. 12E is obtained, a gate electrode and source / drain regions may be formed first, and then a cavity may be formed.

Embodiment 5 Next, a method of manufacturing a field effect transistor according to a fifth embodiment of the present invention will be described. Below,
A manufacturing method by lamination will be described. First, as shown in FIG. 13A, a high etching rate layer 1302 is formed on a silicon substrate 1301, and a non-doped silicon layer 1303 is formed thereon. Here, the high etching rate layer 1302 may be made of porous silicon provided by hydrogen ion implantation or silicon introduced with a large amount of impurities such as phosphorus, and is less likely to be etched by an appropriate etchant than the non-doped silicon layer 1303. A material may be used. In addition, the silicon layer 1303
Is a layer having a low impurity concentration formed by vapor phase epitaxial growth, and has a thickness of, for example, 100 nm.

Next, as shown in FIG. 13B, an insulating film 1304 having an opening partly removed is formed on the silicon layer 1303. In the opening, the lower silicon layer 1303 may be exposed or the insulating film 1304 may be thin. Then, FIG.
As shown in FIG. 3C, the support substrate 1 is formed on the insulating film 1304.
305 is bonded by heating. As a result, a cavity 1306 is formed between the support substrate 1305 and the silicon layer 1303.

Next, as shown in FIG. 13D, the silicon substrate 1301 is removed. At this time, the silicon substrate 1301 is etched and removed by a mechanical method such as etching, grinding, polishing or the like using a mixed solution of hydrofluoric acid and nitric acid. After that, only the high etching rate layer 1302 is selectively etched away using a mixed solution of hydrofluoric acid and nitric acid having a low concentration or an etching solution obtained by adding acetic acid, iodine, or the like thereto. Here, the combination of the material of the high etching rate layer and the etching solution may satisfy the condition that the etching rate of the high etching rate layer is higher than that of the silicon layer 1303 on the surface. Since the silicon layer 1303 is hard to be etched by this etching, it is easy to stop the etching at the surface of the silicon layer 1303.

Then, the silicon layer 1303 is patterned and separated into a planar shape so as to cover the region on each cavity 1306 forming portion, and a semiconductor layer 1313 having an SOI structure is formed as shown in FIG. On this, a gate electrode 1315 is formed via a gate insulating film 1314, and the source / drain regions 131 are formed in the semiconductor layers 1313 on both sides thereof.
By forming 6, the field-effect transistor according to the fifth embodiment is formed. The field effect transistor has a source / drain region 1 sandwiched between a region on a support substrate 1305 and a semiconductor layer 1313.
Below the channel formation region between 306 is a cavity 1306 which is a buried insulating layer having a lower dielectric constant than silicon oxide. Note that the uneven oxide film may be provided not on the non-doped silicon layer but on the support substrate side. That is,
Instead of depositing an oxide film on the non-doped silicon layer, a method may be used in which an oxide film is deposited on a support substrate, irregularities are formed on the oxide film, and then the laminate is laminated. Further, the oxide film may be completely removed from the concave and convex portions, or may be processed so that a part of the oxide film remains.

Embodiment 6 Hereinafter, a sixth embodiment of the present invention will be described.
Also in the sixth embodiment, a method of manufacturing a field-effect transistor by bonding will be described. First, as shown in FIG. 14A, a high etching rate layer 1402 is formed on a silicon substrate 1401, and a non-doped silicon layer 1403 is formed thereon. Here, the high etching rate layer 1402 may be formed using porous silicon or silicon introduced with a large amount of impurities such as phosphorus provided by hydrogen ion implantation. It may be used. The silicon layer 1403 is a layer with a low impurity concentration formed by vapor phase epitaxial growth and has a thickness of 100 nm. The above is the same as in the fifth embodiment.

Next, as shown in FIG. 14B, a low dielectric constant insulating layer 1404 is formed on the silicon layer 1403. This low dielectric constant insulating layer 1404 is made of, for example, SiO 2
A material having a lower dielectric constant than bulk silicon oxide, such as F or porous SiO _2, may be used. Next, FIG.
As shown in (2), a supporting substrate 1405 is bonded to the surface of the low dielectric constant insulating layer 1404 by heating. Next, as shown in FIG. 14D, the silicon substrate 1401 is removed, and additionally, the high etching rate layer 1402 is removed.

The removal of the silicon substrate 1401 is the same as that of the above-described fifth embodiment. For example, etching using a mixed solution of hydrofluoric acid and nitric acid, or a mechanical method such as grinding and polishing is used. Next, for example, only the high etching rate layer 1402 is selectively etched away using a mixed solution of hydrofluoric acid and nitric acid having a low concentration or an etching solution obtained by adding acetic acid, iodine, or the like thereto. As a result, a state where the silicon layer 1403 is formed over the supporting substrate 1405 with the low dielectric constant insulating layer 1404 interposed therebetween is obtained.

Then, the silicon layer 1403 is patterned and separated so as to leave a predetermined region, and a semiconductor layer 1413 having an SOI structure is formed as shown in FIG.
On this, a gate electrode 1 is interposed via a gate insulating film 1414.
When the 415 is formed and the source / drain regions 1416 are formed in the semiconductor layers 1413 on both sides thereof, the field effect transistor according to the sixth embodiment is formed. In this field-effect transistor, a buried insulating layer having a dielectric constant lower than that of silicon oxide is provided below a channel forming region between a source / drain region 1416 and a region on a supporting substrate 1405 and a semiconductor layer 1413. A low dielectric constant insulating layer 1404 is formed.

Hereinafter, another embodiment will be described.
In the first to sixth embodiments, the following configuration may be used. In the above-described field-effect transistor of the present invention, the impurity introduced into the source / drain region is not limited to the above-described phosphorus, and arsenic or another donor may be used. In the above description, the configuration of the n-channel transistor has been described, but the same applies to the configuration of the p-channel transistor. In this case, acceptors such as boron may be introduced into the source / drain regions. The concentration of these impurities introduced into the source / drain regions is 5
The range may be about × 10 ¹⁸ cm ⁻³ to about 2 × 10 ²¹ cm ⁻³ . Generally, 1 × 10 ¹⁹ cm ⁻³ to 2 × 10 ²⁰
cm ^-3 . These may be realized so that the resistance of the source / drain region can be reduced and the crystallinity of the region can be ensured.

In the case of forming an n-channel transistor, an impurity such as boron may be used as an impurity to be introduced into a channel formation region sandwiched between source / drain regions. In the case of forming a p-channel transistor, a donor such as phosphorus or arsenic may be used as an impurity to be introduced into a channel formation region. These impurity concentrations generally range from 2 × 10 ¹⁷ cm ^-3 to 5
It may be set to a range of × 10 ¹⁸ cm ^-3 and may be set as appropriate so as to satisfy a desired threshold value in the operation of the transistor. From the viewpoint of suppressing impurity scattering, the impurity concentration is preferably set to 2 × 10 ¹⁸ cm ⁻³ or less.

The above-described impurity concentration is obtained when polysilicon is used for the gate electrode. For example, n
In a channel transistor, when a gate electrode is formed using a material having a higher work function than polysilicon or n ⁺ -type polysilicon, or when a part in contact with a gate insulating film is formed using a material having a higher work function, channel formation is performed. The impurity concentration of the region is 2 × 10 ^{17 as described above.}
The concentration may be less than cm ⁻³ . Further, a donor having the same or lower concentration may be introduced into the channel formation region. Typically, an impurity may not be introduced into the channel region. The gate electrode may be formed after the formation of the source / drain regions by using a buried gate forming process or a method other than self-alignment.

When a material having a higher work function than that of n ^{+ type} polysilicon is used for the gate electrode, it has an effect of increasing the threshold value of the operation of the transistor. Is not required. Here, as a material having a larger work function than the n ^{+ type} polysilicon, a refractory metal or a refractory metal compound such as TiN, Mo, W, tungsten silicide, molybdenum silicide, or a refractory metal silicide is used. Is raised.

In a p-channel transistor,
When a gate electrode made of a metal as described above is used, the impurity concentration of the channel formation region may be lower than the above-described value. Alternatively, acceptors having the same or lower concentration may be introduced. Also in this case, typically, it is sufficient to prevent impurities from being introduced into the channel region. Also, an appropriate potential may be applied to the silicon substrate in order to set the threshold to a desired value. This can be achieved by applying a negative potential in the case of an n-channel transistor and applying a positive potential in the case of a p-channel transistor.

The threshold voltage (gate voltage) of the above-described field effect transistor according to the present invention may be the same as that of a transistor used in an integrated circuit such as a normal memory or a logic circuit. For example, when an n-channel transistor is used, the threshold value is set to 0.1 V
Should be 1V. In the case of a p-channel transistor, the threshold value is changed from -1 V to -0.1.
V. However, when a high voltage is applied to a high breakdown voltage transistor or a power transistor, the threshold voltage may be set higher than this. For example, the value may reach several tens of volts to several hundred volts.

In the case of a depletion mode transistor, the threshold voltage may be set to 0.1 V or less for an n-channel transistor and -0.1 V or more for a p-channel transistor. To form a depletion mode transistor, a donor is introduced into a channel formation region in the case of an n-channel transistor, and an acceptor is introduced into a channel formation region in the case of a p-channel transistor. The concentration may be in the range of 2 × 10 ¹⁷ cm ⁻³ to 5 × 10 ¹⁸ cm ⁻³ .

[0084]

As described above, according to the present invention, a buried insulating layer formed on a substrate, a semiconductor layer formed in contact with the buried insulating layer, and a gate insulating film formed on the semiconductor layer are provided. And a source and drain region formed from the surface of the semiconductor layer so as to sandwich the gate electrode except for a region below the gate electrode. A part or all of the region was formed as a low dielectric constant layer having a lower dielectric constant than silicon oxide. Further, according to the present invention, a semiconductor layer disposed at a predetermined interval on a substrate, a side wall formed on a side portion of the semiconductor layer and supporting the semiconductor layer at an interval on the substrate, and a gate on the semiconductor layer A semiconductor device is provided with a gate electrode formed via an insulating film, and source and drain regions formed from the surface of the semiconductor layer so as to sandwich the gate electrode except for a region below the gate electrode. Therefore, the electric field from the lower part of the drain region to the lower part of the gate electrode is reduced, so that the short channel effect can be suppressed. Further, the parasitic capacitance between the channel and the substrate can be reduced. In the present invention, the low dielectric constant region is extended to below the source / drain region. Thereby, the parasitic capacitance between the source / drain region and the substrate can be reduced. As a result, it is possible to suppress deterioration of the characteristics of the field-effect transistor formed in the semiconductor layer (SOI) on the buried insulating layer and to improve the characteristics at the same time.

Further, according to the present invention, first, a buried insulating layer substrate having a semiconductor film formed on a supporting substrate via a buried insulating layer is prepared, and the semiconductor film is selectively removed by etching to obtain an element. A semiconductor layer to be formed is formed.
Next, a buried insulating layer below the periphery of the semiconductor layer is selectively removed so as to leave a region below the semiconductor layer, and a sacrificial layer is formed below the semiconductor layer. Next, sidewalls made of a material different from that of the sacrifice layer are formed on the side surfaces of the semiconductor layer and the sacrifice layer. Next, an opening is formed in a part of the side wall to expose the side surface of the sacrificial layer. Next, the sacrifice layer is removed through the opening by etching for selectively removing the sacrifice layer from the support substrate, the semiconductor layer, and the side wall, and a cavity is formed below the center of the semiconductor layer. Next, a gate electrode is formed over the semiconductor layer with a gate insulating film interposed therebetween. Then, source / drain regions are formed in the semiconductor layers on both sides of the gate electrode.

In the present invention, first, a buried insulating layer substrate having a semiconductor film formed on a supporting substrate with a buried insulating layer interposed therebetween is prepared, and the semiconductor film is selectively removed by etching. A semiconductor layer to be formed is formed.
Next, a buried insulating layer below the periphery of the semiconductor layer is selectively removed so as to leave a region below the semiconductor layer, and a sacrificial layer is formed below the semiconductor layer. Next, sidewalls made of a material different from that of the sacrifice layer are formed on the side surfaces of the semiconductor layer and the sacrifice layer. Next, a gate electrode is formed over the semiconductor layer with a gate insulating film interposed therebetween. Next, source / drain regions are formed in the semiconductor layers on both sides of the gate electrode. Next, an opening is formed in a part of the side wall to expose the side surface of the sacrificial layer. Then, the sacrifice layer is removed through the opening by etching for selectively removing the sacrifice layer from the support substrate, the semiconductor layer, and the side wall, so that a cavity is formed below the center of the semiconductor layer.

In the present invention, first, a buried insulating layer substrate in which a semiconductor film is formed on a supporting substrate via a buried insulating layer is prepared, and the semiconductor film is selectively removed by etching to obtain an element. A semiconductor layer to be formed is formed.
Next, a buried insulating layer below the periphery of the semiconductor layer is selectively removed so as to leave a region below the semiconductor layer, and a sacrificial layer is formed below the semiconductor layer. Next, sidewalls made of a material different from that of the sacrifice layer are formed on the side surfaces of the semiconductor layer and the sacrifice layer. Next, an opening is formed in a part of the semiconductor layer to expose the side surface of the sacrificial layer. Next, the sacrifice layer is removed through the opening by etching for selectively removing the sacrifice layer from the support substrate, the semiconductor layer, and the side wall, and a cavity is formed below the center of the semiconductor layer. Next, a gate electrode is formed over the semiconductor layer with a gate insulating film interposed therebetween. Then, source / drain regions are formed in the semiconductor layers on both sides of the gate electrode.

In the present invention, first, a buried insulating layer substrate in which a semiconductor film is formed on a supporting substrate via a buried insulating layer is prepared, and the semiconductor film is selectively removed by etching to form an element. A semiconductor layer to be formed. Next, a buried insulating layer below the periphery of the semiconductor layer is selectively removed so as to leave a region below the semiconductor layer, and a sacrificial layer is formed below the semiconductor layer. Next, sidewalls made of a material different from that of the sacrifice layer are formed on the side surfaces of the semiconductor layer and the sacrifice layer. Next, a gate electrode is formed over the semiconductor layer with a gate insulating film interposed therebetween. Next, source / drain regions are formed in the semiconductor layers on both sides of the gate electrode. Next, an opening is formed in a part of the semiconductor layer to expose the side surface of the sacrificial layer. Then, the sacrifice layer is removed through the opening by etching for selectively removing the sacrifice layer from the support substrate, the semiconductor layer, and the side wall, so that a cavity is formed below the center of the semiconductor layer.

As a result, the region under the semiconductor layer sandwiched between the source and drain regions is formed to have a lower dielectric constant than silicon oxide. Since the capacity decreases, the short channel effect can be suppressed. Further, the parasitic capacitance between the source / drain region and the substrate can be reduced. Further, the parasitic capacitance between the channel and the substrate can be reduced. As a result, according to the present invention, the semiconductor layer (SO
The deterioration of the characteristics of the field effect transistor formed in I) can be suppressed.

In the present invention, first, a high etching rate layer is formed on a silicon substrate. Next, a semiconductor layer is formed on the high etching rate layer. Next, a buried insulating layer is formed on the semiconductor layer. Next, a part of the buried insulating layer is etched to form a recess having a reduced thickness. Next, the supporting substrate is bonded to the insulating layer by heating. Next, the silicon substrate is selectively removed from the high etching rate layer. Next, the high etching rate layer is selectively removed from the semiconductor layer to expose the semiconductor layer surface. Next, a gate electrode is formed over the semiconductor layer with a gate insulating film interposed therebetween. Then, source / drain regions were formed in the semiconductor layers on both sides of the gate electrode. At this time, the region of the semiconductor layer sandwiched between the source / drain regions was arranged on the recess. Therefore, since the region under the semiconductor layer sandwiched between the source and drain regions is formed to have a lower dielectric constant than silicon oxide, the effect of the electric field formed from below the drain region to below the gate electrode is reduced. Therefore, the short channel effect can be suppressed. Further, the parasitic capacitance between the channel and the substrate can be reduced. Further, when the low dielectric constant layer is extended to a part below the source / drain region, the parasitic capacitance between the source / drain region and the substrate can be reduced. As a result, according to the present invention, it is possible to suppress the deterioration of the characteristics of the field effect transistor formed in the semiconductor layer (SOI) on the buried insulating layer, and to improve the characteristics.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a field-effect transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a configuration of a field-effect transistor according to another embodiment of the present invention.

FIG. 3 is an explanatory diagram for illustrating the method for manufacturing the field-effect transistor in the first embodiment.

FIG. 4 is an explanatory view following FIG. 3 for illustrating the method for manufacturing the field-effect transistor in the first embodiment.

FIG. 5 is an explanatory diagram for explaining a method of manufacturing another embodiment of the field-effect transistor of the present invention.

FIG. 6 is a cross-sectional view illustrating a partial configuration of a field-effect transistor according to another embodiment of the present invention.

FIG. 7 is an explanatory diagram for describing a method of manufacturing another embodiment of the field-effect transistor of the present invention.

FIG. 8 is an explanatory diagram for describing the method for manufacturing the field-effect transistor according to the second embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating a configuration of a field-effect transistor according to another embodiment of the present invention.

FIG. 10 is an explanatory diagram for describing a method for manufacturing a field-effect transistor according to a third embodiment of the present invention.

FIG. 11 is an explanatory diagram for describing a method for manufacturing a field-effect transistor according to a third embodiment of the present invention.

FIG. 12 is an explanatory diagram illustrating a method for manufacturing a field-effect transistor according to a fourth embodiment of the present invention.

FIG. 13 is an explanatory diagram illustrating a method for manufacturing a field-effect transistor according to a fifth embodiment of the present invention.

FIG. 14 is an explanatory diagram illustrating a method for manufacturing a field-effect transistor according to a sixth embodiment of the present invention.

FIG. 15 is a cross-sectional view showing a configuration of a conventional field-effect transistor having an SOI structure.

FIG. 16 is a cross-sectional view showing another configuration of a conventional field effect transistor having an SOI structure.

FIG. 17 is a cross-sectional view showing another configuration of a conventional field-effect transistor having an SOI structure.

FIG. 18: SiO ₂ deposited above or below the cavity
FIG. 9 is a characteristic diagram showing a change in ΔV _th1 when the film thickness (T _box1 ) of the first embodiment changes.

[Explanation of symbols]

101: silicon substrate, 102: cavity, 103: semiconductor layer, 104: gate insulating film, 105: gate electrode, 10
6: source / drain region, 107: channel formation region, 108: insulator side wall.

Claims (22)

[Claims] A buried insulating layer formed on a substrate; a semiconductor layer formed on and in contact with the buried insulating layer; a gate electrode formed on the semiconductor layer via a gate insulating film; A source and drain region formed on the surface of the semiconductor layer so as to sandwich the region below the gate electrode, and at least a portion of the buried insulating layer below the semiconductor layer sandwiched between the source and drain regions; Is a low-permittivity layer having a lower dielectric constant than silicon oxide. 2. The field effect transistor according to claim 1, wherein said low dielectric constant layer extends to at least a part of a region below said source / drain region. . 3. The field effect transistor according to claim 1, wherein the low dielectric constant layer is formed of a cavity. 4. The field effect transistor according to claim 3, wherein the cavity is formed in contact with a lower surface of the semiconductor layer. 5. The field-effect transistor according to claim 1, wherein the low dielectric constant layer includes an insulating film formed in contact with a lower portion of the semiconductor layer and a cavity formed below the insulating film. A field effect transistor characterized by being constituted. 6. The field effect transistor according to claim 1, wherein said source / drain region is formed in contact with said buried insulating layer. . 7. A semiconductor layer disposed at a predetermined interval on a substrate, a side wall formed on a side of the semiconductor layer and supporting the semiconductor layer on the substrate at the interval, and the semiconductor layer. A gate electrode formed thereon with a gate insulating film interposed therebetween, and source and drain regions formed from the surface of the semiconductor layer so as to sandwich the region except for a region below the gate electrode. Field effect transistor. 8. The field effect transistor according to claim 7, wherein an insulating film having a thickness of 33 nm or less is formed below the semiconductor layer. 9. The field effect transistor according to claim 7, wherein an insulating film having a thickness of not more than twice the thickness of said gate insulating film is formed under said semiconductor layer. Type transistor. 10. A first step of preparing a buried insulating layer substrate having a semiconductor film formed on a supporting substrate via a buried insulating layer, and selectively etching and removing the semiconductor film to obtain an element. A second step of forming a semiconductor layer to be formed; and a step of selectively removing a buried insulating layer around the semiconductor layer so as to leave a region below the semiconductor layer, and forming a sacrificial layer below the semiconductor layer. A third step of forming a side wall made of a material different from that of the sacrificial layer on the side surfaces of the semiconductor layer and the sacrificial layer; and forming an opening in the side wall or a part of the semiconductor layer. Removing the sacrificial layer through the opening by performing a fifth step of exposing the sacrificial layer by etching and selectively removing the sacrificial layer from the support substrate, the semiconductor layer, and the side wall. Under the semiconductor layer Without even a method of manufacturing a field effect transistor and a sixth step, characterized in that it comprises at least to form the cavity in a part of the region. 11. A first step of preparing a buried insulating layer substrate having a semiconductor film formed on a supporting substrate via a buried insulating layer, and forming an element by selectively etching away the semiconductor film. Forming a semiconductor layer to be formed, and selectively removing a buried insulating layer below the periphery of the semiconductor layer so as to leave a region below the semiconductor layer, forming a sacrificial layer below the semiconductor layer. A fourth step of forming a side wall made of a material different from that of the sacrifice layer on the side surfaces of the semiconductor layer and the sacrifice layer; and forming an opening in a part of the side wall, Removing the sacrificial layer through the opening by performing a fifth step of exposing a side surface of the sacrificial layer, and etching to selectively remove the sacrificial layer from the support substrate, the semiconductor layer, and the side wall At least below the semiconductor layer A sixth step of forming a cavity in the region of the portion, forming a gate electrode on the semiconductor layer via a gate insulating film, and forming a source / drain region in the semiconductor layer at a position where the gate electrode is not provided. A method of manufacturing a field-effect transistor, comprising at least a seventh step of forming 12. A first step of preparing a buried insulating layer substrate having a semiconductor film formed on a supporting substrate with a buried insulating layer interposed therebetween, and forming an element by selectively etching away the semiconductor film. Forming a semiconductor layer to be formed, and selectively removing a buried insulating layer below the periphery of the semiconductor layer so as to leave a region below the semiconductor layer, forming a sacrificial layer below the semiconductor layer. A third step of forming side walls made of a material different from that of the sacrifice layer on the side surfaces of the semiconductor layer and the sacrifice layer; and a gate electrode on the semiconductor layer via a gate insulating film. A fifth step including forming a source / drain region in the semiconductor layer at a position where the gate electrode is not provided; and a part of the side wall performed following these steps. Form an opening in Removing the sacrificial layer through the opening by performing a sixth step of exposing the sacrificial layer side surface by etching, and etching for selectively removing the sacrificial layer with respect to the support substrate, the semiconductor layer, and the side wall. Forming a cavity below a central portion of the semiconductor layer. 13. A first step of preparing a buried insulating layer substrate having a semiconductor film formed on a supporting substrate with a buried insulating layer interposed therebetween, and forming an element by selectively etching away the semiconductor film. Forming a semiconductor layer to be formed, and selectively removing a buried insulating layer below the periphery of the semiconductor layer so as to leave a region below the semiconductor layer, and forming a sacrificial layer below the semiconductor layer. A third step of forming side walls made of a material different from the material of the sacrifice layer on the side surfaces of the semiconductor layer and the sacrifice layer; and forming an opening in a part of the semiconductor layer. Removing the sacrificial layer through the opening by performing a fifth step of exposing the sacrificial layer side surface, and etching for selectively removing the sacrificial layer with respect to the support substrate, the semiconductor layer, and the side wall. A cavity below the semiconductor layer A sixth step of forming; forming a gate electrode on the semiconductor layer via a gate insulating film; and forming a source / drain region in the semiconductor layer at a position where the gate electrode is not provided. And a method for manufacturing a field-effect transistor. 14. A first step of preparing a buried insulating layer substrate having a semiconductor film formed on a supporting substrate with a buried insulating layer interposed therebetween, and forming an element by selectively etching away the semiconductor film. Forming a semiconductor layer to be formed, and selectively removing a buried insulating layer below the periphery of the semiconductor layer so as to leave a region below the semiconductor layer, and forming a sacrificial layer below the semiconductor layer. A third step of forming side walls made of a material different from the material of the sacrifice layer on the side surfaces of the semiconductor layer and the sacrifice layer; and a gate electrode on the semiconductor layer via a gate insulating film. A fifth step of forming source / drain regions in the semiconductor layer at positions where the gate electrode is not provided, and an opening in a part of the semiconductor layer, which is performed following these steps. Before forming part Removing the sacrificial layer through the opening by performing a sixth step of exposing the side surface of the sacrificial layer, and etching to selectively remove the sacrificial layer with respect to the supporting substrate, the semiconductor layer, and the side wall; And a seventh step of forming a cavity below the semiconductor layer. 15. The method for manufacturing a field-effect transistor according to claim 10, wherein the cavity is formed such that at least a lower portion of a region of the semiconductor layer sandwiched between the source / drain regions is exposed. A method for manufacturing a field effect transistor, comprising: 16. The method for manufacturing a field effect transistor according to claim 15, wherein after forming the cavity, a thickness of the gate insulating film is reduced in a region exposed in the cavity on a lower surface of the semiconductor layer. A method for manufacturing a field-effect transistor, comprising forming an insulating film having a thickness of twice or less. 17. The method for manufacturing a field-effect transistor according to claim 16, wherein the insulating film is formed by thermal oxidation. 18. The method according to claim 10, wherein the gate electrode is formed after a field oxide film is formed on the support substrate around the semiconductor layer. A method for manufacturing a field effect transistor, comprising: 19. A first step of forming a high etching rate layer on a silicon substrate, and a second step of forming a semiconductor layer on the high etching rate layer
A third step of forming a buried insulating layer on the semiconductor layer; a fourth step of etching a part of the buried insulating layer to form a recess having a reduced thickness; Fifth bonding of the supporting substrate to the insulating layer by heating
A sixth step of removing the silicon substrate; a seventh step of selectively removing the high etching rate layer with respect to the semiconductor layer to expose the surface of the semiconductor layer; Forming at least an eighth step including forming a gate electrode thereon with a gate insulating film interposed therebetween and forming source / drain regions in the semiconductor layer on both sides of the gate electrode; A region of the semiconductor layer sandwiched between the semiconductor layers is disposed on the recess. 20. The method for manufacturing a field-effect transistor according to claim 19, wherein the cavity is formed so that the semiconductor layer is exposed. 21. A first step of forming a high etching rate layer on a silicon substrate, and a second step of forming a semiconductor layer on the high etching rate layer
A third step of forming a buried insulating layer on a support substrate; a fourth step of etching a part of the buried insulating layer to form a recess having a reduced thickness; A fifth step of adhering the semiconductor layer to the upper buried insulating layer by heating, a sixth step of removing the silicon substrate, and selectively applying the high etching rate layer to the semiconductor layer. A seventh step of exposing the semiconductor layer surface by removing, forming a gate electrode on the semiconductor layer via a gate insulating film, and forming a source / drain region in the semiconductor layer on both sides of the gate electrode. An eighth step including forming the semiconductor layer, wherein a region of the semiconductor layer sandwiched between the source / drain regions is disposed on the concave portion. Manufacturing method. 22. The method for manufacturing a field-effect transistor according to claim 21, wherein the cavity is formed such that the support substrate is exposed.