JP4058751B2 - Method for manufacturing field effect transistor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a field effect transistor and a manufacturing method thereof.
[0002]
[Prior art]
In a field effect transistor formed on an insulating layer provided on a substrate such as a silicon wafer, a field effect transistor having a structure in which a main channel is formed in a plane substantially perpendicular to the upper surface of the substrate is Japanese Patent Laid-Open No. 64-8670 (FIG. 4), Japanese Laid-Open Patent Publication No. 64-27270 (FIG. 2), Hisamoto to Japanese Patent Laid-Open No. 2-263473 (FIG. 1), Yagishita JP-A-10-93093 discloses each. The field effect transistor having the structure disclosed in the above publication will be described with reference to FIG. FIG. 50 corresponds to FIG. 4 of Japanese Patent Laid-Open No. 64-8670.
[0003]
As illustrated in FIG. 50, an insulator 102 is provided over a semiconductor substrate 101, and a rectangular semiconductor layer 103 is provided over the insulator 102. A gate insulating film 104 is provided on the surface of the semiconductor layer 103, and a gate electrode 105 is provided across the semiconductor layer 103 on which the gate insulating film 104 is formed. Here, the surface of the semiconductor layer 103 refers to the upper surface and side surfaces of the semiconductor layer 103.
[0004]
The semiconductor layers 103 on both sides of the gate electrode 105 constitute source / drain regions into which high-concentration impurities are introduced. In the example shown in FIG. 50, portions of the rectangular semiconductor layer 103 located on the near side and the far side with respect to the gate electrode 105 constitute source / drain regions containing high-concentration impurities. By applying an appropriate gate voltage to the gate electrode 105, a main channel is formed on the side surface of the rectangular parallelepiped semiconductor layer 103. Even if a channel is formed on the upper surface of the semiconductor layer 103, the channel width is narrow, so that it is not dominant in carrier conduction. The height of the normal semiconductor layer 103 (a in FIG. 50) is larger than the width of the rectangular parallelepiped (b in FIG. 50) in the plane perpendicular to the direction in which the channel current flows. In FIG. 50, the width of the semiconductor layer 103 (b in FIG. 50) is made smaller than the total width of depletion layers formed from the channels on both sides toward the inside of the semiconductor layer 103, so that the operation characteristics are excellent. A fully depleted MOSFET is obtained.
[0005]
In general, a fully depleted MOSFET having gates on both sides of a semiconductor layer in which a channel is formed is characterized by excellent suppression of the short channel effect.
In the manufacturing method for manufacturing the field effect transistor of the conventional example shown in FIG. 50, first, a structure in which the rectangular semiconductor layer 103 is disposed on the insulator 102 is formed by some method, and then the surface of the semiconductor layer 103 is formed. Is subjected to thermal oxidation to provide a gate insulating film 104, and subsequently a gate electrode material is deposited and then processed by etching to form a gate electrode 105, whereby the field effect of the conventional example shown in FIG. Type transistor is obtained.
[0006]
[Problems to be solved by the invention]
However, in the manufacturing method for manufacturing the conventional vertical field effect transistor shown in FIG. 50, there is a problem that it is difficult to form a gate sidewall (gate sidewall).
[0007]
In a normal MOSFET that is not a vertical type, an insulating film side wall (hereinafter referred to as a gate side wall) is provided on the side surface of the gate before forming the source / drain. Here, the gate sidewall is processed in the source / drain region, for example, introduction of impurities into the source / drain region, silicidation of the source / drain region, epitaxial growth of the semiconductor into the source / drain, selection The purpose is to protect the gate electrode and the channel region in a process such as growth.
[0008]
When forming a gate sidewall in a normal non-vertical MOSFET, after forming a gate electrode on a plane where a channel is formed, an insulating film is deposited on the entire surface with a certain thickness, and the deposited insulation is formed. The film is anisotropically etched by RIE (reactive ion etching) or the like, and the insulating film is removed except for the side surface of the gate electrode. Gate sidewalls).
[0009]
When the gate sidewall is provided, the side surface of the gate electrode is protected by the gate sidewall (insulating film), while the semiconductor surface is exposed at a position where neither the gate electrode nor the gate sidewall is provided. Is obtained.
[0010]
In such a process, after depositing a film on an uneven structure and then subjecting the deposited film to anisotropic etching under appropriate conditions, the deposition is performed only on the side surface of the protrusion of the uneven structure. This is based on the principle that the formed film can be left, that is, the side wall is formed on the side surface of the projection having the uneven structure.
[0011]
However, if a gate sidewall is provided by the same method as that in the case of a normal non-vertical MOSFET with respect to the vertical transistor structure shown in FIG. 50, in the vertical transistor structure shown in FIG. Side walls are also formed on the side surfaces of the semiconductor layer 103 because of the protruding shape. In this case, a side wall is formed only on the side surface of the gate electrode 5 and the surface of the semiconductor layer 103 (the vertical structure shown in FIG. 50) at a position where neither the gate electrode 5 nor the gate side wall 22 is provided. In the case of a type transistor, a structure in which the side surface of the semiconductor layer 103 is exposed) cannot be obtained.
[0012]
Therefore, in a method for manufacturing a transistor in which the channel surface is substantially perpendicular to the substrate, the semiconductor layer (shown in FIG. 50) has a side wall only on the side surface of the gate and is provided with neither a gate electrode nor a gate side wall. In the case of a vertical transistor, a method for manufacturing a field effect transistor is necessary in which the surface of the semiconductor layer 103 is exposed).
[0013]
  An object of the present invention is to provide a vertical field effect transistor that is optimal as a method for manufacturing a fine vertical field effect transistor constituting an LSI, particularly a double gate vertical field effect transistor having gate electrodes on both sides of a semiconductor layer.Providing manufacturing methodThere is.
[0018]
[Means for Solving the Problems]
  In order to achieve the above object, a method of manufacturing a field effect transistor according to the present invention includes:A dummy gate electrode is provided on a semiconductor region having a protruding shape, the dummy gate electrode is embedded in an insulator, and the upper portion of the insulator covering the dummy gate electrode is removed by etching, and the upper portion of the dummy gate electrode is removed. Etching back the insulator covering the dummy gate electrode using the dummy gate electrode and the first side wall as a mask by providing a first side wall on both sides of the exposed dummy gate electrode. Forming a gate sidewall made of an insulator on a side surface of the dummy gate electrode at a lower portion of the first sidewall;Dummy gate electrodeAnd the portion not covered by any of the gate side walls,Dummy gate electrodeProviding a source / drain region in which a first conductivity type impurity is introduced at a high concentration in the semiconductor regions on both sides ofDummy gate electrodeAnd a step of burying a conductive material in a gap formed by removing the gate electrode to form a gate electrode.
[0019]
The first side wall is polysilicon.
[0020]
The gate sidewall is made of SiO.₂It is.
[0021]
The gate sidewall is Si_ThreeN_FourIt is.
[0022]
Further, the material of the portion of the gate sidewall that is in contact with the gate electrode or the dummy gate electrode is Si._ThreeN_FourAnd Si_ThreeN_FourThe outer layer is made of SiO₂It is.
[0023]
The first sidewall is Si_ThreeN_FourIt is.
[0024]
The first sidewall is Si_ThreeN_FourAnd the gate sidewall is SiO.₂It is.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1) FIG. 1 is a bird's-eye view showing a vertical field effect transistor according to the present invention, and FIG. 2 is a plan view of the vertical field effect transistor according to the present invention shown in FIG. 3 is a cross-sectional view taken along line A1-A1 ′ of FIGS. 1 and 2, FIG. 4 is a cross-sectional view taken along line B1-B1 ′ of FIGS. 1 and 2, and FIG. 5 is a cross-sectional view taken along line C1-C1 ′ of FIGS. It is.
[0037]
As shown in FIG. 1, a buried insulating film 2 is provided on a silicon substrate 1, and a semiconductor layer 3 patterned in an appropriate shape is provided on the insulating film 2. The semiconductor layer 3 is provided with a row of openings 10 so as to cross the semiconductor layer 3 (FIG. 2). In the opening 10, the semiconductor layer 3 is removed, and the opening reaches the buried insulating film 2.
[0038]
As shown in FIG. 2, the gate electrode 5 having a long side in the direction in which the openings 10 are arranged is provided on the semiconductor layer 3 and the buried insulating film 2 exposed in the openings 10 in the opening arrangement region 34. The semiconductor layer 3 (see FIG. 3) located below the gate electrode 5 has a channel formation region 7 in which impurities are not introduced or impurities are introduced at a low concentration and a channel is formed by applying an appropriate gate voltage. Constitute.
[0039]
An insulating film (a gate insulating film 6 on the upper surface and the side surface in the form of FIG. 1) is provided on the upper surface and side surfaces of the semiconductor layer 3 constituting the channel forming region 7 (see FIG. 3), and the semiconductor constituting the channel forming region 7 The layer 3 faces the gate electrode 5 through the insulating film on the upper surface and side surfaces (see FIG. 4). Here, the insulating film provided on the side surface of the semiconductor layer 3 constituting at least the channel formation region 7 is the gate insulating film 6, and the film thickness is increased to the extent that a channel is formed on the side surface of the semiconductor layer 3 by application of the gate voltage. Set thin.
[0040]
The insulating film on the upper surface of the semiconductor layer 3 constituting the channel forming region 7 may be a gate insulating film as thin as the side insulating film (gate insulating film 6), or may be provided thicker than the side insulating film. good. The insulating film on the upper surface of the semiconductor layer 3 and the material of the insulating film on the side surface may be different.
[0041]
As shown in FIG. 2, portions of the semiconductor layer 3 located on both sides of the region 34 where the openings 10 are arranged constitute a source / drain region 4 doped with a high-concentration impurity. In a region between the source / drain region 4 and the channel forming region 7, an impurity having the same conductivity type as that of the source / drain 4 is introduced at a high concentration, and the source / drain connecting the source / drain region 4 and the channel forming region 7 is connected. The connection part 32 will be comprised (refer FIG. 2).
[0042]
The source / drain region 4 of this embodiment has a role of connecting wirings via the source / drain contact 16 (FIGS. 35 to 37). The source / drain connection portion 32 connects the source / drain region 4 and the channel formation region 7, and the thickness of the portion where the high impurity concentration portion and the channel formation region are connected (the semiconductor layer 3 constituting the conduction path). By reducing the width (corresponding to the horizontal width and the junction depth of a normal field effect transistor), the short channel effect (variation in characteristics such as threshold voltage due to transistor miniaturization) is suppressed. Have.
[0043]
Note that the combined portion of the source / drain region 4 and the source / drain connection portion 32 in this transistor corresponds to a portion having the function of the source / drain region in a normal single drain field effect transistor. For a field effect transistor having a source / drain extension that extends shallowly from the source / drain region to the channel formation region, the source / drain connection portion 32 of this embodiment corresponds to the source / drain extension.
[0044]
Although not shown in FIG. 2, various insulators are embedded in the opening 10 not covered by the gate electrode 5 in various insulating film deposition steps until the transistor is completed. However, it is not necessary for the inside of the opening 10 to be filled with an insulator, and a cavity in which the insulator is not embedded may remain in part. In FIG. 2, the gate insulating film 6 is not shown in order to make the drawing easier to see.
[0045]
The dimensions of each part are as follows, for example. The thickness of the buried insulating film 2 is 100 nm, for example. The thickness of the semiconductor layer 3 (corresponding to the height a in FIG. 1) is, for example, 120 nm. The width of the opening 10 in the direction in which the openings 10 are arranged (A1-A1 ′ line direction) is 100 nm, and the width of the openings 10 in the direction perpendicular to the direction in which the openings 10 are arranged (C1-C1 ′ line direction). The width is 300 nm. The width of the semiconductor layer 3 sandwiched between the two openings 10 is 50 nm. At both ends of the opening array region 34, notches having approximately half the size of the opening 10 are provided in the semiconductor layer 3. The gate insulating film has a combination of a material and a thickness suitable for suppressing a short channel effect in a transistor to be formed. The material of the gate insulating film is SiO₂In this case, a typical thickness is 1.5 to 4 nm.
[0046]
However, the thickness of the buried insulating film 2 is not particularly limited. In general, in a SIMOX wafer (an SOI substrate manufactured by ion implantation of oxygen into a silicon substrate), the thickness of the buried insulating layer is about 100 nm to 400 nm, and a bonded wafer (manufactured by bonding two silicon substrates through an insulating film). In the case of SOI wafers), the thickness of the buried insulating layer is generally about 1 to 3 μm, but it is a bonded wafer using ELTRAN technology (a technology for separating a thin film silicon layer by forming porous silicon). Then, the buried insulating layer has a thickness of about 50 nm. In general, in a logic circuit, the thickness of the buried insulating layer is preferably set to 150 nm or less so that heat can easily escape through the buried insulating layer, but the effect of the present invention is the thickness of the buried insulating layer 2. The thickness is not limited.
[0047]
The width of the semiconductor layer 3 sandwiched between the two openings 10 is preferably about the same as or smaller than the gate length from the viewpoint of suppressing the short channel effect, and is half or less than the gate length. This is particularly desirable from the viewpoint of suppressing the short channel effect. The gate length is not particularly limited, but a typical gate length assumed for the field effect transistor to which the present invention is applied is in the range of 10 nm to 0.25 μm. The relationship between the width and height of the semiconductor layer 3 will be described in detail with reference to FIG.
[0048]
The material of each part is as follows. The buried insulating film 2 may be an insulator, for example, SiO.₂And SiO₂Besides, for example, Si_ThreeN_FourAn insulator made of AlN, alumina, other metal oxides, an insulator made of an organic material, or the like may be used. Alternatively, the buried insulating film 2 may be replaced with a cavity to form a transistor having a buried insulating layer made of a cavity.
[0049]
In order to enjoy the effects of the present invention, the material of the semiconductor layer 3 is not particularly limited, but single crystal silicon is most desirable from the viewpoint of compatibility with a normal LSI process. The material of the gate electrode 5 may be a conductor having a necessary work function and conductivity. For example, n⁺Type or p⁺Type polysilicon, n⁺Type or p⁺Type polycrystalline SiGe mixed crystal, n⁺Type or p⁺Type polycrystalline Ge, n⁺Type or p⁺Examples thereof include semiconductors such as type polycrystalline SiC, metals such as Mo, W, and Ta, metal nitrides such as TiN and WN, and silicide compounds such as platinum silicide and erbium silicide.
[0050]
In the figure, the gate length (the dimension of the gate electrode 5 in the direction connecting two source / drain regions formed later. In FIGS. 1, 2, and 4, the dimensions in the B1-B1 ′ direction and the C1-C1 ′ direction are shown. (Corresponding) is set so as not to fill the opening 10 and is set to, for example, 150 nm. However, the gate electrode 5 may completely cover the opening 10 as long as the source / drain regions are provided so as to reach both ends of the opening 10. Low-concentration impurities may be introduced into the semiconductor layer 3 constituting the channel formation region 7, or impurities may not be introduced at all. Impurities are, for example, boron, phosphorus and arsenic, and the concentration is 10¹⁹cm^-3Is less than. In order to obtain a fully depleted operation with excellent device characteristics, the concentration is 10¹⁸cm^-3It is desirable to be less than.
[0051]
As a material of the gate electrode 5, a material whose work function is suitable for controlling the threshold value (metal such as Mo, W, Ta, metal nitride such as TiN, WN, platinum silicide, erbium silicide, SiGe mixed crystal etc.), introduction of impurities is not necessary, and even if introduced, 10¹⁸cm^-3Less than good. Further, if the impurity concentration is set to a low concentration so that the depletion layers extending from the channels on both side surfaces toward the center of the semiconductor layer 3 are in contact with each other in a state where the threshold voltage is applied to at least the gate electrode 5, the operating characteristics are obtained. It is possible to enjoy the effect of suppressing the short channel effect brought about by the double gate structure.
[0052]
Impurities having the same conductivity type as the channel conductivity type are introduced into the source / drain region 4 at a high concentration. In the case of an n-channel transistor, an n-type impurity such as phosphorus or arsenic is introduced, and in the case of a p-channel transistor, a p-type impurity such as boron is introduced. The concentration of the impurity introduced into the source / drain region 4 is 10¹⁹cm^-3Above, typically 5 × 10¹⁹cm^-3~ 5x10²⁰cm^-3It is.
[0053]
Since the potential of the channel formation region 7 of this transistor is controlled by the gate electrodes 5 provided on both side surfaces of the semiconductor layer 3 constituting the channel formation region 7, the controllability to the potential of the channel formation region 7 is high and short. The channel effect is suppressed and the characteristics of the device are improved.
[0054]
Further, the electric field from the gate electrode 5 arranged on both side surfaces of the semiconductor layer 3 causes the semiconductor layer to be larger than the total width of the two depletion layers formed from both side surfaces of the semiconductor layer 3 toward the inside of the semiconductor layer 3. 3 width (W in FIG._Three) Is reduced, the device can be operated in a fully depleted manner, so that the subthreshold characteristic (the degree to which the transistor sharply turns off when a gate voltage lower than the threshold voltage is applied) is improved, and the substrate floating effect (Abnormal operation due to accumulation of surplus carriers in the semiconductor layer) is suppressed.
[0055]
When the insulating film on the upper surface of the semiconductor layer 3 constituting the channel formation region 7 is thin and a channel is formed on the upper surface of the semiconductor layer 3, the height of the semiconductor layer 3 (h in FIG. 3)_Three) And the width of the semiconductor layer 3 (W in FIG. 3)_Three) Are the same, the sum of the channel widths on both sides (vertical direction in FIG. 3) is twice the width of the channel formed on the upper surface of the semiconductor layer 3 (horizontal direction in FIG. 3). Height h of semiconductor layer 3_ThreeIs the width W of the semiconductor layer 3_ThreeIf it is larger, the sum of the channel widths on both sides (vertical direction in FIG. 3) is more than twice the width of the channel formed on the upper surface of the semiconductor layer 3 (lateral direction in FIG. 3). Can be the dominant channel.
[0056]
Therefore, the height h of the semiconductor layer 3 constituting the channel forming region 7_ThreeAnd the width W of the semiconductor layer 3_ThreeOr the height h of the semiconductor layer 3_ThreeIs the width W of the semiconductor layer 3_ThreeIt is desirable to make it larger.
[0057]
Equivalent film thickness (equivalent film thickness is obtained by dividing the thickness of the insulating film by the relative dielectric constant of the insulating film) rather than the gate insulating film 6 formed on the side surface of the semiconductor layer 3 constituting the channel forming region 7. Quotient SiO₂Is multiplied by the relative dielectric constant. ) Is provided on the upper surface of the semiconductor layer 3 constituting the channel formation region 7, and when the carrier constituting the channel is not induced on the upper surface, the channel forms the semiconductor layer 3 constituting the channel formation region 7. It is formed only on both sides. In this case, the channel width per one conduction path (35) is twice the height of the semiconductor layer 3 constituting the channel formation region 7.
[0058]
Here, an appropriate height h of the semiconductor layer 3 constituting the channel formation region 7_ThreeWill be described with reference to FIG. Consider one period separated by an alternate long and short dash line in a cross section in which the channel forming region 7 and the opening 10 are periodically arranged.
[0059]
If the channel width on one side surface is W, the total channel width is 2 W in a structure having one cycle.
[0060]
On the other hand, the lateral width of the semiconductor layer 3 constituting the channel formation region 7 in FIG._si(W in FIG._ThreeThe width of the opening 10 separating the channel formation region 7 is W_spThen, the width of one cycle is W_si+ W_spIt becomes. The channel width obtained when a normal transistor (for example, the structure of FIG. 52) is formed in the same region is W_si+ W_spTherefore, in order to realize a channel width larger than that of a normal transistor in the transistor of the present invention, 2W> W_si+ W_spIt is sufficient to satisfy the condition. Divide both sides by 2 to get W> (W_si+ W_sp) / 2.
[0061]
That is, W is W_siAnd W_spLarger than the average of. Channel width W on one side surface and height h of channel formation region 7_SiAre considered to be the same, the height h of the semiconductor layer 3 constituting the channel formation region 7_Si(H_Three) Is the width W of the semiconductor layer 3 constituting the channel formation region 7._siAnd opening 10 width W_spIt can be said that it should be larger than the average of. Here, as a typical example, the width W of the semiconductor layer 3 constituting the channel formation region 7 is used._siAnd opening 10 width W_spAre the same, the average of both is W_siSince the height h of the semiconductor layer 3 constituting the channel forming region 7 is equal to_SiIs the width W of the channel formation region 7_siYou can conclude that it is better to be larger. W_siAnd W_spAre not necessarily equal, but W_si= W_spObtained by assuming h_Si> W_siIf the above condition is adopted as a guideline for designing a transistor, the above condition W> (W_si+ W_sp) / 2, at least a transistor that does not deviate significantly is obtained.
[0062]
As another typical structure, when the width of the semiconductor layer 3 constituting the channel formation region 7 is made smaller than the width of the opening 10, W_si<W_spSo h_Three> W_spIf the above condition is satisfied, the above condition W> (W_si+ W_sp) / 2 must be satisfied.
[0063]
In addition, although this field effect transistor is a transistor having a channel formed on the side surface of the semiconductor layer 3 substantially perpendicular to the substrate plane as a main conduction path, the shape of the source / drain and the gate electrode 5 The shape (FIG. 2) when projected onto the substrate surface is the same as that of a normal field effect transistor (FIG. 52).
[0064]
Further, the shape of the element region 15 is the same as that of a normal field effect transistor except for the arrangement of the openings 10 crossing the central portion. That is, the channel formation region 7 and the source / drain connection 32 have a vertical structure, but the shape of the source / drain region is the same as that of a normal field effect transistor except for the periphery of the opening 10.
[0065]
Therefore, the contact 16 for the source / drain region and the contact 17 for the gate electrode 5 can also be manufactured by the same pattern (FIG. 35) and the same process as those of the normal field effect transistor (FIG. 52).
[0066]
The source / drain region is the same as that of a normal field effect transistor except for the periphery of the opening 10, so that the source / drain region is formed for the formation of the source / drain region, silicidation, or low resistance. In the process of epitaxially growing and selectively growing the semiconductor layer 3 on the top, the same process as that for a conventional field effect transistor or the same process as that for a conventional SOI field effect transistor can be used.
[0067]
Accordingly, except for the addition of the arrangement structure of the openings 10, almost the same pattern as that of a normal transistor can be used, and the formation of the openings 10 and the processing of the periphery of the openings 10 (for example, the gate electrode 5). In the process except for the processing of (for example, contact formation to the gate and the source / drain), the same process as that for the conventional field effect transistor can be used.
[0068]
The channel portion has a structure in which vertical transistors having a certain height (typically 200 nm or less, preferably 120 nm or less, more preferably 60 nm or less) are connected in parallel, and the channel width is set to each conduction path. Therefore, the height of the channel formation region 7 is kept constant even in a transistor having a large channel width.
[0069]
In addition, when transistors having different channel widths are mixed in the circuit, it is only necessary to change the number of conductive paths to be arranged. Therefore, there is no need to change the height of the transistor, and there is no variation in the height of the transistor.
[0070]
In addition, since the height of the transistor can be kept below a certain value, even when impurities are introduced from the upper surface of the semiconductor layer 3 by an impurity introduction means such as ion implantation, the semiconductor layer 3 is vertically oriented perpendicular to the substrate plane. Good uniformity of impurity concentration. Further, the uniformity of the gate dimension (particularly, the length in the direction connecting two sources / drains, that is, the gate length) with respect to the vertical direction of the semiconductor layer 3 is good. Also, the thickness in the substrate plane direction of the semiconductor layer 3 is good in the vertical direction.
[0071]
The uniformity of the impurity concentration in the vertical direction perpendicular to the substrate plane of the semiconductor layer 3, the gate dimension, and the thickness of the semiconductor layer 3 in the substrate plane direction described here is improved as the semiconductor layer 3 is thinner (channel). Height h of the semiconductor layer 3 in the portion_siIs preferably 120 nm or less, more preferably 60 nm or less).
[0072]
In addition, this field effect transistor is provided with gate electrodes 5 on both side surfaces of the semiconductor layer 3 constituting the channel formation region 7 to form a structure called a double gate structure. This is a structure in which two gate electrodes 5 are provided with a semiconductor layer 3 of a thin film (typically 50 nm or less) sandwiched between them. For example, Sekikawa, Solid State Electronics, Vol. 27, page 827, 1984 (T. Sekikawa, Solid- State Electronics, vol. 27, p. 827, 1984), Tanaka, 1991, IMD, Technical Digest, pages 683-686 (T. Tanaka, 1991 IEEE, IEDM, pp. 683-686). Each is disclosed. Sekikawa and Tanaka have reported that the short channel effect is suppressed by adopting a structure in which gate electrodes are formed above and below a semiconductor layer parallel to the substrate plane.
[0073]
However, in the structure disclosed in the above-mentioned publication, in which the gate electrodes are provided above and below the semiconductor layer, there is a problem that the upper and lower gate electrodes cannot be formed simultaneously. For this reason, the position of the upper and lower gates cannot be determined in a self-aligned manner, and the position of the upper and lower gates is shifted, or the size of the upper and lower gates (particularly the gate length, that is, the dimension of the gate in the direction connecting the source and drain) There is a problem that can not be aligned.
[0074]
On the other hand, the structure of the present embodiment realizes a double gate structure by providing the gate electrodes 5 on both side surfaces of the semiconductor layer 3 and can suppress the short channel effect and simultaneously form the gate electrodes 5 on both side surfaces. It is easy (see, for example, Embodiment 3 to be described later), and the positional deviation of the gates on both sides and the difference in dimensions can be greatly reduced as compared with the conventional technique.
[0075]
Next, a modification of the vertical field effect transistor of the present invention shown in FIG. 1 will be described.
[0076]
FIG. 6 is a plan view showing an example in which the opening 10 provided in the semiconductor layer 3 is circular. FIG. 7 shows a structure in which notches are not provided in the semiconductor layer 3 at both ends of the opening array region 34. 6 and 7, the outline of the opening 10 that is originally hidden under the gate electrode 5 is also shown in order to facilitate understanding of the positional relationship between the gate electrode 5 and the opening 10.
[0077]
As shown in FIG. 8, when the opening 10 is provided in the semiconductor layer 3, the buried insulating layer 2 is dug down to a certain depth in the opening 10, and the gate electrode 5 is formed to a position slightly below the lower end of the semiconductor layer 3. The lower end is reached.
[0078]
When the lower end of the gate electrode 5 and the lower end of the semiconductor layer 3 are aligned, or when the lower end of the gate electrode 5 is located above the lower end of the semiconductor layer 3, the lower end of the semiconductor layer 3 or the semiconductor layer 3 It is relatively difficult to sufficiently control the potential of the lower corners (which correspond to the end of the element region and the end of the element region in a normal field effect transistor) by the gate electrode 5, and the potential between the source and the drain is relatively difficult. Leakage current is easy to flow.
[0079]
On the other hand, as shown in FIG. 8, in the present invention, when the lower end of the gate electrode 5 reaches a position slightly below the lower end of the semiconductor layer 3, it becomes easy to suppress the leakage current in the vicinity of the lower end of the semiconductor layer 3. .
[0080]
In addition, as shown in FIG. 26, the buried insulating layer 2 may be subjected to taper etching to form a shape in which the side surface of the buried insulating layer 2 is inclined at a position below the lower end of the semiconductor layer 3.
[0081]
In FIG. 26, since the lower end of the gate electrode 5 is lower than the lower end of the semiconductor layer 3, the controllability of the gate electrode 5 with respect to the potential of the lower end of the semiconductor layer 3 can be improved.
[0082]
8 and 26 show the case where the gate insulating film 6 having the same film thickness is provided on both the side surface and the upper surface of the semiconductor layer 3 constituting the channel formation region 7. This may be applied to the case where the insulating film materials are different from each other, or when the insulating film on the upper surface of the semiconductor layer 3 is thicker than the insulating film on the side surface.
[0083]
Here, the case where the silicon substrate 1 as the supporting substrate is present under the insulator (embedded insulating layer 2) under the semiconductor layer 3 has been described, but the present invention relates to the semiconductor layer 3 forming the field effect transistor. Applicable if there is any insulator below. For example, the present invention can be applied to a structure in which the insulator itself under the semiconductor layer 3 serves as a support substrate, such as an SOS structure (silicon on sapphire) in which the semiconductor layer 3 is provided on the sapphire substrate.
[0084]
The material of the support substrate may not be silicon, and may be an insulator such as quartz or AlN. This structure can be formed, for example, by transferring single crystal silicon to be the semiconductor layer 3 onto an insulator such as quartz or AlN by a general bonding process and thinning process used for manufacturing an SOI substrate.
[0085]
Even in the case where one of the source / drain regions is exclusively used as a source and the other is exclusively used as a drain, such as an inverter, a NAND gate, a NOR gate, etc. in a CMOS structure, the present specification includes both. It is expressed as source / drain.
[0086]
(Embodiment 2) Next, another vertical field effect transistor of the present invention will be described.
[0087]
With respect to the three arrangement of the channel formation region 7, the opening 10 provided in the semiconductor layer 3, and the source / drain region 4, several modifications to the transistor of Embodiment 1 will be described.
[0088]
27 to 34 are plan views of the field-effect transistor viewed from the same position as in FIGS. 2, 6, and 7, and particularly the left end is enlarged.
[0089]
  As shown in FIGS.In any vertical field effect transistor,The openings 10 are arranged so as to cross the semiconductor layer 3, and the gate electrode 5 is provided across the semiconductor layer 3 along the direction in which the openings 10 are arranged. The semiconductor layer 3 is provided with a source / drain region 4 into which a high concentration conductive impurity is introduced with the gate electrode 5 and the opening 10 interposed therebetween.
[0090]
The semiconductor layer 3 located below the gate electrode 5 constitutes a channel formation region 7 having a low impurity concentration, and the channel is mainly formed on the side surface of the semiconductor layer 3 constituting the channel formation region 7.
[0091]
27 to 34 also show the outline of the opening 10 that is originally hidden under the gate electrode 5 in order to facilitate understanding of the positional relationship between the gate electrode 5 and the opening 10. . Further, the gate insulating film 6 is also omitted for easy understanding of the drawing.
[0092]
27 to 34, the gate insulating film 6 is actually provided on the side surface of the semiconductor layer 3 constituting the channel forming region 7, and the side surface of the semiconductor layer 3 constituting the channel forming region 7 is interposed via the gate insulating film 6. Facing the gate electrode 5.
[0093]
Further, on the upper surface of the semiconductor layer 3 constituting the channel formation region 7, the gate insulating film 6 or an insulating film having a larger equivalent thickness than the gate insulating film 6 (for example, the pad oxide film 8 and Si in FIG._ThreeN_FourThe film 9 is provided).
[0094]
Between the two source / drain regions 4, a conduction path arrangement region 31 in which a plurality of conduction paths 33, which are semiconductor regions connecting the two source / drain regions 4, are provided. The structure of the conduction path arrangement region 31 is the same in the transistor shown in FIGS. 1 to 8 and 35, the transistor described below, and the manufacturing method thereof.
[0095]
A hatched portion in FIG. 27 clearly shows one of the conduction paths 33. The conduction path 33 includes a channel formation region 7 and a source / drain connection portion 32 which is a high impurity concentration region in the conduction path 33. The channel formation region 7 is a region having a low impurity concentration (or no impurity is introduced) located below the gate electrode 5.
[0096]
The source / drain connection portion 32 in the conduction path 33 is located between the channel formation region 7 and the source / drain region 4 and is a region into which impurities of the same conductivity type as the source / drain region 4 are introduced at a high concentration. is there. When a part of the source / drain connection part 32 or a part of the source / drain region 4 is located under the gate electrode 5, the gate electrode 5 and the source / drain connection part 32, respectively, An insulating layer is provided between the source / drain 4. The thickness of this insulating layer may be the same as that of the gate insulating film, or may be thicker than the gate insulating film.
[0097]
Also, the form of the conduction path 33 may be one in which both the channel formation region 7 and the high impurity concentration region (source / drain connection portion 32) in the conduction path 33 are disposed under the gate electrode 5 (FIG. 28).
[0098]
Furthermore, in addition to the channel formation region 7 and the source / drain connection portion 32, a part of the source / drain region 4 may be positioned below the gate electrode 5 (FIG. 28). Further, the source / drain connection portion 32 is not provided in the conduction path 33, and the channel forming region 7 and the source / drain region 4 may be directly connected (FIG. 29).
[0099]
FIGS. 27 to 29 show the case where the projection shape of the opening 10 onto the substrate plane draws a curve at least near the source / drain region 4, but as shown in FIGS. The shape of the part 10 may be a polygon such as a hexagon or an octagon. Further, as shown in FIGS. 46 to 49, it may be a quadrangle that is substantially square and is inclined with respect to the extending direction of the gate electrode 5 (the same as the direction in which the openings 10 are arranged). 33 and 34, the width of the opening 10 may be narrowed within a certain range on the source / drain region 4 side.
[0100]
In any of the embodiments shown in FIGS. 27 to 31, 33, 34, and 46 to 49, the arrangement direction of the openings 10 (perpendicular to the direction connecting the source / drain, Width W of opening 10 in a direction parallel to the substrate surface)_spIs the value (W in FIG. 27) at the center of the opening 10 (position equidistant from the two sources / drains)._sp1) In the vicinity of the source / drain region (for example, W in FIG. 27)._sp2). Conversely, the width W of the semiconductor layer 3 constituting the conduction path 33._siIs the value (W in FIG. 27) at the center of the channel formation region (position equidistant from the two sources / drains)._si1) In the vicinity of the source / drain region 4 (for example, W in FIG. 27)._si2), The maximum at the position connected to the source / drain region 4.
[0101]
That is, the shapes of FIGS. 27 to 31, 33, 34, and 46 to 49 are all the width W of the semiconductor layer 3 from the channel formation region 7 to the source / drain region 4._siIn this case, the lateral width W of the channel formation region 7_siOr at least the width W at the center of the channel formation region 7_siTherefore, as in the case of thinning the semiconductor layer in a normal SOI field effect transistor, it is effective in improving the S factor, suppressing the short channel effect, and improving the characteristics of the transistor.
[0102]
On the other hand, since the width of the semiconductor layer 3 constituting the conduction path 33 is increased at the position in contact with the source / drain region, the parasitic resistance can be reduced.
[0103]
Furthermore, it has a source / drain connection portion 32 (a shape shown in FIGS. 27, 28, 30, 31, 33, 34, and 46 to 49), which is a region containing a high concentration of impurities. If it has, the contact area between the source / drain connection portion 32 and the channel forming region 7 becomes small.
[0104]
When a drain junction which is a high concentration impurity region is formed shallow in a normal field effect transistor, a source / drain extension with a high impurity concentration and a shallow junction is provided, or a semiconductor layer is thinned in an SOI field effect transistor As in the case where the drain which is the high concentration impurity region is formed thin, the short channel effect is suppressed because the cross-sectional area of the high concentration impurity region is reduced at the portion where the high concentration impurity region and the channel formation region are in contact with each other. The characteristics of the transistor are improved.
[0105]
According to the present invention, the effect of suppressing the short channel effect can be obtained by reducing the width of the source / drain connection portion 32 in the arrangement direction of the openings 10 in the portion in contact with the semiconductor layer 3 constituting the channel forming region 7. By increasing the width of the source / drain connection portion 32 in the arrangement direction of the openings 10 in the portion in contact with the source / drain region 4, a parasitic resistance suppressing action can be obtained, and the above-described third problem can be suppressed.
[0106]
The shape of the opening 10 may be a quadrangle as shown in FIG. In this case, W_si, W_spAre both constant. In this case, the structure is simple and the manufacturing is easy. Further, as described below, the parasitic capacitance 36 is small.
[0107]
Next, the parasitic capacitance 36 between the gate side surface and the source / drain side surface will be described with reference to FIGS. FIG. 54 is a plan view showing a case where there is an opening (or a space in which an insulator is embedded in the opening) between the gate end and the source / drain region 4. The form shown in FIG. 54 corresponds to a case where at least a part of the source / drain connection portion 32 is not covered with the gate.
[0108]
  FIG. 55 is a plan view showing a case where there is no opening (or a space in which an insulator is embedded in the opening) between the gate end and the source / drain region 4.FIG.The form shown in FIG. 6 corresponds to the case where the source / drain connection part 32 is entirely covered with the gate.
[0109]
54 and 55, the outline of the opening 10 and the outline of the gate insulating film 6 that are actually hidden under the gate electrode 5 are clearly shown in order to make the drawings easier to see.
[0110]
56 and 57 are cross-sectional views taken along line A205-A205 'in FIG. 54 and cross-sectional views taken along line A206-A206' in FIG.
[0111]
54 and FIG. 56, in the structure having the opening 10 between the gate end and the source / drain region, the side surface of the gate 5 and the side surface of the source / drain region 4 are separated by a distance corresponding to the opening portion 10. The parasitic capacitance 36 between the side surface and the source / drain side surface is small.
[0112]
On the other hand, in the structure having no opening between the gate end and the source / drain region shown in FIGS. 55 and 57, the distance between the gate side surface and the source / drain side surface is small. The parasitic capacitance 36 becomes large, which is disadvantageous for high-speed operation of the element.
[0113]
In the vertical field effect transistor opening 10 according to the present invention, in the process of depositing an insulating film such as a PSG deposition process or an interlayer dielectric film deposition process, SiO 2₂An insulating film such as PSG is embedded, but the inside of the opening 10 is SiO.₂54 and 56, the parasitic capacitance 36 in the structure of FIG. 54 and FIG. 56 can be obtained even when the cavity is completely filled with an insulator such as PSG or when a cavity not filled with the insulator remains in the opening 10. There is no change in being smaller than the parasitic capacitance 36 in the structure of FIG.
[0114]
Therefore, a structure in which at least a part of the source / drain connection portion 32 is not covered with the gate electrode 5 on both the side surface and the upper surface (the structures in FIGS. 27, 30 to 34, and FIGS. 46 to 49). It can be said that it is advantageous in reducing the parasitic capacitance.
[0115]
In the structures of FIGS. 1, 6, 7, and 27 to 34, the channel plane is slightly inclined from the (100) plane (or equivalent plane) or the (100) plane (or equivalent plane). The arrangement direction of the openings 10 is set to the [100] direction (or an equivalent direction) so as to be a plane. In the structure shown in FIGS. 46 to 49 in which one side of the square opening 10 is inclined 45 degrees with respect to the arrangement direction of the openings 10, the arrangement direction of the openings 10 is in the [110] direction (or an equivalent direction). As a result, the channel surface is formed in the (100) plane (or an equivalent direction).
[0116]
When the channel plane is formed on the (100) plane or a plane inclined slightly from the (100) plane, excellent characteristics can be obtained in that the interface state is small and the channel carrier has a high mobility.
[0117]
46 to 49 are diagrams relating to the same transistor, FIG. 46 shows the positional relationship between the opening and the gate electrode, FIG. 47 is a plan view after contact formation with the source / drain and gate, and FIG. 48 is a semiconductor diagram. FIG. 49 is a bird's-eye view of the layer shape, and FIG. 49 is a bird's-eye view after the formation of the gate electrode. In FIG.
[0118]
FIG. 49 shows a case where the mask film 9 and the pad film 8 are removed in the source / drain connection portion 32 (both may not necessarily be removed).
[0119]
The various openings described in the present embodiment and the shapes of the source / drain connection portions can be applied to the various forms described in the first embodiment. In addition, various openings described in this embodiment and the shape of the source / drain connection portion are formed by a transistor having an insulating film having the same thickness as the side surface of the channel formation region above the channel formation region, and above the channel formation region. The present invention can be applied to a transistor having an insulating film thicker than the side surface of the channel formation region and a transistor having a multilayer insulating film above the channel formation region, and the effects of the present invention can be obtained by applying to any of these.
[0120]
(Embodiment 3)
Next, a manufacturing method for manufacturing the vertical field effect transistor shown in Embodiments 1 and 2 according to the present invention will be described in the order of steps.
[0121]
As shown in FIG. 9, a 100 nm thick SiO 2 film is formed on the silicon substrate 1.₂An SOI (silicon-on-insulator) substrate having a buried insulating layer 2 made of a semiconductor layer 3 made of a single crystal silicon layer having a thickness of 120 nm is prepared.
[0122]
Next, a pad oxide film 8 is provided on the semiconductor layer 3 by thermally oxidizing the upper surface of the semiconductor layer 3 by 20 nm, and a Si film having a thickness of 50 nm is formed on the pad oxide film 8 by a CVD method._ThreeN_FourA membrane 9 is provided.
[0123]
Next, a resist pattern having a pattern in which openings are arranged is provided by a lithography process, and using this as a mask, the pad oxide film 8 and Si by an ordinary etching process such as RIE._ThreeN_FourThe film 9 is patterned.
[0124]
Next, as shown in FIG. 10, a resist pattern covering a certain region including the pattern in which the openings 10 are arranged (for example, a range surrounded by a dotted line A9 in FIG. 9) is provided, and this resist pattern is used as a mask to form Si._ThreeN_FourThe film 9 and the pad oxide film 8 are patterned by RIE.
[0125]
After removing the resist subsequently, the remaining Si_ThreeN_FourUsing the film 9 and the pad oxide film 8 as a mask, the etching rate for silicon is Si_ThreeN_FourThe semiconductor layer 3 is patterned by performing selective RIE (reactive ion etching, reactive ion etching) faster than the etching rate for the film.
[0126]
At the stage shown in FIG. 10, Si other than a certain region (in this case, the range surrounded by the dotted line A9)._ThreeN_FourThe film 9, the pad oxide film 8, and the semiconductor layer 3 are removed.
[0127]
Following silicon etching, SiO₂Etching rate with respect to Si_ThreeN_FourBy performing selective RIE, which is faster than the etching rate for the film, SiO 2 is formed in the opening 10.₂A shape in which the upper end of the film 2 is located below the lower end of the semiconductor layer 3 (FIG. 8) or SiO 2 in the opening 10₂A shape (FIG. 26) in which the surface of the film 2 is inclined can also be obtained. Si_ThreeN_FourThe two-layer structure of the film 9 and the pad film (pad oxide film 8) is Si_ThreeN_FourA single-layer structure of only the film 9 may be used (hereinafter, a single-layer structure and a multilayer structure are collectively referred to as a mask film 9).
[0128]
The material of the mask film may be any material that can selectively etch the semiconductor layer 3, such as SiO2.₂But it ’s okay. Further, the shape of the opening 10 is not limited to the shape shown here. For example, the shapes shown in FIGS. 27 to 34 and FIGS. 46 to 49 may be used. In the process described here, SiO₂The main reason for providing the pad film 8 made of Si is Si_ThreeN_FourPreventing the semiconductor layer 3 from being stressed by the direct contact between the film 9 and the semiconductor layer 3;_ThreeN_FourBy directly contacting the film 9 and the semiconductor layer 3, Si_ThreeN_FourPreventing a large amount of interface states from being generated at the interface between the film 9 and the semiconductor layer 3;_ThreeN_FourThe object is to avoid the problem caused by the direct contact between the film 9 and the semiconductor layer 3. Si_ThreeN_FourThe pad oxide film 8 may be omitted when the influence of problems caused by direct contact between the film 9 and the semiconductor layer 3 is small.
[0129]
In addition, after forming the structure shown in FIG. 10, when the opening 10 is formed in the semiconductor layer 3 by etching and then the upper portion of the buried insulating layer 2 is etched, in order to prevent the mask film from being completely lost by etching, It is preferable to select a combination of the material of the mask film and the material of the buried insulating layer 2 so that only the buried insulating layer can be selectively etched. Further, when the combination does not satisfy this condition, the following is performed. For example, the mask film 9 is the same SiO as the buried insulating layer 2.₂In this case, the mask film 9 may be thickened in anticipation that part of the mask film 9 is removed during the etching of the buried insulating layer 2. Generally speaking, when the buried insulating layer 2 is etched after the semiconductor layer 3 is etched in the opening 10 and the material of the buried insulating layer 2 and the material of the mask film 9 are the same, the buried insulating layer 2 is Etching depth T_boxovThan the thickness T of the mask film_maskShould be increased.
[0130]
Further, after the semiconductor layer 3 is exposed, a heat treatment step for planarizing and cleaning the side surface of the exposed semiconductor layer 3 before forming a gate insulating film on the surface of the semiconductor layer 3 may be added. For example, hydrogen annealing is performed. Typical hydrogen annealing conditions are 10 to 50000 Pa, 850 to 1100 ° C., and about 5 to 60 minutes. However, particularly when the distance between the openings 10 is narrow and the thickness of the semiconductor layer 3 in the substrate plane direction is thin, the semiconductor layer 3 may be heat-treated in a shorter time or at a lower temperature in order to avoid aggregation of the semiconductor layer 3. Further, other gas such as HCl may be mixed in the hydrogen atmosphere.
[0131]
Further, after providing the opening 10 arranged so as to cross the semiconductor layer 3, the exposed side surface of the semiconductor layer 3 is exposed to SiO 2.₂A step of flattening the side surface of the exposed semiconductor layer 3 may be added by covering with a film and performing heat treatment at a temperature of 980 ° C. or higher (more desirably, a temperature of 1200 ° C. or higher) for 1 hour or longer. Here, the temperature of 980 ° C. or higher is SiO₂It is a temperature necessary for imparting fluidity to the membrane, and a temperature of 1200 ° C. or higher is a temperature necessary for remarkable flow. The heat treatment is performed in nitrogen or in an inert gas such as Ar. Further, the width W of the semiconductor layer 3 constituting the channel formation region 7 is obtained by mixing oxygen in the atmosphere for the heat treatment and oxidizing the exposed side surface of the semiconductor layer 3._siMay be performed (the thickness in the substrate plane direction of the semiconductor layer 3 constituting the channel formation region 7 is reduced).
[0132]
In addition, after the opening 10 arranged so as to cross the semiconductor layer 3 is provided, the exposed side surface of the semiconductor layer 3 is covered with an insulating film. This insulating film is made of, for example, SiO.₂Film, Si_ThreeN_FourIt consists of insulators, such as a film | membrane, for example, consists of a multilayer film which consists of several insulators. By heating with a heat source such as a laser beam, an electron beam, or an electric heater, a semiconductor region (semiconductor layer) in which a conduction path or a channel formation region is formed melts a partial region near the side surface, You may perform the process to crystallize.
[0133]
Similarly, by heating with a heat source such as a laser beam or an electron beam, or an electric heater, the entire semiconductor region (projection-shaped semiconductor layer) in which the conduction path or channel formation region is formed is melted. The region may be recrystallized. The purpose of this process is to flatten the unevenness generated on the side surface of the semiconductor layer 3 by the RIE process. The power and energy of a beam such as a laser beam or an electron beam, the temperature of an electric heater, and the scanning speed of the beam and electric heater are preferably the surface of a semiconductor region (projection-shaped semiconductor layer) where a conduction path or a channel formation region is formed. The semiconductor region (projection-shaped semiconductor layer) in which the source / drain region is formed is not melted by melting the projecting portion where the conduction path is formed or melting the projecting portion where the conduction path is formed. It is preferable.
[0134]
This is because, in the process of lowering the temperature of the substrate after beam scanning, a seed crystal (seed) is formed in a region inside a semiconductor region that is not melted (projection-shaped semiconductor layer) or a source / drain region that is not melted. ) For recrystallization of the molten region.
[0135]
Further, with the purpose of removing defects such as fixed charges or traps generated in the buried insulating layer 2 due to the melt recrystallization, a high-temperature heat treatment step (1000 ° C. or more, typically 1300 ° C. or more after melt crystallization) is performed. (1360 ° C., 1 hour or longer, oxidizing atmosphere or non-oxidizing atmosphere), or a lower temperature heat treatment step in an oxidizing atmosphere may be performed.
[0136]
Next, using the CVD method, SiO₂An insulating film for forming the dummy gate insulating film 18 is deposited by 10 nm and etched back by RIE (the process of removing the material film deposited on the flat part and leaving the material film deposited on the side wall part). The dummy gate insulating film 18 is provided on the inner wall of the opening 10 in the semiconductor layer 3 and the side surface of the semiconductor layer 3 (side surface around the semiconductor layer 3 forming the element region).
[0137]
Subsequently, polysilicon is deposited by CVD, and this is processed by normal lithography and RIE to provide a dummy gate electrode 11. The shape at this stage is the pad oxide film 8, Si._ThreeN_FourExcept for the presence of the film 9 and the presence of the dummy gate insulating film 18 and the dummy gate electrode 11 in place of the gate insulating film 6 and the gate electrode 5, respectively, the same as in FIG. 1 (in FIG. 39, the dummy gate electrode 11 39. However, in FIG. 39, the dummy gate insulating film 18 is omitted for the sake of clarity.
[0138]
Here, the dummy gate insulating film 18 and the dummy gate electrode 11 are formed by a so-called replacement gate process in which the gate insulating film 6 and the gate electrode 5 are formed again in a space obtained by removing them later. It is preparation for implementation.
[0139]
When the replacement gate process is not performed, the gate insulating film 6 is formed instead of forming the dummy gate insulating film 18 and the gate electrode 5 is formed instead of forming the dummy gate electrode 11 (the gate electrode 5 in FIG. 39). 39. However, in FIG. 39, the gate insulating film 6 is omitted for easy understanding of the drawing), and subsequently, introduction of impurities into the source / drain connection region described below, formation of the source / drain, wiring The transistor may be formed by performing the above. In this case, in the process from FIG. 11 to FIG. 16, a shape in which the gate insulating film 6 is provided in place of the dummy gate insulating film 18 and the gate electrode 5 is provided in place of the dummy gate electrode 11 is obtained.
[0140]
Further, here, the dummy gate insulating film 18 is deposited by CVD if the dummy gate insulating film 18 is formed by thermal oxidation. After the dummy gate insulating film 18 is removed, the mask film ( In this case, the pad oxide film 8 and Si_ThreeN_FourThe width of the semiconductor layer 3 constituting the channel formation region 7 in the substrate plane direction is narrower than the width in the substrate plane direction of the two-layer film 9 of the film 9. This is because particular attention has been paid to preventing the problem that the flatness in the vertical direction is liable to deteriorate due to the step 3 being stepped back from the edge of the mask film to cause a step.
[0141]
However, generally, the gate insulating film 6 and the dummy gate insulating film 18 are made of SiO.₂An insulating film other than the above may be used, and SiO formed by thermal oxidation.₂It may be a film. In general, the dummy gate insulating film 18 may be any material that can be selectively removed from the semiconductor layer 3.
[0142]
The dummy gate electrode 11 is made Si_ThreeN_FourFor example, the dummy gate insulating film 18 may be omitted if the dummy gate electrode 11 can be selectively removed from the semiconductor layer 3. good.
[0143]
Then Si_ThreeN_FourRIE is performed under conditions that are selective to the film to remove the dummy gate insulating film other than the lower part of the dummy gate electrode 11, and then a PSG (phosphorus glass) film 12 is deposited to a thickness of 200 nm on the whole, and this is performed by RIE Is etched back, and a sidewall-shaped PSG film 12 is provided on the inner wall of the opening 10 and the side surface of the semiconductor layer 3.
[0144]
FIG. 11 is a cross-sectional view taken along line A10-A10 ′ of FIG. 10, FIG. 12 is a cross-sectional view taken along line B10-B10 ′ of FIG. 10, and is a cross-sectional view taken along line C10-C10 ′ of FIG. It is shown in FIG.
[0145]
In this process, PSG is deposited by attaching PSG to the inner wall of the opening 10 and diffusing high-concentration phosphorus from the PSG into the semiconductor region adjacent to the opening 10 on both sides of the gate electrode (or dummy gate electrode) 5. High concentration (5 × 10 5) in the semiconductor layer 3 on both sides of the gate electrode 5.¹⁸cm^-3Or more, preferably 3 × 10¹⁹cm^-3The above-described phosphorus is introduced to form the source / drain connection portion 32.
[0146]
Note that the heat treatment (for example, 800 ° C. for 10 seconds) for diffusing phosphorus from PSG may be performed immediately after PSG deposition, or may be performed after several steps after PSG deposition. A method of diffusing phosphorus from PSG at the same time as another thermal process (for example, activation after ion implantation into the source / drain, gate oxidation) performed after deposition of PSG may be used.
[0147]
FIG. 14 shows the case where the width of the opening 10 in the source / drain direction is large, and the opening 10 is not filled with PSG. However, even in this case, the adhesion of PSG to the inner wall of the opening 10 is guaranteed. So there is no problem. FIG. 15 is a plan view in a state corresponding to FIG. N due to thermal diffusion from PSG⁺FIG. 16 is a cross-sectional view at a position corresponding to a cross section taken along line B10-B10 'in a state where the type source / drain region 4 is formed.
[0148]
In the case of a p-channel transistor, a p-type impurity diffusion source such as BSG (boron glass) is used instead of PSG. Also in the case of an n-channel transistor, an n-type impurity diffusion source (for example, arsenic glass) other than PSG may be used instead of PSG. In addition, in BPSG (boron, phosphorous glass) containing both p-type impurity boron and n-type impurity phosphorus, a p-type or n-type transistor in which one of boron and phosphorus is increased is used. You may use for manufacture.
[0149]
Source / drain regions are formed in the semiconductor layer 3 on both sides of the gate electrode 5 and away from the opening 10 by a normal process. For example, by ion implantation, plasma doping, or the like, an n-type impurity in the case of an n-channel transistor and a p-type impurity in a case of a p-channel transistor are highly concentrated (3 × 10¹⁹cm^-3Or more, preferably 1 × 10²⁰cm^-3~ 3x10²⁰cm^-3). For example, an impurity that forms a donor such as phosphorus or arsenic is used as the n-type impurity, and an impurity that forms an acceptor such as boron is used as the p-type impurity. Further, for the purpose of reducing parasitic resistance, the source / drain regions may be subjected to epitaxial growth of a semiconductor, selective growth of a polycrystalline or amorphous semiconductor, or silicidation.
[0150]
Note that the mask film 9 on the semiconductor layer 3 is provided for the purpose of protecting the semiconductor layer 3 during the processing of the dummy gate electrode 11 (or the gate electrode 5 in place thereof). Therefore, after the dummy gate electrode 11 (or the gate electrode 5 in place thereof) is formed by processing by RIE, the impurity is introduced into the source / drain region. It is desirable to be removed by RIE or wet etching at any stage prior to the introduction of.
[0151]
After the PSG is deposited, the PSG is etched back by RIE, and in the step of forming the side wall made of PSG, if the mask film 9 and the pad oxide film 8 in the region excluding the lower part of the gate electrode and the lower part of the PSG side wall are removed simultaneously Thus, a shape in which the upper surface of the semiconductor layer 3 is exposed in the region where the source / drain regions are formed as shown in FIG.
[0152]
Further, the PSG sidewall is formed with the mask film 9 and the pad oxide film 8 left (FIGS. 12 and 13), and after the impurity diffusion from the PSG, the mask film 9 and the pad oxide are formed before the source / drain regions are formed. RIE may be performed for the purpose of removing the film 8 (at this time, the upper portion of the PSG is also removed, but there is no problem because impurity diffusion from the PSG has already been performed).
[0153]
Alternatively, the mask film 9 and the pad oxide film 8 may be removed by an etching process such as RIE after the dummy gate electrode 11 (or the gate electrode 5 instead thereof) is processed by RIE and before the deposition of PSG. In this case, the element shape finally obtained through various steps is as shown in FIG. If the mask film 9 and the pad oxide film 8 are removed at any stage after the deposition of PSG, the shape of FIG. 36 is finally obtained.
[0154]
After the PSG is deposited and etched back, SiO is deposited by CVD.₂Are deposited to form an interlayer insulating film 13, and the interlayer insulating film 13 is planarized by CMP using the dummy gate electrode 11 as a stopper. At this time, the upper portion of the dummy gate electrode 11 is exposed at the same time. Subsequently, the dummy gate electrode 11 is removed by RIE, and then the dummy gate insulating film 18 is removed by RIE.
[0155]
Subsequently, a gate insulating film 14 having a thickness of 2 nm is formed by thermal oxidation, and a conductive material such as TiN is buried in the slit obtained by removing the dummy gate electrode 11 by sputtering to form the gate electrode 5 (FIG. 18). , FIG. 19).
[0156]
FIG. 19 shows a shape when the gate insulating film 14 is formed by thermal oxidation, and FIG. 18 shows a shape when the gate insulating film 14 is formed by CVD.
[0157]
Thereafter, openings are formed in the interlayer insulating film on the gate electrode and the source / drain regions (respectively, an opening for forming the gate contact 17 and an opening for forming the source / drain contact 16). After the deposition, this is patterned and the wiring 24 is provided, whereby the field effect transistors shown in FIGS. 35 to 38 are obtained. Here, although the wiring connected to the gate electrode 5 is not drawn, the wiring is connected to the gate electrode 5 via the gate contact 17 in the same manner as the connection to the source / drain region 4 via the source / drain contact 16. .
[0158]
  36 and 38 are cross-sectional views taken along line B41-B41 'of FIG. 35, and FIG.FIG.It is a C41-C41 'sectional view taken on the line. However, FIG. 36 shows the case where the mask film 9 and the pad oxide film 8 are removed before the deposition of PSG, and FIG. 38 shows the case where the mask film 9 and the pad oxide film 8 are removed after the deposition of PSG. FIG. 37 shows the case where the openings are not completely filled with PSG (FIG. 14).
[0159]
  After removing the dummy gate insulating film by RIE, the dummy gate insulating film is removed by RIE.ByIn order to remove damage and contamination generated in the semiconductor layer during removal, part of the surface of the semiconductor layer constituting the channel formation region may be removed by dry etching. In this case, isotropic etching is preferable for dry etching. As an etching gas, Cl₂, CF_Four, CHF_ThreeHCl or the like may be used. In addition, at the same time as performing dry etching, the semiconductor layer constituting the channel formation region may be etched from both side surfaces in order to make the semiconductor layer thinner. For example, thinning may be performed until the width of the semiconductor layer becomes about 5 to 10 nm for the purpose of suppressing the short channel effect.
[0160]
Of course, in the step of forming the dummy gate insulating film 18 and the dummy gate electrode 11, if the gate oxide film 6 and the gate electrode 5 are formed instead of these, the conductive material is removed from the removal of the dummy gate insulating film. The above steps leading to the formation of the gate electrode 5 by embedding are not required.
[0161]
Further, after the semiconductor layer is exposed, a heat treatment step for planarizing and cleaning the exposed side surface of the semiconductor layer before forming the gate insulating film on the surface of the semiconductor layer may be added. For example, hydrogen annealing is performed. Typical hydrogen annealing conditions are 10 to 50000 Pa, 850 to 1100 ° C., and about 5 to 60 minutes. However, particularly when the interval between the openings is narrow and the semiconductor layer is thin, the semiconductor layer may be heat-treated in a shorter time or at a lower temperature in order to avoid aggregation of the semiconductor layer. Further, other gas such as HCl may be mixed in the hydrogen atmosphere.
[0162]
When the width of the source / drain connection portion is large (for example, the structure shown in FIGS. 6 and 46 to 49), the impurity is introduced into the source / drain connection portion by performing normal ion implantation from above. May be. When ions are implanted into the source / drain connection portion from above, it is preferable to remove the mask film 9 and the pad film 8 (FIG. 49). The mask film 9 and the pad film 8 may be simultaneously removed from both the source / drain connection portion and the source / drain region, and impurities may be simultaneously introduced.
[0163]
In addition, when ion implantation is performed from the top to the source / drain region and the source / drain connection portion, ion implantation with different energy may be repeated a plurality of times in order to make the impurity concentration in the direction perpendicular to the substrate plane uniform.
[0164]
Further, the heat treatment for activating the impurity introduced into the semiconductor region such as the channel formation region, the source / drain connection portion, or the source / drain region may be performed immediately after the introduction of the impurity by ion implantation or the like. It may be carried out at an appropriate stage before the metal layer is provided.
[0165]
In the field effect transistor manufacturing method described above, the mask layer (here, Si_ThreeN_FourSince the element layer is formed by patterning the semiconductor layer 3 in a region excluding the excessive opening pattern, and then forming the element region in advance, the width of the semiconductor layer constituting the channel formation region is increased. It can be formed uniformly.
[0166]
Here, if an opening pattern and an element region pattern are formed simultaneously without providing an extra arrangement in the opening pattern, the channel formation region located at the end of the opening pattern arrangement (in FIG. The width of the resist pattern corresponding to the right and leftmost semiconductor regions) is reduced by the influence of light rays (or beams of electron beams, X-rays, etc.) exposed to a wide region outside the device region. As a result, as shown in FIG. 51, the width of the semiconductor layer constituting the channel formation region located at both ends of the opening pattern arrangement may be reduced (proximity effect). On the other hand, when this manufacturing method is used, this problem does not occur, and an element region having a uniform width can be obtained as shown in FIG.
[0167]
In the manufacturing method of the present embodiment, a mask layer (here, SiO 2) is formed on the semiconductor layer constituting the channel formation region.₂Layer and Si_ThreeN_FourThe semiconductor layer constituting the channel formation region is not damaged during etching of the gate electrode (or dummy gate electrode). The material of the mask layer may be any material as long as the entire mask layer is not etched and disappears during the gate etching. For example, SiO₂Layer, Si_ThreeN_FourA material that is not or hardly etched when the gate electrode or dummy gate electrode is etched, such as a layer, may be selected.
[0168]
After removing the dummy gate electrode and the dummy gate insulating film, an insulating sidewall material, for example, a second Si having a thickness of 5 nm_ThreeN_FourA film is deposited on the entire surface by CVD, and then this insulating material is etched back by RIE to form sidewalls made of the insulating material in the slit obtained by removing the dummy gate electrode and the dummy gate insulating film. You may add the process to do. At this time, if both the semiconductor layer constituting the channel formation region and the dummy gate electrode have substantially vertical side surfaces, the height of the dummy gate electrode (the height from the lowermost end to the uppermost end in contact with the buried oxide film) ) Is at least twice that of the semiconductor layer constituting the channel formation region, the insulating sidewall material (here, the second Si)_ThreeN_FourBy performing RIE on the film at least as much as the thickness of the semiconductor layer constituting the channel formation region, an insulating sidewall material (here, a second Si) is formed on the sidewall of the semiconductor layer._ThreeN_FourInsulating sidewall material (here, second Si) only on the inner wall of the slit_ThreeN_FourFilm) can be provided.
[0169]
When a side wall made of an insulating material is provided on the inner wall of the slit, the semiconductor layer in the slit can be cleaned or etched without damaging the material adjacent to the slit (here PSG).
[0170]
For example, to remove contamination on the side surface of the semiconductor layer, or the width W of the semiconductor layer_siIn order to reduce the thickness of the semiconductor layer, the side surface of the semiconductor layer is once thermally oxidized (for the purpose of removing contamination, 10 times the gate oxide film thickness or less, and there is no particular range for the purpose of thinning. The process is called sacrificial oxidation). This is diluted with dilute hydrofluoric acid or buffered hydrofluoric acid.₂Even if the step (sacrificial oxide film removing step) of removing the film with the etching liquid is performed, since both sides of the slit are covered with the insulating sidewall material, damage to the material (here PSG) on both sides of the slit is small.
[0171]
As a method of providing a side wall on the gate electrode 5 (or the dummy gate electrode 11), the height h of the gate electrode 5 (or the dummy gate electrode 11) from the surface of the buried insulating layer in the opening formed in the semiconductor layer._gThe height t of the semiconductor layer from the surface of the buried insulating layer_SiAfter the gate electrode 5 (or dummy gate electrode 11) is formed on the structure of FIG. 10, an insulating sidewall material is formed so as to cover the surface of the gate electrode 5 (or dummy gate electrode 11). Deposit, then t_si(H_g-T_SiBy etching back over a thickness less than (), a side wall can be formed on the side surface of the gate electrode at a position from the lower end of the gate electrode to the height of the upper end of the semiconductor layer.
[0172]
However, in the method for forming the insulating side wall on the inner wall of the slit described in the present embodiment and the method for forming the insulating side wall in the gate electrode 5 (or dummy gate electrode 11) described in the present embodiment, When the gate electrode 5 (or dummy gate electrode 11) is formed on the structure, both side surfaces of the gate electrode 5 (or dummy gate electrode 11) cannot be completely covered with insulating sidewalls (the former method is used at this time). In the latter method, the side surface of the gate electrode is partially exposed).
[0173]
Therefore, when the semiconductor material is epitaxially grown in the source / drain regions, there is a problem that the semiconductor material is also epitaxially grown on the side surface of the gate electrode. This problem is solved based on the manufacturing method described as the fourth embodiment.
[0174]
In addition, each process in this embodiment can be used for manufacture of the field effect transistor which concerns on Embodiment 1 and 2 or the field effect transistor which accompanies various deformation | transformation which concerns on Embodiment 1 and 2. FIG.
[0175]
In addition, by combining a part of each process in the present embodiment with another general field effect transistor manufacturing method, the field effect transistor according to the first and second embodiments, or the first and second embodiments are combined. It is also possible to manufacture field effect transistors with such various modifications.
[0176]
In addition, the film thickness, dimensions, and material of each part in the present embodiment may be appropriately changed based on the description in the first and second embodiments.
[0177]
(Embodiment 4) Next, as Embodiment 4, an insulating film (for example, Si) is formed on a gate electrode or a dummy gate electrode according to the present invention._ThreeN_FourA method for forming the sidewall of the film will be described with reference to FIGS.
[0178]
20 to 25 illustrate a process of providing a dummy gate electrode (or gate electrode) and a side wall attached to the dummy gate electrode after the structure of FIG. 10 is formed. 20 to 22 correspond to the cross section taken along line B10-B10 'of FIG. 10, and FIGS. 23 to 25 correspond to the vicinity of the dummy gate electrode 11 taken along the line C10-C10' of FIG.
[0179]
In the manufacturing method of the present invention shown in the fourth embodiment, when the side wall is provided on the dummy gate electrode shown in the first embodiment, or in the manufacturing method shown in the third embodiment, the gate electrode 5 is replaced with the step of providing the dummy gate electrode. When the step of providing is performed, the gate electrode 5 can be used for providing a side wall.
[0180]
Further, the manufacturing method of the fourth embodiment may be used for manufacturing a field effect transistor in which source / drain regions are connected to each other by a single semiconductor layer, as will be described later.
[0181]
First, the case where a side wall is provided in the dummy gate electrode 11 will be described. A structure in which the element region is patterned (for example, FIG. 10) is formed by the manufacturing method shown in the second embodiment, and then the dummy gate insulating film 18 and the dummy gate electrode 11 are formed in the same manner as the manufacturing method shown in the third embodiment. (For example, FIG. 39). Note that the height difference between the upper end of the semiconductor layer 3 and the upper end of the dummy gate electrode 11 in the fourth embodiment is, for example, 150 nm. Further, as will be described later, a step of introducing impurities into the semiconductor layer 3 may be performed after the formation of the dummy gate electrode 11.
[0182]
Next, a second Si is formed so as to cover the entire surface._ThreeN_FourA film 20 is deposited to a thickness of 10 nm by CVD. Then the second CVDSiO₂A film 21 is deposited to a thickness of 200 nm by a CVD method, and a second CVDSiO is deposited by CMP.₂The film 21 is planarized (FIGS. 20 and 23). In the CMP process, the second Si_ThreeN_FourThe film 20 functions as a stopper for CMP.
[0183]
Subsequently, the second Si_ThreeN_FourFilm 20 and second CVDSiO₂The film 21 is etched to a depth of 15 nm from the surface by RIE, and then polysilicon is deposited to 20 nm, the polysilicon is etched back by RIE, and the first sidewall 22 (the material is polysilicon in this case) Are provided on both side surfaces of the upper portion of the dummy gate electrode 11 (FIGS. 21 and 24).
[0184]
Subsequently, using the dummy gate electrode 11 and the first sidewall 22 as a mask, the second Si_ThreeN_FourFilm 20 and second CVDSiO₂By etching back the film 21, the second Si_ThreeN_FourFilm 20 and second CVDSiO₂A gate sidewall (gate sidewall) made of a part of the film 21 is provided on the side surface of the dummy gate electrode 11.
[0185]
22 and 25, the second Si attached to the side surface of the dummy gate electrode 11_ThreeN_FourFilm 20 and second CVDSiO₂A portion constituted by the film 21 is a gate sidewall. In this etch-back process, Si having a thickness that is substantially the difference in height between the upper end of the buried insulating film 2 and the upper end of the dummy gate electrode 11._ThreeN_FourIf etching back is performed longer than the time required for etching the film, the second Si is removed except for the portion that becomes the gate sidewall._ThreeN_FourFilm 20 and second CVDSiO₂The film 21 is removed, and a structure in which the semiconductor layer is exposed on the side surface of the source / drain connection portion 32 is obtained (the cross-sectional shape parallel to the A10-A10 ′ cross-sectional line at a position away from the dummy gate electrode 11 is shown in FIG. Shown in
[0186]
The semiconductor layer 3 shown in FIG. 68 corresponds to a portion where a source / drain connection portion is formed. Note that a part of the buried insulating layer may be removed at the same time during the etch back. Further, during the etch back process, the dummy gate insulating film 18 adhering to the side surface of the semiconductor region 3 excluding the lower portion of the dummy gate electrode 11 is removed at the same time. The mask film 9 on the semiconductor layer is also removed at the same time.
[0187]
FIG. 69 is an enlarged perspective view of the shape of the vicinity of the gate sidewall after the etch back in order to clarify the positional relationship between the gate sidewall, the dummy gate electrode 11 (or gate electrode), and the semiconductor layer 3. .
[0188]
Note that in this specification, both the sidewall provided on the gate electrode and the sidewall provided on the dummy gate electrode are referred to as a gate sidewall. The reason is that the side wall provided on the dummy gate electrode also becomes a side wall attached to the side surface of the gate electrode when the dummy gate electrode is replaced with the gate electrode in a later step.
[0189]
Thereafter, impurities are introduced into the source / drain connection portion and the source / drain region, and the dummy gate and the dummy gate insulating film are removed and slits in the same procedure as the steps after FIG. 11 in the manufacturing method according to the third embodiment. After forming a gate insulating film and a gate electrode in the obtained slit, a wiring is connected to the gate electrode and the source / drain region to form a transistor in the form of FIGS. 75 is a cross-sectional view corresponding to FIGS. 20 to 22.
[0190]
In addition, a process of siliciding the upper part of the source / drain region may be performed. When the width of the opening between the source / drain connection portions is large, the side surfaces of the source / drain connection portions may be silicided. Further, when performing these silicidation steps, the side surfaces of the source / drain regions (portions corresponding to the outer periphery of the element region) may or may not be silicided.
[0191]
When the dummy gate electrode is not formed, the invention of the present embodiment may be similarly applied to the gate electrode provided in place of the dummy gate electrode. In this case, the steps from removing the dummy gate to embedding the gate electrode in the slit are omitted after replacing the dummy gate electrode with the gate electrode and the dummy gate insulating film with the gate insulating film.
[0192]
The second CVD SiO₂The second Si without the film 21_ThreeN_FourA gate sidewall in which the side surface of the film 20 is exposed may be provided (see FIG. 58. In this case also, the effect of the invention does not change). Second CVDSiO₂For example, when the lateral projection of the first sidewall 22 is small, the sidewall without the film 21 is made of SiO 2 by hydrofluoric acid after the formation of the gate sidewall.₂This occurs when etching is performed.
[0193]
The feature of this embodiment is that after the dummy gate electrode (or gate electrode) is once embedded in the insulating film, only a part of the upper portion of the dummy gate electrode (or gate electrode) is exposed, and the exposed dummy gate electrode (or gate) is exposed. The first sidewall (first sidewall) is provided on the side surface of the electrode), and the dummy gate electrode (or gate electrode) is embedded using the dummy gate electrode (or gate electrode) and the first sidewall as a mask. By etching the film, a gate sidewall made of an insulating film in which the dummy gate electrode (or gate electrode) is embedded is formed.
[0194]
When the gate sidewall is provided in this way, various processes (ion implantation, silicidation, epitaxial growth of semiconductor, selection of amorphous semiconductor or polycrystalline semiconductor) are performed on the source / drain region after the dummy gate electrode (or gate electrode) is formed. When performing growth, the gate electrode and the semiconductor layer under the gate electrode (or under the dummy gate electrode and the dummy gate electrode) can be protected.
[0195]
Further, when the gate side wall is formed in this way, at the time when the dummy gate electrode is removed and the slit is formed, the inner wall of the slit constitutes the Si that forms the gate side wall._ThreeN_FourA structure in which the oxide film and the PSG film are not exposed on the inner wall of the slit is obtained. Therefore, the dummy gate oxide film can be removed by wet etching.
[0196]
This is because SiO such as a dummy gate oxide film.₂Etching solution containing hydrofluoric acid, which is usually used when removing the film, is PSG film, SiO 2₂Si having resistance to etching action by hydrofluoric acid, while having an etching action on the material constituting the side wall of the slit such as a film_ThreeN_FourIf the inner wall of the slit is protected by the film, the side wall of the slit is not subjected to the etching action when the dummy gate oxide film is removed.
[0197]
If wet etching cannot be used to remove the dummy gate oxide film, it is necessary to remove the dummy gate oxide film by dry etching such as RIE. In general, when dry etching is performed, a semiconductor layer constituting a channel formation region is required. In some cases, however, there is a problem that damage such as crystal defects or contamination is likely to occur. On the other hand, according to the manufacturing method described in this embodiment, the dummy gate oxide film can be removed by wet etching, and damage to the semiconductor layer constituting the channel formation region can be reduced.
[0198]
Similarly, since the periphery of the gate electrode protected by the gate sidewall remaining on the inner wall of the slit is not affected by wet etching, the semiconductor layer constituting the channel formation region is thinned by sacrificial oxidation and subsequent sacrificial oxidation. The film can be etched by wet etching, and damage to the semiconductor layer constituting the channel formation region (particularly damage due to thinning by dry etching) is reduced.
[0199]
When the invention of the present embodiment is similarly applied to a gate electrode that is provided in place of the dummy gate electrode without forming a dummy gate electrode, various processes ( When performing ion implantation, silicidation, epitaxial growth of semiconductor, selective growth of amorphous semiconductor or polycrystalline semiconductor), the gate electrode and the lower portion of the gate electrode can be protected.
[0200]
Note that the step of injecting a high concentration impurity of the same conductivity type as the channel type into the semiconductor layer 3 may be performed after the formation of the dummy gate electrode (or gate electrode) and before the formation of the gate sidewall. This lowers the parasitic resistance of the source / drain connection portion covered by the gate sidewall, particularly when forming a gate sidewall having a thickness of 10 nm or more (thickness in the lateral direction with respect to the gate electrode). It is effective for. Here, in the case of introducing impurities by ion implantation or oblique ion implantation, the dummy gate insulating film (or gate insulating film) in a region not covered by the dummy gate electrode (or gate electrode) is removed when the impurities are introduced. Need not be removed. When introducing impurities by a method such as vapor phase diffusion that prevents impurities from penetrating through the insulating film, the dummy gate insulating film (or gate insulating film) in the region not covered by the dummy gate electrode (or gate electrode) is RIE. It is preferable to introduce impurities after removing them by etching.
[0201]
Further, an etch-back process for forming a gate sidewall (after the formation of the first sidewall 22, the second Si_ThreeN_FourFilm 20 and second CVDSiO₂Step of etching back the film 21)_ThreeN_FourSiO against the film₂Alternatively, the etching may be performed using RIE that is selectively etched. In this case, etch back is Si_ThreeN_FourStop at the surface of the membrane.
[0202]
Then Si_ThreeN_FourThe second Si is etched by anisotropic or isotropic dry etching having an etching action on the film, or wet etching with heated phosphoric acid._ThreeN_FourIf the film 20 is removed, etching of the buried oxide film 2 (for example, the depression of the buried oxide film 2 at both ends of FIG. 22) is suppressed, and the controllability of the shape after the etch back is increased. When the dummy gate insulating film 18 (or gate insulating film) is provided on the side surface of the semiconductor layer 3, the second side is provided on the side surface of the semiconductor layer 3 via the dummy gate insulating film 18 (or gate insulating film). Si_ThreeN_FourA shape to which the film 20 is attached is formed, and selective SiO 2 is formed.₂Following the etching of Si_ThreeN_FourBy performing isotropic dry etching on the film or wet etching with heated phosphoric acid, the dummy gate insulating film 18 (or gate insulating film) is exposed on the side surface of the semiconductor layer 3. At this time, since the gate side wall is provided on the side surface of the gate electrode, short-time wet etching with hydrofluoric acid or the like is performed on the side surface of the semiconductor layer 3 in order to remove the dummy gate insulating film 18 (or gate insulating film). However, the dummy gate insulating film 18 (or the gate insulating film) in contact with the channel formation region is not damaged by the etchant such as hydrofluoric acid. At this time, the gate insulating film (or dummy gate insulating film) located under the gate sidewall is partially etched and lost, but the element characteristics are not affected.
[0203]
The second CVD SiO₂The second Si without the film 21_ThreeN_FourGate sidewalls in which the side surfaces of the film 20 are exposed may be provided (modes corresponding to FIGS. 20 and 25 are shown in FIGS. 64 and 65. In this case, the effect of the invention is not changed). Second CVDSiO₂For example, when the side wall without the film 21 has small projections in the lateral direction of the first sidewall 22 (this is because the thickness of the film deposited for forming the first sidewall 22 is the second Si_ThreeN_Four(This corresponds to a case where the film is thinner than the film 20), or SiO 2 by hydrofluoric acid after the gate sidewall is formed.₂This occurs when etching is performed.
[0204]
After performing the CMP process, the second Si_ThreeN_FourFilm 20 and second CVDSiO₂The depth at which the film 21 is etched from the surface by RIE is not limited to the above (15 nm), and is not particularly limited. However, from the viewpoint of controllability with respect to the width of the first sidewall, the etching depth is larger than the thickness of the film deposited to form the first sidewall 22 (polysilicon in the above example). Is more desirable. For example, when the thickness of the polysilicon is 20 nm, the etching depth here is set in a range larger than 20 nm and smaller than 40 nm.
[0205]
In addition, it is desirable that a gate sidewall is formed on the gate electrode (or dummy gate electrode) at least in the range where the semiconductor layer 3 exists, so that the etching depth here reaches the upper end of the semiconductor layer 3. It is desirable to set it to such an extent that it does not.
[0206]
As described above, in the present embodiment, the second Si is formed on the side surface of the dummy gate electrode (or gate electrode)._ThreeN_FourBy depositing film 20, Si_ThreeN_FourAn example of forming a gate sidewall having a film as a constituent element has been shown. Si as a material deposited on the side of the dummy gate electrode (gate electrode)_ThreeN_FourThe following two can be mentioned as the advantages of selecting a membrane.
[0207]
The first is CVD and the second Si_ThreeN_FourWhen the film 20 is deposited, the second Si is also formed on the dummy gate electrode (or gate electrode)._ThreeN_FourFilm 20 film is deposited, followed by the deposited second CVDSiO₂When the film 21 is planarized by CMP, the second Si deposited on the dummy gate electrode (or gate electrode)_ThreeN_FourThe film 20 serves as a stopper against CMP.
[0208]
Second, when the side wall is formed with respect to the dummy gate electrode, and then the dummy gate electrode is removed to form a slit, the inner wall of the slit becomes the second Si._ThreeN_FourProtected by the film 20, the SiO in the slit using an etching solution such as hydrofluoric acid₂Even when the material is etched, the side wall of the slit is not etched and the shape can be maintained. In addition, SiO in the slit₂Etching is performed on the material when the dummy gate insulating film is removed, or when the surface of the silicon material in the slit is once sacrificed and the oxide film formed by sacrificial oxidation is removed.
[0209]
However, the second CVDSiO₂In the case where a material constituting the dummy gate electrode (or gate electrode) itself (for example, polysilicon constituting the dummy gate electrode) is used as a stopper when the film 21 is planarized by CMP, it is necessary to protect the side wall of the slit. When there is no dummy gate (when a gate electrode is provided from the beginning without forming a dummy gate and a side wall is provided on this, or when the dummy gate insulating film in the slit is removed by RIE, sacrificial oxidation is performed on the silicon material in the slit. If not, etc.), the second Si_ThreeN_FourThe step of providing the film 20 may be omitted. Second Si_ThreeN_FourIf the film 20 is omitted, the second CVDSiO₂A gate sidewall consisting only of the film 21 is obtained. The forms corresponding to FIGS. 20 and 25 in this case are shown in FIGS. 58 and 59, respectively.
[0210]
The second Si_ThreeN_FourInstead of the film 20, an insulating film made of another material may be used, and the second CVDSiO₂An insulating film made of a material other than the film 21 may be used. Second CVDSiO₂Instead of the film 21, a PSG film deposited by means such as CVD or spin coating may be used. After removing the dummy gate insulating film (or gate insulating film), the second CVDSiO₂When a PSG film is deposited instead of the film 21, a step of diffusing impurities from the deposited PSG into the semiconductor layer may be performed.
[0211]
Second Si_ThreeN_FourFilm 20 film, second CVDSiO₂The film thickness of the film 21 and an insulating film made of another material used in place of these is not particularly limited. However, the second CVDSiO can be obtained by performing CMP.₂From the viewpoint of flattening the surface of the film 21 (or an insulating film replacing it), the second CVDSiO₂The film thickness of the film 21 (or an insulating film replacing it) is preferably larger than the height of the gate electrode (or dummy gate electrode). When the gate electrode (or dummy gate electrode) or a substance adhering to the upper portion thereof is exposed by etching as described later (FIGS. 60 and 61), the second CVDSiO₂In the case where the flatness of the surface of the film 21 (or an insulating film replacing the film 21) is not strongly required, the second CVDSiO₂The thickness of the film 21 (or an insulating film that replaces it) may be smaller than the height of the gate electrode (or dummy gate electrode). Second Si_ThreeN_FourThe thickness of the film 20 is not particularly limited, but is typically 1000 nm or less, more preferably 50 nm or less.
[0212]
Further, as in the embodiment shown in FIGS. 20 to 25, an insulating film (here, the second CVDSiO) covering the dummy gate electrode (or gate electrode) is used.₂By planarizing the film 21) by CMP, the upper portion of the dummy gate electrode (or gate electrode) (or the second Si shown here) is obtained._ThreeN_FourRather than exposing the dummy gate electrode or the substance attached to the upper portion of the gate electrode as in the film 20, the etching process by RIE or the like is performed on the upper portion of the dummy gate electrode (or gate electrode) or the dummy gate electrode (or A process of etching back may be used by carrying out until the substance attached to the upper part of the gate electrode) is exposed. The forms corresponding to FIGS. 20 and 25 in this case are shown in FIGS. 60 and 61, respectively.
[0213]
Further, the first sidewalls 22 projecting on both sides above the dummy gate electrode (or gate electrode) may be polysilicon as in the embodiments shown in FIGS. 20 to 25, or may be made of a material other than polysilicon. . An insulating film (second CVDSiO) covering the dummy gate electrode (or gate electrode) with respect to the material of the first sidewall 22₂The material of the insulating film covering the first sidewall 22 and the dummy gate electrode (or the gate electrode) may be selected so that the material constituting the portion corresponding to the film 21 can be selectively etched. . For example, the first sidewall 22 is made of a metal such as W or Mo, a silicide such as titanium silicide, or a metal compound such as TiN, and the second sidewall is made of SiO.₂Or Si_ThreeN_Four, Amorphous carbon fluoride, siloxane and derivatives thereof, and various insulating films such as an organic insulating film.
[0214]
(Embodiment 5)
In the third and fourth embodiments, the PSG film is not provided, and impurities are introduced into the semiconductor layer adjacent to the opening by a normal impurity introduction process other than solid phase diffusion from the PSG film, such as ion implantation or plasma doping. May be introduced. In this case, SiOG instead of PSG after the introduction of impurities.₂, Si_ThreeN_FourIt is sufficient to deposit an insulating material such as.
[0215]
(Embodiment 6)
Instead of providing a PSG film in the opening, an insulating film side wall (gate side wall) is provided on the gate electrode 5 or the dummy gate electrode 11 in accordance with the method of Embodiment 4, and then the impurity having the same conductivity type as the channel type is formed by selective epitaxial growth. When a semiconductor (Si, silicon-germanium mixed crystal, etc.) having a high concentration is grown on the side surface of the source / drain connection portion, a source / drain connection portion having the shape shown in FIGS. 33 and 70 is obtained. In this case, the source / drain connection portion has a shape that becomes thicker while being inclined toward the source / drain region from a position separating the gate sidewall from the connection point with the channel formation region. Such inclination is derived from crystal habits (facets) formed during selective epitaxial growth.
[0216]
FIG. 33 shows a case where a small amount of selective epitaxial growth is performed, and FIG. 70 shows a case where a large amount of selective epitaxial growth is performed. Further, FIG. 34 shows a case where a crystal habit (facet) is not formed during selective epitaxial growth, or a semiconductor (Si, silicon-germanium mixed crystal, etc.) amorphous layer or polycrystal containing impurities of the same conductivity type as the channel type at a high concentration. This is a case where a layer made of the layer is selectively grown.
[0217]
In general, when the growth gas flow rate is relatively small, facets are likely to be formed when the growth temperature is relatively high. When the facet is not formed, the source / drain connection part is inclined and the shape retreating from the gate electrode cannot be obtained, and the parasitic capacitance between the source / drain connection part and the gate electrode is increased as compared with the case where the facet is formed. . In order to avoid this problem, in FIG. 34 where the facet is not formed, a method is adopted in which the side wall provided on the gate electrode (or dummy gate electrode) is set thick so that the parasitic capacitance between the gate electrode and the source / drain connection portion is reduced. You may do it.
[0218]
Note that the semiconductor layer formed by selective epitaxial growth has impurities (particularly the same conductivity type as the channel type and a high concentration impurity after the selective epitaxial growth.¹⁹cm^-3The above concentration) may be introduced by an impurity introduction process such as ion implantation or plasma doping. By supplying a gas containing impurities during selective epitaxial growth, impurities (especially the same conductivity type as the channel type) Concentration impurity, typically 10¹⁹cm^-3The above concentration) may be introduced. In addition, when introducing an impurity after selective epitaxial growth, it is not necessary to introduce an impurity simultaneously with selective epitaxial growth. Further, impurities may be introduced simultaneously with growth, and impurities may be introduced again after growth. The same applies to not only selective epitaxial growth but also selective growth of other semiconductor layers (selective growth of a semiconductor, selective growth of a polycrystalline semiconductor or an amorphous semiconductor are collectively referred to as selective growth of a semiconductor). Impurities are introduced during the selective growth of the semiconductor layer or after the selective growth of the semiconductor layer.
[0219]
When the selective growth of the semiconductor layer is performed, if the upper portion of the source / drain region is exposed, the selective growth proceeds upward also to the upper portion of the source / drain region. If the upper part of the source / drain region is covered with the mask film 9 or the like and is not exposed, epitaxial growth does not occur on the upper part of the source / drain region. In either case, the device characteristics are not adversely affected.
[0220]
For the formation of the source / drain regions, first, selective epitaxial growth (or after selective growth of polycrystalline or amorphous) is performed, for example, a third CVD oxide film is deposited thickly (for example, 200 nm) on the entire surface, and etched back to form the source / drain regions. A thick gate side wall (in this case, a third CVD oxide film) is provided to cover a part of the connection part near the gate electrode (or dummy gate electrode) or the entire source / drain connection part (in this case, the third CVD oxide film is provided on the side wall of the PSG film). However, the mask film on the semiconductor layer is usually removed simultaneously with the formation of the gate sidewall, and if the mask film on the semiconductor layer remains, the mask film can be removed before or after the CVD oxide sidewall formation. Then, a source / drain region is formed using a thick gate sidewall (here, a third CVD oxide film) as a mask. Net objects introduced, for example, may be performed ion implantation. Here, at least a part of the source / drain connection portion near the gate electrode (or dummy gate electrode) is covered. The source / drain connection portion in this region is constituted by a semiconductor layer having a small thickness in the substrate plane direction. This is to protect this part from ion implantation because it is vulnerable to ion implantation damage. The dummy gate itself is Si_ThreeN_FourIn the case of being formed of an insulator such as an organic substance, the step of forming the side wall in the dummy gate is omitted, and the semiconductor is selectively grown on the side surface of the source / drain connection portion by the same procedure as described above, and then Similarly to the above, the step of forming the gate electrode by removing the dummy gate may be performed.
[0221]
When it is necessary to form both an n-channel MOSFET and a p-channel MOSFET in a circuit having a CMOS structure, after performing the step of forming the form of FIG. 21 and before performing the etch back to form the form of FIG. By covering the region where the second channel type transistor is formed with a resist, only the first channel type transistor is subjected to the etching process related to the formation of the gate side wall and the exposure of the semiconductor layer 3 (FIG. 22, FIG. 25), and after the resist is removed, the above-described series of steps relating to epitaxial growth (or selective growth of a semiconductor) and source / drain formation on the source / drain region connection portion are performed. (Alternatively, after forming the configuration of FIG. 20, the region where the second channel type transistor is formed is covered with a resist, and an insulating film that covers the gate electrode only in this case is formed in this case. Is Si_ThreeN_FourFilm and SiO₂The film is etched to a certain depth, after which the resist is removed and the first sidewall 22 is formed. Then, the region where the second channel type transistor is to be formed is again covered with the resist. Etching to form the shape may be performed. Alternatively, each channel type transistor is formed each time the channel type transistor is formed after the shape of FIG. 20 is formed for both channel type transistors and then the whole is covered with a thin CVD oxide film, eg, 10 nm thick. A resist pattern having an opening in the formation region is provided, and after removing the thin CVD oxide film provided on the surface of each channel type transistor formation region, the resist pattern is removed, and the steps of forming the shapes shown in FIG. You may do it. ). Thereafter, the whole is covered with a fourth CVD oxide film (the film thickness is not limited. The film thickness may be as thin as 10 nm. In order to obtain flatness, it may be as thick as 200 nm to 500 nm. These intermediate films. The gate sidewall may be formed by performing a similar process on the region where the second channel type transistor is formed.
[0222]
The manufacturing method of this embodiment may be used for manufacturing a vertical field effect transistor (for example, the shape of FIG. 50) in which channel forming regions are not arranged in parallel (FIG. 40). Each manufacturing process is the same as the manufacturing method described in (Embodiment 4 of the manufacturing method) except that semiconductor patterning is performed in a form in which an element region including a single current path is formed (broken line portion in FIG. 40). Are the same.
[0223]
(Embodiment 7)
When the manufacturing method of Embodiment 6 is used, the shape of the opening provided initially in the semiconductor layer is rectangular as shown in FIG. 32, and after forming the gate electrode 5 (or dummy gate electrode 11), the source / drain connection portion 32 is formed. By performing selective growth of the semiconductor layer, the width of the source / drain connection portion 32 is narrow on the channel formation region 7 side and wide on the source / drain region 4 side, and the width of the source / drain connection portion 32 is continuous between them. Alternatively, a shape (FIGS. 33 and 34) that changes stepwise can be obtained. At this time, as in the sixth embodiment, the semiconductor layer may be simultaneously doped during the selective growth of the semiconductor layer, or during the growth of the semiconductor layer, the doping is not performed, and the grown semiconductor layer is grown after the epitaxial growth. A method of introducing impurities may be used. Further, impurities may be introduced simultaneously with growth, and impurities may be introduced again after growth.
[0224]
In this case, a shape having a rectangular opening as shown in FIG. 32 can be formed as follows. One example will be described with reference to FIGS. 100 nm thick SiO on the silicon substrate 1₂An SOI (silicon-on-insulator) substrate having a buried insulating layer 2 made of a semiconductor layer 3 made of a single crystal silicon layer having a thickness of 120 nm is prepared.
[0225]
Next, a pad oxide film 8 is provided by thermally oxidizing the upper portion of the semiconductor layer 3 by 20 nm, and a Si film having a thickness of 50 nm is formed thereon by a CVD method._ThreeN_FourA membrane 9 is provided.
[0226]
Next, a second mask material 41 is deposited thereon (here, polysilicon having a thickness of 20 nm is deposited as the second mask material 41 by a CVD method).
[0227]
Next, a resist pattern in which rectangles are arranged is provided by a lithography process, the second mask material 41 is patterned using the resist as a mask, and a shape in which the rectangular second mask material 41 (here, polysilicon) is arranged. Get. Here, the width of the second mask material 41 in the arrangement direction (lateral direction in FIG. 41) is, for example, 50 nm. Next, a resist pattern is provided in a region (region 44 in FIG. 41) covering the remaining second mask material 41 excluding the second mask material 41 located at both ends of the array, and this resist is used as a mask at both ends of the array. The second mask material 41 located is removed by an etching process such as RIE, and then the resist pattern is removed.
[0228]
Next, a resist pattern covering a certain region including one end of the plurality of second mask materials 41 is provided at both ends of the rectangular second mask material 41 (range surrounded by a dotted line in FIG. 41). Area 42).
[0229]
Next, using the resist pattern and the second mask material 41 as a mask (that is, selectively with respect to the resist pattern and the second mask material 41), Si that is a mask film located under them_ThreeN_FourThe film 9 is patterned. If the resist is removed here, the shape of FIG. 42 is obtained.
[0230]
Subsequently, when the semiconductor layer 3 (silicon in this case) is etched by selective RIE using the mask material 9 and the second mask material 41 as a mask, the shape of FIG. 43 is obtained. Here, since there is almost no selectivity between the polysilicon which is the second mask material 41 and the silicon 3, the second mask material 41 is lost during the etching of the semiconductor layer 3. Si located under the mask material 41_ThreeN_FourFilm 9 is exposed and Si_ThreeN_FourThe film 9 becomes a mask for etching. Thereafter, a field effect transistor is formed in the same procedure as in the other embodiments. However, the steps of Embodiment 6 are used for the step of selectively depositing a single crystal, amorphous or polycrystalline semiconductor layer on the side surface of the source / drain region connection portion and the side wall forming step preceding it.
[0231]
In the process of FIG. 41, the purpose of removing the second mask material 41 located at both ends of the array is as follows. During exposure for forming a pattern, the patterns positioned at both ends of the array may be formed with a width different from other patterns due to the influence of the proximity effect. Since it is not preferable to mix the second mask material 41 having different pattern widths, it is desirable to remove the material at both ends. However, when the proximity effect is small, it is not necessary to remove the patterns located at both ends of the array. On the other hand, when the influence of the proximity effect is large, a plurality of patterns may be appropriately removed from both ends of the array.
[0232]
Further, the second mask material 41 at both ends of the array is not removed, and the second mask material 41 at both ends of the array is not covered with the resist pattern that covers the region 42, so that both ends of the array having different pattern widths can be obtained. The semiconductor layer forming the channel formation region formed by using the second mask material 41 as a mask is separated from the position where the source / drain region is formed (substantially corresponding to the region 42) so as not to affect the element characteristics. You can also
[0233]
Moreover, when removing each one or several 2nd mask material 41 from the both ends of an arrangement | sequence, the range (area | region 42) which provides the resist pattern which covers the end of several 2nd mask material 41 is from both ends of an arrangement | sequence. After each of the one or more second mask materials 41 is removed, even if the respective one or more second mask materials 41 exist from both ends of the array, I do not care.
[0234]
Next, an embodiment for forming a channel formation region more narrowly will be described with reference to FIGS. 44 and 45. FIG. Similar to the embodiment of FIGS. 41 to 43, a 100 nm thick SiO 2 film on the silicon substrate 1.₂An SOI (silicon-on-insulator) substrate having a buried insulating layer 2 made of a semiconductor layer 3 made of a single crystal silicon layer having a thickness of 120 nm is prepared.
[0235]
Next, a pad oxide film 8 is provided by thermally oxidizing the upper portion of the semiconductor layer 3 by 20 nm, and a Si film having a thickness of 50 nm is formed thereon by a CVD method._ThreeN_FourA membrane 9 is provided.
[0236]
Next, 40 nm thick SiO₂A film is deposited by CVD and patterned to form a second mask forming dummy pattern 43 (meaning a dummy pattern for forming a second mask. It is not the second mask forming dummy pattern. ).
[0237]
Next, polysilicon having a thickness of 30 nm is deposited as a second mask material as a whole, and this is etched back (etching equivalent to 30 nm to 50 nm) to thereby form polysilicon around the second mask forming dummy pattern 43. Sidewalls are formed, and then the second mask formation dummy pattern 43 is removed using dilute hydrofluoric acid, buffered hydrofluoric acid, or the like. Si_ThreeN_FourThe polysilicon side wall remaining on the film 9 corresponds to the second mask material 41 in FIG.
[0238]
Thereafter, similarly to the steps of FIGS. 41 to 43, a resist pattern is provided to cover a certain region including one end of the second mask material 41 (the range of 42 surrounded by a dotted line in FIG. 44).
[0239]
Next, using the resist pattern and the second mask material 41 as a mask, the mask film located under them is Si._ThreeN_FourThe film 9 is patterned. If the resist is removed here, the shape of FIG. 45 is obtained. Subsequently, when the semiconductor layer 3 (silicon in this case) is etched by selective RIE using the mask material 9 and the second mask material 41 as a mask, the same shape as in FIG. 43 is obtained.
[0240]
Thereafter, a field effect transistor is formed in the same procedure as in the other embodiments. However, the steps of Embodiment 6 are used for the step of selectively depositing a single crystal, amorphous or polycrystalline semiconductor layer on the side surface of the source / drain region connection portion and the side wall forming step preceding it.
[0241]
In the process described with reference to FIGS. 44 and 45, the width of the semiconductor layer constituting the channel formation region is the same as that when the second mask material 41 is deposited on the side surface of the second mask formation dummy pattern 43. Although it depends on the deposition thickness, generally, the thickness of a film deposited by CVD can be controlled with high accuracy, so that the width of the semiconductor layer constituting the channel formation region can be controlled with high accuracy.
[0242]
Similarly, since the controllability with respect to the thickness of the deposited film is good, it is advantageous for reducing the width of the semiconductor layer constituting the channel formation region.
[0243]
Here, the semiconductor layer 3 can be selectively etched with respect to the mask film 9 and the second mask material 41, and the second mask forming dummy pattern 43 can be selectively etched with respect to the second mask material 41 and the mask film 9, respectively. The material is selected. For the second mask forming dummy pattern 43, a material that can be selectively etched with respect to the second mask material 41 is selected. However, the second mask material 41 and the mask film 9 are the same material, for example, Si._ThreeN_FourIt can be a membrane. The second mask material 41 and the mask film 9 are made of the same material, and each film thickness is t_mask1, T_mask2, After covering the area indicated by reference numeral 42 in FIG. 41 or 44 with a resist, t_mask2T_mask1+ T_mask2If RIE is performed under the conditions for etching the film thickness of the following amount, both the second mask material 41 and the mask film 9 are not lost at the position of the conduction path. The second mask material 41 or the mask film 9 can be left.
[0244]
In each of the manufacturing methods described with reference to FIGS. 41 to 45 in the seventh embodiment, the side wall formation on the gate electrode described in the fourth embodiment is not performed, or the source / drain connection portion described in the sixth embodiment is performed. This may be applied when the selective epitaxial growth is not performed. Moreover, you may use with respect to the case where a rectangular opening is provided like FIG.
[0245]
Further, the manufacturing methods described in the seventh embodiment with reference to FIGS. 41 to 45 may be replaced with the steps of providing the mask film in which the openings are arranged in the third and fifth embodiments. However, it is not suitable when there is an arc at the boundary of the opening, when the opening is circular, or when the boundary of the opening is greatly inclined (specifically, close to 45 degrees) with respect to the arrangement direction of the openings.
[0246]
(Embodiment 8)
In the third to seventh embodiments, when the gate insulating film and the gate electrode 5 are formed directly after patterning the semiconductor layer 3 (for example, FIG. 10) without providing a dummy gate, Si gate is formed on the gate sidewall._ThreeN_FourThe gate sidewall is made of SiO₂In the case where the first side wall 22 is made of only Si (as shown in FIGS. 58 and 59), the first side wall 22 is made of Si._ThreeN_FourCan be configured. At this time, Si_ThreeN_FourAgainst SiO₂The second CVD SiO using conditions that allow selective etching of₂A gate sidewall may be formed by etching the film 21. At this time, the mask film 9 on the semiconductor layer 3 is made of Si._ThreeN_FourIn the case of a film, the mask film 9 remains even after the gate sidewall is formed. If the mask film 9 is to be removed, after forming the gate sidewall,_ThreeN_FourAn RIE process having an effect of etching the substrate may be performed. Further, the mask film 9 may be left as it is.
[0247]
Further, after depositing polysilicon forming the gate electrode 5 (or an alternative conductor such as metal silicide or metal compound), Si is deposited on the polysilicon._ThreeN_FourThe film 25 is deposited, for example, 20 nm and patterned in the same shape as the gate electrode (or Si using a resist pattern)._ThreeN_FourThe film 25 is patterned and Si_ThreeN_FourAfter etching the gate electrode material using the film 25 as a mask,_ThreeN_FourThe first sidewall 26 may be provided. At this time, Si_ThreeN_FourThe lower end of the first sidewall 26 is Si_ThreeN_FourIt may be below the lower end of the film 25, may be above it, or may be substantially the same height.
[0248]
(Embodiment 9)
In the third to eighth embodiments, instead of forming a transistor on a semiconductor layer (for example, FIG. 10) patterned so as to connect the source / drain regions with a plurality of conduction paths, they are separated from each other and parallel to each other. A dummy gate insulating film (or gate insulating film) and a dummy gate electrode (or gate electrode) are formed on a conduction path made of a semiconductor layer arranged in parallel, and after forming a gate sidewall, they are separated from each other in parallel. The semiconductor layer may be selectively epitaxially grown on the side of the arranged semiconductor layers, and the epitaxially grown semiconductor layers may be joined to each other to be used in a method for manufacturing a transistor that forms a source / drain region. 66 and 67 are plan views showing the embodiment. 66 shows a form obtained when the resist in the region 42 is omitted in the manufacturing method according to FIG. 41, and FIG. 67 shows a form obtained when the resist 42 is omitted in the manufacturing process according to FIG. 66 and 67 indicate the shapes of the semiconductor layers separated from each other initially formed in the manufacturing method according to FIGS. 66 and 67. In FIG. 67, the conduction path may take two embodiments, and the effect of the invention does not change. In this case, the two conduction paths made of the semiconductor layers arranged in parallel are not separated from each other in the embodiment shown in FIGS. 66 and 67, but the wide source / drain regions are not formed. 10 differs from the embodiment of FIG. However, the procedure of the manufacturing process is exactly the same as in the case of FIGS. In the figure, symbol 22 indicates a first sidewall, and the gate sidewall is provided below the first sidewall 22 in the same shape as the first sidewall 22.
[0249]
(Embodiment 10)
The sidewall manufacturing method according to the fifth embodiment is not limited to the case where a gate electrode (or dummy gate electrode) is provided on a semiconductor layer on an insulator, but a gate electrode provided on an uneven semiconductor region on a bulk substrate. (Or a dummy gate electrode) may be used when a gate sidewall is provided.
[0250]
Further, a field effect transistor provided over a semiconductor layer over an insulator may be used for a form in which a semiconductor layer remains below a gate electrode (or a dummy gate electrode).
[0251]
Further, in any of the modes in which the semiconductor layer remains below the gate electrode in the field effect transistor provided on the semiconductor region with unevenness on the bulk substrate and on the semiconductor layer on the insulator, the conduction path is singular. In some cases, a plurality of cases may be used.
[0252]
Further, it may be used in the case where a sidewall is provided for a gate electrode (or a dummy gate electrode) of any field effect transistor provided on a semiconductor region having unevenness.
[0253]
71 and 72 show the case where a gate sidewall is provided on a gate electrode (or a dummy gate electrode) provided on an uneven semiconductor region on a bulk substrate, and FIGS. 73 and 74 show an insulator. Sections of the field-effect transistor provided on the semiconductor layer of FIG. 10 in which the semiconductor layer remains below the gate electrode are illustrated at positions corresponding to the A10-A10 ′ line cross section and the B10-B10 ′ line cross section of FIG. FIG. Lower SiO in the figure₂For example, after the film 28 is formed in a shape corresponding to FIG.₂It is obtained by depositing a film, planarizing the surface, and then etching back by RIE. Between the silicon substrate and the lower part of the gate electrode (including the lower part of the gate electrode embedded after removal of the dummy gate electrode) There is an effect of reducing the capacity. In the silicon substrate 1 in FIGS. 71 and 72 and the lower silicon layer 29 in FIGS. 73 and 74, a portion below the channel formation region 7 is usually 3 × 10.¹⁷cm^-3Or more, preferably 3 × 10¹⁸cm^-3An impurity having a conductivity different from that of the channel type at the above concentration is introduced.
[0254]
【The invention's effect】
As described above, according to the method of manufacturing a field effect transistor and the structure of the field effect transistor of the present invention, in the method of manufacturing a field effect transistor formed on an uneven semiconductor region, an insulating film is formed on the gate electrode. In addition, a structure in which the side surface of the uneven semiconductor region is not covered with an insulating film can be formed.
[0255]
Furthermore, according to the method for manufacturing a field effect transistor and the structure of the field effect transistor of the present invention, in the method for manufacturing a field effect transistor formed on an uneven semiconductor region, it is provided for forming a gate electrode. A side wall of the insulating film can be provided on the dummy gate electrode, and a structure in which the side surface of the uneven semiconductor region is not covered with the insulating film can be formed.
[0256]
Therefore, according to the present invention, it is particularly effective for a fine vertical field effect transistor constituting an LSI and a double gate vertical field effect transistor having gate electrodes on both sides of a semiconductor layer.
[Brief description of the drawings]
FIG. 1 is a bird's-eye view showing an embodiment of the present invention.
FIG. 2 is a plan view showing an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing an embodiment of the present invention.
FIG. 4 is a cross-sectional view showing an embodiment of the present invention.
FIG. 5 is a cross-sectional view showing an embodiment of the present invention.
FIG. 6 is a plan view showing an embodiment of the present invention.
FIG. 7 is a plan view showing an embodiment of the present invention.
FIG. 8 is a cross-sectional view showing an embodiment of the present invention.
FIG. 9 is a bird's-eye view showing an embodiment of the present invention.
FIG. 10 is a bird's-eye view showing an embodiment of the present invention.
FIG. 11 is a cross-sectional view showing an embodiment of the present invention.
FIG. 12 is a cross-sectional view showing an embodiment of the present invention.
FIG. 13 is a cross-sectional view showing an embodiment of the present invention.
FIG. 14 is a cross-sectional view showing an embodiment of the present invention.
FIG. 15 is a plan view showing an embodiment of the present invention.
FIG. 16 is a cross-sectional view showing an embodiment of the present invention.
FIG. 17 is a cross-sectional view showing an embodiment of the present invention.
FIG. 18 is a cross-sectional view showing an embodiment of the present invention.
FIG. 19 is a cross-sectional view showing an embodiment of the present invention.
FIG. 20 is a cross-sectional view showing an embodiment of the present invention.
FIG. 21 is a cross-sectional view showing an embodiment of the present invention.
FIG. 22 is a cross-sectional view showing an embodiment of the present invention.
FIG. 23 is a cross-sectional view showing an embodiment of the present invention.
FIG. 24 is a cross-sectional view showing an embodiment of the present invention.
FIG. 25 is a cross-sectional view showing an embodiment of the present invention.
FIG. 26 is a cross-sectional view showing an embodiment of the present invention.
FIG. 27 is a plan view showing an embodiment of the present invention.
FIG. 28 is a plan view showing an embodiment of the present invention.
FIG. 29 is a plan view showing an embodiment of the present invention.
FIG. 30 is a plan view showing an embodiment of the present invention.
FIG. 31 is a plan view showing an embodiment of the present invention.
FIG. 32 is a plan view showing an embodiment of the present invention.
FIG. 33 is a plan view showing an embodiment of the present invention.
FIG. 34 is a plan view showing an embodiment of the present invention.
FIG. 35 is a plan view showing an embodiment of the present invention.
FIG. 36 is a cross-sectional view showing an embodiment of the present invention.
FIG. 37 is a cross-sectional view showing an embodiment of the present invention.
FIG. 38 is a cross-sectional view showing an embodiment of the present invention.
FIG. 39 is a bird's eye view showing an embodiment of the present invention.
FIG. 40 is a plan view showing an embodiment of the present invention.
FIG. 41 is a plan view showing an embodiment of the present invention.
FIG. 42 is a plan view showing an embodiment of the present invention.
FIG. 43 is a plan view showing an embodiment of the present invention.
FIG. 44 is a plan view showing an embodiment of the present invention.
FIG. 45 is a plan view showing an embodiment of the present invention.
FIG. 46 is a plan view showing an embodiment of the present invention.
FIG. 47 is a plan view showing an embodiment of the present invention.
FIG. 48 is a bird's eye view showing an embodiment of the present invention.
FIG. 49 is a bird's eye view showing an embodiment of the present invention.
FIG. 50 is a bird's eye view for explaining a conventional technique.
FIG. 51 is a plan view for explaining an effect of the production method of the present invention.
FIG. 52 is a plan view showing a conventional element structure.
FIG. 53 is a cross-sectional view for explaining an element structure of the present invention.
FIG. 54 is a plan view for explaining the effect of the present invention.
FIG. 55 is a plan view for explaining the effect of the present invention.
FIG. 56 is a cross-sectional view illustrating the effect of the present invention.
FIG. 57 is a cross-sectional view illustrating the effect of the present invention.
FIG. 58 is a cross-sectional view showing an embodiment of the present invention.
FIG. 59 is a cross-sectional view showing an embodiment of the present invention.
FIG. 60 is a cross-sectional view showing an embodiment of the present invention.
FIG. 61 is a cross-sectional view showing an embodiment of the present invention.
FIG. 62 is a cross-sectional view showing an embodiment of the present invention.
FIG. 63 is a cross-sectional view showing an embodiment of the present invention.
FIG. 64 is a cross-sectional view showing an embodiment of the present invention.
FIG. 65 is a cross-sectional view showing an embodiment of the present invention.
FIG. 66 is a plan view showing an embodiment of the present invention.
FIG. 67 is a plan view showing an embodiment of the present invention.
FIG. 68 is a cross-sectional view showing an embodiment of the present invention.
FIG. 69 is a bird's eye view showing an embodiment of the present invention.
FIG. 70 is a plan view showing an embodiment of the present invention.
FIG. 71 is a cross-sectional view showing an embodiment of the present invention.
FIG. 72 is a cross-sectional view showing an embodiment of the present invention.
FIG. 73 is a cross-sectional view showing an embodiment of the present invention.
FIG. 74 is a cross-sectional view showing an embodiment of the present invention.
FIG. 75 is a cross-sectional view showing an embodiment of the present invention.
[Explanation of symbols]
1 Silicon substrate
2 Buried insulation layer
3 Semiconductor layer
4 Source / drain regions
5 Gate electrode
6 Gate insulation film
7 Channel formation region
8 Pad oxide film
9 Si_ThreeN_Fourfilm
10 opening
11 Dummy gate electrode
12 PSG membrane
13 Interlayer insulation film
14 Gate insulation film
15 element area
16 Source / drain contact
17 Gate contact
18 Dummy gate insulating film
19 Opening area
20 Second Si_ThreeN_Fourfilm
21 Second SiO₂film
22 First sidewall
23 Interlayer insulation film
24 metal wiring
25 Si on gate_ThreeN_Fourfilm
26 Si_ThreeN_FourFirst side wall
27 Initially formed semiconductor layer
28 Lower CVDSiO₂film
29 Lower silicon layer
31 Conduction path placement region
32 Source / drain connection
33 Conduction path
34 Aperture array area
35 One conduction path
36 Gate side-source / drain side capacitance
41 Second mask material
42 Range of resist pattern (formation area)
43 Dummy pattern for second mask formation
44 Resist pattern range (formation area)
101 Semiconductor substrate
102 Insulator
103 Semiconductor layer
104 Gate insulation film
105 Gate electrode

Claims (7)

A dummy gate electrode is provided on a semiconductor region having a protruding shape, the dummy gate electrode is embedded in an insulator, and the upper portion of the insulator covering the dummy gate electrode is removed by etching, and the upper portion of the dummy gate electrode is removed. Etching back the insulator covering the dummy gate electrode using the dummy gate electrode and the first side wall as a mask by providing a first side wall on both sides of the exposed dummy gate electrode. wherein the step of the lower portion of the first side wall forming a gate sidewall made of an insulating material on a side surface of the dummy gate electrode, the portion that is not also covered by any of the dummy gate electrode and the gate sidewalls, the dummy gate electrode on both sides of the semiconductor region, a step of providing a source / drain region by introducing a first conductivity type impurity at a high concentration, the dummy gate Method for producing a field-effect transistor which comprises a step of forming a gate electrode buried conductive material in the gap formed by removing a pole. 2. The method of manufacturing a field effect transistor according to claim 1 , wherein the first sidewall is polysilicon. _{2. The} method of manufacturing a field effect transistor according to claim 1 , wherein the gate side wall is made of SiO2. Method for producing a field effect transistor according to claim 1, wherein the gate sidewall is Si ₃ N _4. Among the gate sidewalls, the material of the portion contacting the gate electrode or the dummy gate electrode is a Si ₃ N _4, the outer layer made of Si ₃ N ₄ is as defined in claim 1, characterized in that the SiO ₂ A method of manufacturing a field effect transistor. Method for producing a field effect transistor according to claim 1, wherein the first side wall is Si ₃ N _4. It said first sidewall is Si ₃ N _4, a method of manufacturing a field effect transistor according to claim 1, wherein the gate sidewall is characterized by a SiO _2.

Images