JP3605086B2 - Field effect transistor - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a field effect transistor.
[0002]
[Prior art]
Currently, the performance of ultra-high-speed MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) has been improved by reducing the size of devices represented by the gate length (Lg).
[0003]
However, when the gate length is extremely short, even when the gate is closed, a short channel effect occurs in which electric charges leak due to a potential difference between the source region and the drain region. As a result, there is a problem that the switching operation cannot be performed in the field effect transistor.
[0004]
In order to suppress the short channel effect, a field effect transistor having a double gate structure in which a gate voltage is applied from both sides of a channel surface has been proposed.
[0005]
In the field effect transistor having the double gate structure, since the channel surface is sandwiched between the gate electrodes arranged at extremely small plane intervals, a sufficient voltage can be applied to the channel region, so that the leakage of electric charges is suppressed even in the gate closed state.
[0006]
However, the field effect transistor having the double gate structure has a problem that the amount of current flowing in the gate open state is small and the driving force is small since the thickness of the channel region is also small because the gate interval is extremely narrow.
[0007]
[Problems to be solved by the invention]
As described above, the conventional double-gate field-effect transistor has a problem that the short-channel effect is suppressed but the driving force is small.
[0008]
The present invention has been made in view of such a problem, and an object of the present invention is to provide a field effect transistor capable of suppressing a short channel effect and improving a driving force.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, the present invention has a source region and a drain region, and between the source region and the drain region, a base having an opposing main surface,
A pair of gate electrodes provided on the main surface,
A distance between the pair of gate electrodes is larger on the source region side than on the drain region side.
[0010]
At this time, it is preferable that the base is formed of a semiconductor.
[0011]
Further, it is preferable that an interval between the pair of gate electrodes is gradually reduced from the source region side to the drain region side.
[0012]
In addition, it is preferable that a plurality of the field effect transistors are arranged in a ring shape such that the source region is located outside and the drain region is located inside .
[0013]
Further, the plurality of field effect transistors include a mixture of p-type and n-type, and it is preferable that p-type is more than n-type.
[0014]
Further, it is preferable that a drain electrode is provided at a central portion, and drain regions of the plurality of field effect transistors are arranged around the drain electrode.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiments, and various selections can be made.
[0016]
(Embodiment 1)
FIG. 1 is a perspective view of a field-effect transistor according to Embodiment 1 of the present invention.
[0017]
As shown in FIG. 1, a wedge-shaped base 2 is formed on a silicon substrate 1. The base 2 is formed of a semiconductor such as silicon. Further, a channel region is formed in the base 2.
[0018]
The base 2 has a pair of opposed channel surfaces, and a pair of gate electrodes 3 and 4 are formed on the channel surfaces, respectively. A gate insulating film (not shown) is formed on the channel surface and between the gate electrodes 3 and 4, respectively.
[0019]
A source region 5 and a drain region 6 are formed so as to be separated from each other so as to sandwich the base 2. The source region 5 and the drain region 6 are formed at positions sandwiching the channel region in the direction in which the channel region extends. The source region 5 and the drain region 6 are formed of a semiconductor such as silicon and are doped with impurities.
[0020]
The base 2 is a wall-shaped projection formed so as to protrude from the silicon substrate 1, and has a wedge shape in which the width on the source region 5 side is wider than the width on the drain region 6 side. That is, the interval W1 between the pair of gate electrodes 3 and 4 on the source region 5 side is larger than the interval W2 on the drain region 6 side. The distance between the pair of gate electrodes 3 and 4 gradually decreases from the source region 5 side to the drain region 6 side.
[0021]
The specific dimensions of the base 2 are such that the width of the portion in contact with the source region 5 is 10 nm and the width of the portion in contact with the drain region 6 is 6 nm. These widths substantially coincide with the distance W1 between the pair of gate electrodes 3 and 4 on the source region 5 side and the distance W2 on the drain region 6 side minus the thickness of the gate insulating film (not shown). The height Lw of the base 2 is 20 nm. The length of the channel region, here, the distance Lg from the portion in contact with the source region 5 to the portion in contact with the drain region 6 is 30 nm.
[0022]
The width of the source region 5 and the drain region 6 may be the same as the width of a portion that is in contact with the channel region. However, the width of the drain region 6 may be increased to reduce the resistance.
[0023]
Next, the relationship between the gate voltage and the drain current was obtained by simulation for a field-effect transistor in which the distance between the gate electrodes is gradually reduced from the source region to the drain region, and for a field-effect transistor in which the distance between the gate electrodes is constant. Is shown.
[0024]
As shown in FIG. 2, (1) a source region (impurity concentration of 1 × 10 ²⁰ cm ⁻³ ), a channel region (impurity concentration of 1 × 10 ¹⁵ cm ⁻³ ), and a drain region (impurity concentration of 1 × 10 ²⁰ cm ^−3). ) Is 5 nm in width, and the width of the channel region (impurity concentration 1 × 10 ¹⁵ cm ⁻³ ) on the side of the source region (impurity concentration 1 × 10 ²⁰ cm ⁻³ ) is 5 nm. A simulation was performed on a field effect transistor having a double gate structure in which the width of the channel region on the side of the drain region (impurity concentration: 1 × 10 ²⁰ cm ⁻³ ) was 1.67 nm, at 3.34 nm. The gate lengths are both 20 nm.
[0025]
FIG. 3 is a characteristic diagram showing a relationship between a gate voltage and a drain current.
[0026]
As shown in FIG. 3, in the structure having a wide source side shown in (2), a characteristic in which the drain current is smaller in the region having a low gate voltage of 0.2 V or less than that of the normal structure shown in (1) is obtained. ing. That is, it is understood that the short channel effect in the closed state of the field effect transistor is suppressed.
[0027]
Also, in the structure having a wide source side shown in (2), the drain current amount is high in the region where the gate voltage is higher than 0.4 V as in the normal structure shown in (1). This suggests that the driving force can be improved.
[0028]
Thus, it can be said that the structure according to the present embodiment can suppress the short channel effect when the gate is closed, and sufficiently secure the drive current amount when the gate is open.
[0029]
As a comparison, when the channel width of (1) is reduced to about (2), the gate is closed and the short channel effect can be suppressed, but the driving current is smaller than that of (2). Expected to be very low.
[0030]
Next, a method for manufacturing the field-effect transistor according to the present embodiment will be described with reference to FIGS.
[0031]
The field-effect transistor according to the present embodiment uses, for example, a substrate in which an SOI (Silicon On Insulator) layer is laminated on a buried oxide film, forms a thermal oxide film mask on the substrate surface, and performs dry etching. Create a wedge-shaped projection. Next, thermal oxidation is performed at a high temperature to recover the surface of the projection damaged by the dry etching.
[0032]
In the course of this high-temperature thermal oxidation, the size of the protrusion becomes smaller. Thereafter, the oxide film mask on the surface is removed, and after the surface treatment is performed, the gate processing and the processing of the source region and the drain region are performed to complete the field effect transistor.
[0033]
There are two types of manufacturing methods given as examples this time. One is to perform gate processing and then process the source and drain regions. The other is to process the source region and the drain region first, and then perform the gate process.
[0034]
First, an example of a manufacturing method in which gate processing is performed first will be described.
[0035]
Here, a substrate in which a 100-nm-thick SOI layer is stacked over a 100-nm-thick buried oxide film is used. The thickness of the buried oxide film is not significantly restricted from the process. However, since a process of selectively etching the silicon layer on the buried oxide film using the difference in etching rate from the buried oxide film is used, if the thickness of the buried oxide film is several nm or less, attention must be paid to the process. Required.
[0036]
The thickness of the SOI layer is required to be greater than the height of the finally formed protrusion. Since the height of the projection is a value that determines the height Lw (FIG. 1) of the channel region, 50 nm or more is required. Although there is little restriction on the maximum value in terms of element design, the process is difficult if the height of the projection or the height ratio to the bottom surface (aspect ratio) is large, so that the maximum value is preferably 1 μm or less.
[0037]
First, as shown in FIG. 4, an SOI substrate having a laminated structure of a silicon substrate 10, a buried oxide film 11, and an SOI layer 12 is prepared.
[0038]
4, (a) is a top view, (b) is an AA sectional view, and (c) is a BB sectional view. The same applies to FIGS. 5 to 10 below.
[0039]
As shown in FIG. 4, an SiN layer 13 is formed on the SOI layer 12 of the SOI substrate, and a resist pattern 14 having a length of 2 μm and a width of 20 nm to 40 nm is formed.
[0040]
Next, as shown in FIG. 5, the wedge-shaped SiN mask 13 is formed by etching using the resist pattern 14 (FIG. 4) as a mask. Next, wedge-shaped silicon projections 12 are formed by etching using the SiN mask 13 as a mask. At this time, the buried oxide film 11 is exposed.
[0041]
In the silicon projection, a channel region and a source region and a drain region are formed later so as to sandwich the channel region. It is desirable that the side surface of the silicon protrusion 12 faces the (010) plane or the (100) plane. Further, the (110) plane or a plane equivalent thereto may be used. With these planes, the mobility of charges can be increased.
[0042]
Next, as shown in FIG. 6, a thermal oxidation process is performed with the SiN mask 13 left. By doing so, it is possible to remove the damaged layer of the dry etching. At this time, the oxidation of the upper surface covered with the SiN mask 13 does not progress, but the side without the cover is oxidized, and the width of the silicon protrusion 12 is reduced. When the side surface of the silicon protrusion 12 is oxidized by 5 nm, the width is reduced by 5 nm on one side and 10 nm on both sides, and becomes a wedge shape of 10 nm to 30 nm.
[0043]
Next, the SiN mask 13 is removed, the silicon projection 12 is exposed, and after performing a pretreatment, the surface of the silicon projection 12 is thermally oxidized. At this time, the thickness of the oxide film is 4 nm. As a result, the width of the silicon protrusion 12 becomes 8 nm to 28 nm.
[0044]
Next, as shown in FIG. 7, polycrystalline silicon 15 having a thickness of 200 nm is deposited on the entire surface. At this time, a high concentration of phosphorus is added to the polycrystalline silicon 15. Phosphorus may be added by a method of simultaneously adding impurities to the polycrystalline silicon 15 at the time of deposition by CVD or the like, or by a method of introducing ions by ion implantation. In the figure, reference numeral 16 denotes a silicon oxide film.
[0045]
Next, as shown in FIG. 8, the gate of the polycrystalline silicon 15 is processed. At this time, extension ions can be implanted into the silicon protrusions 12 using the resist used as a mask in the gate processing.
[0046]
Next, as shown in FIG. 9, a sidewall insulating film 17 is formed by performing sidewall processing. Here, after depositing a SiO ₂ layer by the CVD method, the sidewall insulating film 17 is formed by leaving the SiO ₂ only on the side wall by selective etching. At this time, since the height of the polycrystalline silicon layer 15 and the height of the silicon protrusion 12 are different, if the condition of the selective etching is set so that the oxide remains only on the side surface of the polycrystalline silicon 15, the SiO _{2 on the} side wall of the silicon protrusion 12 becomes Completely removed. As a result, only the gate has a sidewall remaining, and the strained Si layer is exposed on the side and top surfaces of the fin.
[0047]
Next, as shown in FIG. 10, a source region 18 and a drain region 19 are formed by selective growth of silicon. Here, a new silicon layer grows only on the silicon projection 12 where the silicon crystal is exposed. At this time, the source region 18 and the drain region 19 can be doped with impurities by performing selective growth to which boron is added. Finally, a gate electrode, a source electrode, and a drain electrode are formed to complete a field effect transistor.
[0048]
(Embodiment 2)
Next, a field effect transistor according to Embodiment 2 of the present invention will be described. In this embodiment, an example in which a plurality of channel regions are connected to form one field-effect transistor will be described.
[0049]
FIG. 11 is a perspective view of a field-effect transistor in which three bases serving as wedge-shaped channel regions are formed side by side.
[0050]
As shown in FIG. 11, a source region and a drain region are commonly connected by wiring, and a common gate voltage is applied to a gate electrode. By forming and sharing a plurality of channel regions in this manner, the amount of drive current can be further increased.
[0051]
FIG. 12 is a top view of a field-effect transistor according to a modification of the present embodiment. Here, the channel region is arranged annularly around the drain end. A drain electrode is arranged at the center. A common gate voltage is applied to the double gate of each channel region by a gate wiring. The source region is also shared by the wiring.
[0052]
By arranging the wedge-shaped bases in a ring shape such that the drain region is on the center side, it is effective in reducing the element area.
[0053]
In a field-effect transistor, the driving force of a p-type field-effect transistor is lower than that of an n-type field-effect transistor because the mobility of holes is usually lower than that of electrons.
[0054]
Therefore, in a ring-shaped field effect transistor as shown in FIG. 13, the effective channel width may be controlled by adjusting the number of n-type field effect transistors and p-type field effect transistors. This makes it possible to correct the difference in driving force. Specifically, the number p of the p-type field effect transistors may be larger than the number n of the n-type field effect transistors.
[0055]
Next, a method for manufacturing the field-effect transistor of this embodiment will be described with reference to FIGS. The figure shows a method for manufacturing a field effect transistor having two substrates.
[0056]
First, as shown in FIG. 14, an SOI substrate having an SOI layer 12 made of SiGe formed on a buried oxide film 11 is prepared. Here, the thickness of the SOI layer 12 is 200 nm.
[0057]
14, (a) is a top view, (b) is an AA cross-sectional view, and (c) is a BB cross-sectional view. The same applies to FIGS. 15 to 20 below.
[0058]
As shown in FIG. 14, an oxide film 20 is deposited on the SOI layer 12 of the SOI substrate by a CVD method with a thickness of 10 nm, and a SiN film 21 is deposited on the oxide film 20 with a thickness of 10 nm. Next, etching is performed so that the SiN film 21 remains in portions that become the source region and the drain region, and the oxide film 20 is exposed. Further, the SOI layer 12 is exposed by etching so that the oxide film 20 remains on the base material serving as the channel region.
[0059]
At this time, the width of the oxide film 20 covering the base to be the channel region was set to 240 nm to 260 nm.
[0060]
Next, as shown in FIG. 15, the substrate 22 in the channel region is formed by dry etching using the oxide film 20 and the SiN film 21 as a mask. As a result, the base 22 of the channel region is formed between the source region 23 and the drain region 24. At this time, the mask is designed so that the side surface of the base 22 in the channel region becomes the (010) plane.
[0061]
Next, as shown in FIG. 16, an oxide film 25 is formed by performing thermal oxidation. At this time, the source region 23 and the drain region 24 whose surfaces are covered with the SiN film 21 are not oxidized, but the surface of the base 22 in the channel region not covered with the SiN film 21 is oxidized.
[0062]
That is, the base 22 in the channel region is covered with the CVD oxide film 25 on the upper side, and the thermal oxide film 26 on the side surface. By this thermal oxidation, the substrate 22 in the channel region is oxidized by about 100 nm. As a result, the base 22 in the channel region has a height of 100 nm and a width of 20 nm to 40 nm.
[0063]
Here, since the thin oxide film 20 is previously formed on the upper surface of the base 22 in the channel region, the oxidation speed of the side surface is slightly faster at the start of the oxidation.
[0064]
Next, as shown in FIG. 17, after removing the SiN film covering the source region 23 and the drain region 24, ion implantation of phosphorus is performed. At this time, ions are implanted into the source region 23 and the drain region 24, but are not implanted because the base 22 in the channel region is covered with a thick oxide film formed by thermal oxidation.
[0065]
Next, as shown in FIG. 18, after removing the oxide film on the source region 23 and the drain region 24 and on the projection base in the channel region to expose the SiGe surface, the surface of the SiGe layer is heat-treated to a thickness of 3 nm. Oxidize.
[0066]
Next, polycrystalline silicon 25 is deposited by a CVD method so as to fill gaps between the bases 22 in the channel region. Here, boron is added to the polycrystalline silicon 25. This may be a method of adding boron at the same time as the deposition by the CVD method, or a method of introducing it later by ion implantation.
[0067]
Next, as shown in FIG. 20, the polycrystalline silicon 25 is left with the width of the gate, the periphery is removed, and electrodes are formed in the source region 23, the drain region 24, and the polycrystalline portion of the gate, respectively. It is completed.
[0068]
【The invention's effect】
It is possible to improve the gate open driving force while suppressing the gate closed short channel effect.
[Brief description of the drawings]
FIG. 1 is a perspective view of a field-effect transistor according to a first embodiment of the present invention.
FIG. 2 is a diagram showing dimensions for simulation of (1) a conventional double-gate field effect transistor and (2) a double-gate field effect transistor of the present invention.
FIG. 3 is a characteristic diagram showing a relationship between a gate voltage and a drain current.
FIG. 4 is a sectional view of each main step for explaining the method for manufacturing the field-effect transistor according to the first embodiment of the present invention.
FIG. 5 is a sectional view of each main step for explaining the method for manufacturing the field-effect transistor according to the first embodiment of the present invention.
FIG. 6 is a sectional view of each main step for explaining the method for manufacturing the field-effect transistor according to the first embodiment of the present invention.
FIG. 7 is a sectional view of each main step for explaining the method for manufacturing the field-effect transistor according to the first embodiment of the present invention.
FIG. 8 is a sectional view of each main step for explaining the method for manufacturing the field effect transistor according to the first embodiment of the present invention.
FIG. 9 is a cross-sectional view of each main step for explaining the method for manufacturing the field-effect transistor according to the first embodiment of the present invention.
FIG. 10 is a sectional view of each main step for explaining the method for manufacturing the field-effect transistor according to the first embodiment of the present invention.
FIG. 11 is a perspective view of a field-effect transistor according to a second embodiment of the present invention.
FIG. 12 is a modified example of the field-effect transistor according to the second embodiment of the present invention.
FIG. 13 is a modification example of the field-effect transistor according to the second embodiment of the present invention.
FIG. 14 is a sectional view of each main step for explaining a method for manufacturing a field-effect transistor according to the second embodiment of the present invention.
FIG. 15 is a sectional view of each main step for explaining a method for manufacturing a field-effect transistor according to the second embodiment of the present invention.
FIG. 16 is a sectional view of each main step for explaining the method for manufacturing the field-effect transistor according to the second embodiment of the present invention.
FIG. 17 is a cross-sectional view of each main step for explaining the method for manufacturing the field-effect transistor according to the second embodiment of the present invention.
FIG. 18 is a sectional view of each main step for explaining a method for manufacturing a field-effect transistor according to the second embodiment of the present invention.
FIG. 19 is a sectional view of each main step for explaining the method for manufacturing the field effect transistor according to the second embodiment of the present invention.
FIG. 20 is a sectional view of each main step for explaining the method for manufacturing the field effect transistor according to the second embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Base of channel area 3 ... Gate electrode 4 ... Gate electrode 5 ... Source area 6 ... Drain area

Claims (6)

A base having a source region and a drain region, and having a main surface facing each other between the source region and the drain region;
A pair of gate electrodes provided on the main surface,
A field effect transistor wherein a distance between the pair of gate electrodes is larger on the source region side than on the drain region side. 2. The field effect transistor according to claim 1, wherein said base is formed of a semiconductor. 3. The field effect transistor according to claim 1, wherein the distance between the pair of gate electrodes is gradually reduced from the source region to the drain region. 4. The field-effect transistor according to claim 1, wherein a plurality of the field-effect transistors are annularly arranged such that the source region is located outside and the drain region is located inside. 5. The field effect transistor used. 5. The field effect transistor according to claim 4, wherein the plurality of field effect transistors include a mixture of p-type and n-type, and p-type is more than n-type. 6. The field effect transistor according to claim 4, further comprising a drain electrode at a central portion, wherein drain regions of the plurality of field effect transistors are arranged around the drain electrode.

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