JPH10335660A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with an insulated gate field effect transistor which is provided with a diffusion layer that is lessened in capacitance without using a selective growth method and decreased in size by lessening the diffuison layer in depth. SOLUTION: An element region is formed under a gate electrode 105 and demarcated with an element isolation insulating region 102 in a semiconductor substrate 101 which forms an insulated gate field effect transistor, where a space between a position at which a part of the element region where two diffusion layers 112 and 113 are formed is brought into contact with the element isolation insulating region 102 and the side of the gate electrode 105 is set smaller than the height of the gate electrode 105, the diffusion layers are each composed of an upper layer 112 and a lower layer 113, a distance between the one edge of the diffusion upper layer 112 on an gate electrode side and the other edge on an element isolation insulation region side is set larger than the height of the gate electrode 105, and the edge of the diffusion upper layer 112 on an element isolation region side is formed on the element isolation region 102.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a fine insulated gate field effect transistor and a method of manufacturing the same, and more particularly to a structure of a diffusion layer and a method of manufacturing the same.

[0002]

FIG. 4 shows a conventional basic LDD (Lig).
FIG. 4 is a schematic cross-sectional view showing a manufacturing process of an insulated gate field effect transistor having an htly doped drain (hd.drain) structure. FIG.
(B) shows a state in which a gate electrode is formed from a polysilicon film and a diffusion layer is formed, (c) shows a state in which an insulating gate side wall is formed and a high concentration diffusion layer is formed, and (d) shows an insulating state. This is a state where a film is deposited and an electrode metal is formed. In the figure, reference numeral 401 denotes a semiconductor substrate, 402 denotes an element isolation insulating region, 40
3 is a gate insulating film, 404 is a polysilicon film, 405 is a gate electrode, 406 is a diffusion layer, 407 is an insulating gate side wall, 408 is a diffusion layer, 409 is an insulating film, 410 is an electrode metal, and 414 is an N-well. .

[0003] An insulated gate field effect transistor having an LDD type structure will be described in accordance with the manufacturing process. First, as shown in FIG. An element isolation insulating region 402 is formed by a LOCOS method or a trench isolation method, and a gate insulating film 403 and a polysilicon film 404 for a gate electrode having an appropriate thickness are grown on the element region thus partitioned. Next, as shown in FIG. 4B, the polysilicon film 404 is etched into a required shape by lithography to form a gate electrode 405, and the substrate 4 is formed using the gate electrode 405 as a mask.
By implanting an impurity of the second conductivity type different from 01 by an ion implantation method, a diffusion layer 406 composed of a lightly doped shallow source and drain is formed in the element region in a self-aligned manner.

[0004] Next, as shown in FIG.
After an insulating film is deposited on the entire upper surface by a chemical vapor deposition method, an insulating gate side wall 407 is formed on the side surface of the gate electrode 405 by anisotropic etching. Further, by using the gate electrode 405 and the insulating gate side wall 407 as a mask, an impurity of the second conductivity type is implanted by an ion implantation method, so that a diffusion layer 408 having both a high-concentration deep source and a drain in a self-aligned manner. Is formed in the element region. The deep diffusion layer 408 has a function of reducing the resistance of the diffusion layer and preventing the contact hole from penetrating the diffusion layer when the contact hole is opened.

Next, as shown in FIG. 4D, after an insulating film 409 is deposited by a chemical vapor deposition method, a contact hole is opened on a deep diffusion layer 408 by a lithography technique, and an electrode is formed by a sputtering method. By depositing a metal to be a metal and forming an electrode metal 410 by lithography, an insulated gate field effect transistor having an LDD type structure has been manufactured.

FIG. 5 is a schematic cross-sectional view showing a manufacturing process of a conventional insulated gate field-effect transistor having a diffusion layer partially on the element isolation insulating region, and FIG.
Is a state where an element isolation region, an oxide film, and a polysilicon film are grown on a semiconductor substrate, and the polysilicon film is etched.
(B) shows a state where an oxide film is removed and a silicon selective growth film is deposited, (c) shows a state where a gate insulating film, a gate electrode, an insulating gate side wall and a diffusion layer are formed, and (d) shows an insulating film. Is deposited to form an electrode metal. In the figure, reference numeral 501 denotes a semiconductor substrate, 502 denotes an element isolation insulating region, 50
3 is a gate insulating film, 505 is a gate electrode, 507 is an insulating gate side wall, 508 is a diffusion layer, 509 is an insulating film, 51
0 is an electrode metal, 514 is an N well, 517 is a polysilicon film, 518 is an oxide film, and 519 is a silicon selective growth film.

This insulated gate field effect transistor will be described in accordance with the manufacturing process. First, FIG.
As shown in (a), an element isolation insulating region 502 is formed on a semiconductor substrate 501 of a first conductivity type in the same manner as the insulated gate field effect transistor having the above-described LDD structure.
Next, a well 514 is formed. If the substrate 501 is described as silicon, the surface of the substrate 501 is further oxidized by a thermal oxidation method to grow an oxide film 518, and then a polysilicon film having an appropriate thickness is deposited by a chemical vapor deposition method. Next, the polysilicon film is etched by lithography technique only leaving an appropriate width only on the element isolation insulating film, and then the polysilicon film 51 to be a diffusion layer is formed.
7 is formed. Further, as shown in FIG. 5B, the oxide film 518 on the element region is removed by wet etching, and silicon is selectively grown only on the polysilicon film 517 and the element region by selective chemical vapor deposition. The film 519 is deposited. Next, as shown in FIG.
After a gate insulating film 503, a gate electrode 505, and an insulating gate side wall 507 are formed on the silicon selective growth film 519 in the same manner as in the above-described insulated gate field effect transistor having the LDD type structure, the first is performed by ion implantation. A second conductivity type impurity different from that of the conductivity type substrate 501 is implanted to form a diffusion layer 508 in the element region. Further, FIG.
As shown in (d), after depositing an insulating film 509 by a chemical vapor deposition method, a polysilicon film 5 disposed on an element isolation insulating region 502 by a lithography technique.
After opening a contact hole on the electrode 17, all electrodes 5
By forming No. 10, an insulated gate type field effect transistor having a diffusion layer that partially runs on the element isolation insulating region has been manufactured.

FIG. 6 is a schematic sectional view of a conventional insulated gate transistor having a diffusion layer having a structure rising upward from the surface of a semiconductor substrate. In the figure, reference numeral 601 denotes a semiconductor substrate, 602 denotes an element isolation insulating region, 605 denotes a gate electrode, 606 denotes a diffusion layer, 609 denotes an insulating film, 610 denotes an electrode metal, 611 denotes an insulating film, 614 denotes an N well, and 619 denotes silicon selective growth. It is a membrane.

This insulated gate transistor is
First, as shown in FIG. 6, a gate electrode 605 is formed in the same manner as in a conventional insulated gate field effect transistor having a basic LDD structure, and then an ion A diffusion layer 606 is formed by injecting a second conductivity type impurity different from the first conductivity type semiconductor substrate 601 shallowly by an implantation method. Then
After the insulating film 611 is formed so as to cover the gate electrode 605 so that the gate electrode 605 is not exposed, when the substrate 601 is silicon, only the diffusion layer 606 is formed by selective chemical vapor deposition. Silicon selective growth film 619
Is deposited. Next, the second conductivity type impurity is implanted into the silicon selective growth film 619 only at a high concentration by ion implantation to reduce the resistance. In this way, the substrate 60
There is no need to provide a deep diffusion layer within 1. Then, similarly to the conventional insulated gate field effect transistor having the basic LDD structure, the insulating film 60 is formed by chemical vapor deposition.
9 is deposited, a contact hole is opened on the silicon selective growth film 619 by lithography technology, and an electrode metal 610 is formed, thereby forming an insulated gate type having a diffusion layer having a structure rising upward from the surface of the semiconductor substrate. Transistors were manufactured.

[0010]

The first problem of the conventional insulated gate transistor shown in FIG. 4 is that the junction capacitance of the diffusion layer is increased, and the delay time is increased. There are two main reasons for increasing the junction capacitance.

The first factor is that when a contact hole is formed on the diffusion layer by lithography to connect the diffusion layer and an external electrode, the diffusion layer is formed by adding a matching margin to the diameter of the contact hole. That is, it is necessary to increase the distance between the end on the gate electrode side and the end on the opposite side. As a result, the area of the diffusion layer in contact with the substrate increases, and the junction capacitance increases.

The second factor is that it is necessary to provide a deep diffusion layer in the element region so that the resistance of the diffusion layer is reduced and a contact hole does not penetrate the diffusion layer.
As a result, the peripheral component of the junction capacitance of the diffusion layer increases due to the deep diffusion layer, and the junction capacitance increases.

To solve the first factor, FIG.
However, a transistor having a diffusion layer partially on the element isolation insulating region as shown in (1) has been proposed, but a selective growth step is required to form the diffusion layer, so that the stability of the manufacturing process is poor. There is a problem that.

Further, the second factor can be solved by not forming a deep diffusion layer in a substrate by using a transistor having a diffusion layer having a structure rising upward from the surface of a semiconductor substrate as shown in FIG. Can be. However, in this case, since the contact hole is formed on the diffusion layer, there is a problem that the area of the diffusion layer is increased as in the case of the above-described transistor having a commonly used structure. Further, similarly to the above-described transistor having the diffusion layer partially climbing over the element isolation insulating region, a selective growth step is required to form the diffusion layer, so that the stability of the manufacturing process is poor. is there.

The second problem is derived from the second factor described above. If a deep diffusion layer is formed in a substrate to solve the problem, the gate length becomes short, and as a result, the so-called short length is obtained. Since a channel effect is likely to occur, it is necessary to secure a certain gate length, which makes it difficult to reduce the size of the transistor.

To solve this problem, a transistor having an LDD structure has been proposed. However, in order to prevent a short channel effect in the LDD structure, a gate electrode and a diffusion layer in a shallow diffusion layer having a relatively low impurity concentration are used. Since it is necessary to increase the width in the direction in which the layers are arranged side by side and separate the deep diffusion layer from the gate electrode, there is a problem that the resistance of the diffusion layer increases and the area of the diffusion layer also increases. .

Similarly, to solve the second problem, there has been proposed a transistor having a diffusion layer having a structure rising upward from the surface of the semiconductor substrate. The transistor having this structure has also been described above. As described above, since a selective growth step is required to form a diffusion layer, there is a problem that the stability of the manufacturing process is poor.

An object of the present invention is to provide a semiconductor device having an insulated gate field effect transistor in which the diffusion layer capacitance is reduced by a simple method without using selective growth, and a method of manufacturing the same.

It is another object of the present invention to provide a semiconductor device having an insulated gate type field effect transistor which is reduced in size by making the diffusion layer shallow, and a method of manufacturing the same.

[0020]

According to the present invention, there is provided a semiconductor device comprising:
A gate electrode provided on a semiconductor substrate of the first conductivity type via a gate insulating film and having an insulating side wall; and a gate electrode formed on the semiconductor substrate at an interval around the gate electrode, each of which is different from the substrate. A semiconductor device having an insulated gate type field effect transistor having a diffusion layer forming a source and a diffusion layer forming a drain of two conductivity type and controlling a current flowing between two kinds of diffusion layers by a gate electrode. Thus, in an element region formed by being divided by an element isolation insulating region below a gate electrode in a semiconductor substrate forming an insulated gate field effect transistor, a portion of the element region where two types of diffusion layers are formed is formed. The distance between the position in contact with the element isolation insulating region and the side surface of the gate electrode is
The height is equal to or less than the height of the gate electrode, and the two types of diffusion layers are both formed of an upper layer and a lower layer. The end portion on the element isolation region side, which is higher than the electrode height, is formed on the element isolation region.

The upper layer of the diffusion layer may be formed of polysilicon or metal.

According to the method of manufacturing a semiconductor device of the present invention, in a process of manufacturing an insulated gate field effect transistor formed in a semiconductor device, an element is provided in a first conductivity type semiconductor substrate constituting the insulated gate field effect transistor. An element isolation insulating region formed surrounding the region, a position in contact with the element region on the side where the diffusion layer of the element isolation isolation region is formed,
A step of forming a gap between the side surface of the gate electrode formed in the element region and a height of the gate electrode or less, a step of forming a well region in the element region, and a step of forming a gate oxide film on the element region. Forming, forming a gate electrode on the gate oxide film, and implanting an impurity of a second conductivity type different from the first conductivity type by an ion implantation method using the gate electrode as a mask, thereby forming the vicinity of the surface of the element region. Forming an oxide film on the gate insulating film by chemical vapor deposition, and removing unnecessary portions of the oxide film and the gate oxide film by anisotropic etching to form a gate. Forming an insulative gate sidewall in a self-aligned manner on the side surface of the electrode; and forming an upper layer of a diffusion layer made of a conductive film between an end of the upper layer of the diffusion layer on the gate electrode side and an end of the upper layer on the element isolation insulating region side. The distance is Not less than the the steps of the end portion of the isolation region side is formed to be located on the isolation region,
Forming an interlayer film by depositing an insulating film, and forming a contact hole in the interlayer film, and forming an electrode metal in the contact hole such that at least a part of the tip is connected to the upper layer of the diffusion layer. .

In the step of forming the upper layer of the diffusion layer made of a conductive film, a semiconductor film is deposited over the entire surface, the unnecessary portion of the semiconductor film is removed by anisotropic etching, and the semiconductor film contacts the insulating gate side wall. A step of forming an upper layer of the diffusion layer in a consistent manner and implanting a second conductive type impurity at a high concentration by ion implantation into the upper layer of the diffusion layer. Forming a diffusion layer upper layer in a self-aligned manner in contact with the insulating gate side wall by removing the unnecessary portion of the semiconductor film, and forming a silicide film on the diffusion layer upper layer. May be deposited over the entire surface, an unnecessary portion of the metal film is removed by anisotropic etching, and the upper layer of the diffusion layer is formed in self-alignment with the side wall of the insulating gate.

The method for depositing a semiconductor film or metal for forming the upper layer of the diffusion layer may be a chemical vapor deposition method.
The sputtering method may be used.

The semiconductor film may be a polysilicon film.

In the semiconductor device according to the present invention, the distance from the position of the element region where the diffusion layer is formed in contact with the element isolation protection region to the outside of the gate electrode can be made as short as the height of the gate electrode or less. . Therefore, the junction capacitance of the diffusion layer, which is originally unnecessary, can be reduced, and the performance of the semiconductor device can be improved.

By depositing a semiconductor film and subsequently anisotropically etching the semiconductor film, the diffusion layer disposed on the side of the gate side wall through the insulating gate side wall can be insulated without using a lithography technique. Can be formed in a self-aligned manner with respect to the side wall of the conductive gate. Further, the distance from the end on the gate electrode side to the opposite end of the diffusion layer can be easily controlled by the thickness of the semiconductor film deposited on the gate electrode.

Since the end of the diffusion layer opposite to the end on the gate electrode side is formed so as to ride on the element isolation insulating region,
When opening contact holes for connecting diffusion layers and external electrodes on the diffusion layer using lithography technology, the alignment margin of lithography technology is increased by the extent that the diffusion layer runs over the element isolation insulating film. can do. At this time, the contact hole may be opened over both the element isolation insulating film and the diffusion layer, in which case the alignment margin can be further increased.

A diffusion layer containing high-concentration impurities is formed on the surface of the semiconductor substrate, and is connected to a shallow diffusion layer provided in the same substrate, called a low-concentration source / drain diffusion layer (LDD), on the surface of the substrate. To have been
The semiconductor device of the present invention does not have a deep diffusion layer containing a high concentration of impurities in a substrate. Therefore, the above-described short channel effect due to the deep diffusion layer can be prevented.

[0030]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the first embodiment of the present invention.
1 is a schematic cross-sectional view of an insulated gate field effect transistor according to an embodiment of the present invention.
2 is an element isolation insulating region, 103 is a gate insulating film, 105
Is a gate electrode, 107 is an insulating gate side wall, 109 is an insulating film, 110 is an electrode metal, 111 is an insulating film, 112 is a diffusion layer upper layer, 113 is a diffusion layer lower layer, and 114 is an N well.

Here, as a means for eliminating the above-mentioned factor of increasing the diffusion layer area and the above-described factor of providing the diffusion layer deep from the substrate surface, the diffusion layer is self-aligned with the insulating gate side wall 107. Then, a source / drain diffusion layer of a second conductivity type different from the substrate 101 of the first conductivity type is formed, and a part of the source / drain diffusion layer opposite to the end on the side of the gate electrode 105 is element isolation insulating. This is achieved by comprising two layers, a diffusion layer upper layer 112 provided on the region 102 and a diffusion layer lower layer 113 provided in the substrate 101.

This feature will be described below according to the device forming process. LOCOS on the semiconductor substrate 101
The element regions are divided by forming the element isolation insulating regions 102 by a method or a trench isolation method. At this time, the width of the element region in the direction in which the gate electrode 105 and the diffusion layer are arranged side by side is equal to the sum of the width of the gate electrode 105 and twice the height of the gate electrode 105 in the same direction. Or narrower, so that the diffusion layer area is smaller. With this configuration, when the gate electrode 105 is formed in the center of the element region, the width of the diffusion layers on both sides of the gate electrode 105 is equal to or smaller than the height of the gate electrode 105. In the formation of the side wall by the chemical vapor deposition method and the anisotropic etching, the width of the side wall
If the height is equal to or less than the height, it can be easily formed. When the diffusion layer upper layer 112 having the same width as the height of the gate electrode 105 which is self-aligned with the insulating gate side wall 107 is formed by the chemical vapor deposition method and anisotropic etching, the devices on both sides of the gate electrode are formed. The width of the region is the gate electrode 10
5, a part of the end of the diffusion layer upper layer 112 opposite to the end on the gate electrode side is partially separated from the element isolation insulating region 102.
Riding up and placed. For example, the width of the gate electrode 105 is 100 nm, and the height of the gate electrode is 150 nm.
nm, the width of the element region is (100 nm + 2 × 15
0 nm) and about 250 to 400 nm. Next, after a gate insulating film 103 having an appropriate thickness, a semiconductor film for a gate electrode, and an insulating film 111 having an appropriate thickness are grown on the element region, the insulating film 111 and the semiconductor film are formed into a desired shape by lithography. To the gate electrode 105 and the insulating film 1 covering the upper part of the gate electrode 105.
11 is formed. By using the gate electrode 105 as a mask, a second conductivity type impurity different from that of the substrate 101 is implanted by an ion implantation method, so that a low-concentration shallow source / drain diffusion layer below the gate electrode 105 is self-aligned. 113 is formed. At this time, the second
The impurity concentration of the conductivity type is about 10 ¹⁸ to 10 ²⁰ cm ⁻³ , and the depth of the diffusion layer 113 from the surface of the substrate 101 is 50 to
About 100 nm is desirable. Next, an insulating gate side wall 107 is formed, and the side surface of the gate electrode 105 is covered with an insulating film. At this time, if the width of the insulating gate side wall 107 is small, the width between the gate electrode 105 and the diffusion layer upper layer 112 is small. Is increased, the parasitic resistance of the diffusion layer upper layer 112 increases when the width is large. Next, a semiconductor film having a thickness approximately equal to the height of the gate electrode 105 is deposited by a chemical vapor deposition method, and a diffusion layer upper layer 112 is formed in a self-aligned manner on the side surface of the insulating gate side wall 107 by anisotropic etching. I do. Since the thickness of this semiconductor film was almost equal to the height of the gate electrode 105,
The width of the diffusion layer upper layer 112 in the direction in which the gate electrode 105 and the diffusion layer upper layer 112 are arranged side by side is substantially equal to the gate height, and the element isolation protection region in the element region where the diffusion layer upper layer 112 is formed above. Since the distance between the contact position and the outer surface of the side wall of the insulating gate is smaller than the gate height, the end of the diffusion layer upper layer 112 opposite to the gate electrode side is formed on the element isolation insulating region 102. Next, a second conductivity type impurity is implanted into the diffusion layer upper layer 112 at a high concentration by an ion implantation method. At this time, in order to sufficiently lower the resistance of the diffusion layer upper layer 112, the impurity concentration of the second conductivity type is desirably about 10 ²⁰ to 10 ²² cm ⁻³ . At this time, an impurity of the second conductivity type may be poured into the gate electrode 105 at the same time. Since the upper diffusion layer 112 and the lower diffusion layer 113 are both semiconductors of the same conductivity type, they are easily connected with low resistance. Thereafter, in the upper diffusion layer 112 surrounding the periphery of the gate electrode 105, the side surfaces at both ends of the gate electrode 105 in a direction orthogonal to the direction in which the gate electrode 105 and the diffusion layer upper layer 112 are arranged side by side are covered. Is removed by a lithography technique, and the upper diffusion layer 112 composed of the source and the drain on both sides of the gate electrode 105 is electrically separated into two. Next, after depositing an insulating film 109 as an interlayer film by a chemical vapor deposition method, a contact hole is opened on the diffusion layer upper layer 112 by lithography in order to connect the external electrode and the diffusion layer upper layer 112.
At this time, a part of the contact hole is
02. Next, a metal to be the electrode metal 110 is deposited by a sputter method, and the electrode metal 110 is formed by a lithography technique, whereby a semiconductor device having the insulated gate field effect transistor of the present invention is formed.

Next, a second embodiment of the present invention will be described with reference to FIG. Insulating gate sidewall 107
The diffusion layer upper layer 112 formed in a self-aligned manner on the side surface of
In the first embodiment, the semiconductor film in which the second conductivity type impurity is implanted at a high concentration is replaced with a metal film. By doing so, the diffusion layer upper layer 112 and the electrode metal 110 are connected with lower resistance.

Next, a third embodiment of the present invention will be described. FIG. 2 is a schematic sectional view showing a main part of an insulated gate field effect transistor according to a third embodiment of the present invention. In the figure, reference numeral 201 denotes a semiconductor substrate, 202 denotes an element isolation insulating region, and 203 denotes a gate. An insulating film, 205 is a gate electrode, 207 is an insulating gate sidewall, 212 is a diffusion layer upper layer, 213 is a diffusion layer lower layer, 214 is an N well, and 216 is a silicide.

After the semiconductor film for the gate electrode is grown as in the first embodiment, the semiconductor film is etched into a desired shape by lithography. In this manner, the gate electrode 2 can be removed without performing the step of removing the insulating film on the gate electrode 205 as shown in FIG.
A known silicidation process for lowering the resistance between the gate electrode 205 and the diffusion layer upper layer 212 can be performed, and the silicide film 216 for lowering the resistance between the gate electrode 205 and the diffusion layer upper layer 212 can be more simply formed. Can be formed.

[0036]

An embodiment of the present invention will be described in detail with reference to FIG. 3A and 3B are schematic cross-sectional views of a manufacturing process of an insulated gate field effect transistor according to an embodiment of the present invention. FIG. 3A shows an element isolation insulating region, a gate insulating film, a lower layer of a diffusion layer, a gate electrode on a semiconductor substrate. (B) a state in which an insulating gate side wall is formed and the gate insulating film is etched, (c) a state in which a polysilicon film is deposited,
(D) shows a state in which a diffusion layer upper layer is formed from a polysilicon film, and (e) shows a state in which an insulating film is deposited and an electrode metal is formed. In the figure, reference numeral 301 denotes a semiconductor substrate, 302 denotes an element isolation insulating region, 303 denotes a gate insulating film, 305 denotes a gate electrode, 307 denotes an insulating gate side wall, 309 denotes an insulating film, 31
Numeral 0 denotes an electrode metal, numeral 312 denotes a diffusion layer upper layer, numeral 313 denotes a diffusion layer lower layer, numeral 314 denotes an N well, and numeral 315 denotes a polysilicon film.

As shown in FIG. 3A, an element isolation insulating region 302 of about 400 nm is formed on a silicon substrate 301 by a known LOCOS method or a trench isolation method to divide the element region. At this time, the width of the element region in the direction in which the gate electrode 305 and the diffusion layer upper layer 312 are arranged side by side is set so that the height of the gate electrode 305 is 150 nm and the gate length is 100 nm so that the diffusion layer area is reduced. About 350nm
A degree is desirable. Next, a well region in which an N-type transistor and a P-type transistor are formed is formed by using a known ion implantation method and a heat treatment method. Here, a P-type transistor will be described as an example. The substrate 305 is made of P containing boron.
N-type well 314 in which a P-type transistor is to be formed is about 10 ¹⁶ c
^Contains phosphorus at a concentration of m ^-3 . Next, a gate oxide film 303 of about 4 nm is grown on the device region by a known thermal oxidation method, and then a polysilicon film of about 150 nm thickness for a gate electrode and an oxide film of about 50 nm are formed by a known chemical oxidation method. After being grown by the vapor phase growth method, the oxide film and the polysilicon film are etched by a known lithography technique so that the gate length becomes about 100 nm, and the gate electrode 3 is formed.
05 and an insulating film 311 covering the upper part of the gate electrode 305
And are formed.

Next, boron is implanted by ion implantation using the gate electrode 305 as a mask.
A low concentration shallow source / drain diffusion layer lower layer 313 is formed in a self-aligned manner with respect to the gate electrode 305. At this time, the boron concentration of the diffusion layer lower layer 313 is about 5 × 10 ¹⁹ c
m ⁻³ , and the depth of the diffusion layer lower layer 313 from the surface of the substrate 301 is about 50 nm.

Next, as shown in FIG. 3B, an oxide film of about 50 nm is deposited by a chemical vapor deposition method and then anisotropically etched to form a gate electrode 305 and a diffusion layer upper layer 312. Are about 50 in the direction in which they are arranged side by side
nm insulative gate sidewall 307 is formed and gate electrode 3
05 is covered with an insulating film.

Next, as shown in FIG. 3C, a polysilicon film 315 having a thickness of about 150 nm, which is almost equal to the height of the gate electrode 305, is deposited by a chemical vapor deposition method.

Next, as shown in FIG. 3D, the polysilicon film 315 is anisotropically etched to form a diffusion layer upper layer 312 on the side surface of the gate side wall 307 in a self-aligned manner. At this time, the width of the diffusion layer upper layer 312 in the direction in which the gate electrode 305 and the diffusion layer upper layer 312 are arranged side by side is about 150, which is almost the same as the thickness of the polysilicon film 315.
nm, and the width of the element region below the diffusion layer upper layer 312 in the direction in which the gate electrode 305 and the diffusion layer upper layer 312 are arranged side by side is about 75 nm. The opposite end is formed on the element isolation insulating region 302. Etching conditions are selected when performing anisotropic etching so that the thickness of the diffusion layer upper layer 312 becomes approximately 50 nm approximately uniformly. Next, boron is implanted into the diffusion layer upper layer 312 at a high concentration by an ion implantation method. At this time, the upper diffusion layer 3
In order to sufficiently reduce the resistance of boron, the boron concentration should be about 10
²¹ cm ^-3 . At this time, boron may be simultaneously implanted into the gate electrode 305 to reduce the resistance. The upper diffusion layer 312 and the lower diffusion layer 313 are both of the P-type conductivity, so that they are easily connected with low resistance. After this, the diffusion layer upper layer 3 surrounding the periphery of the gate electrode 305
12, the gate electrode 30 in the direction orthogonal to the direction in which the gate electrode 305 and the diffusion layer upper layer 312 are arranged side by side.
Only the portions covering the side surfaces at both ends of the gate electrode 305 are removed by lithography, and the upper diffusion layer 312 composed of the source and the drain on both sides of the gate electrode 305 is electrically separated into two.

Next, as shown in FIG. 3E, an insulating film 309 as an interlayer film is formed by a chemical vapor deposition method to a thickness of about 50 nm.
After deposition with a thickness of 0 nm, the external electrode and the diffusion layer upper layer 3
In order to connect the contact holes 12, a contact hole having a diameter of about 100 nm is formed on the upper diffusion layer 312 by lithography. At this time, a part of the contact hole may be on the element isolation insulating region 302. Next, a metal to be the electrode metal 310 is deposited by a known sputtering method, and the electrode metal 310 is formed by a lithography technique, whereby a semiconductor device having the insulated gate field effect transistor of the present invention is formed.

[0043]

As described above, the first effect of the present invention is that the junction capacitance between the diffusion layer and the substrate is reduced. Therefore, the semiconductor device can operate at higher speed and power consumption can be reduced. The reason is,
This is because the area of the diffusion layer can be reduced because the element region is narrowed by the element isolation insulating region. In addition, a diffusion layer partially overlapping the element isolation insulating region can be formed in a self-aligned manner with respect to the insulating gate side wall on the side surface of the gate electrode. This is because the diffusion layer area, which had to be widened, can be further reduced.

The second effect is that the manufacturing process is simplified and the productivity is improved. The reason is that the formation of the diffusion layer does not require a silicon selective growth step, and the diffusion layer can be easily formed only by anisotropic etching.

A third effect is that the area of the entire transistor can be further reduced. The reason is that the distance between the end of the diffusion layer on the side of the gate electrode and the end on the opposite side can be easily reduced to about the same as or less than the height of the gate electrode.

A fourth effect is that when a contact hole is formed on the diffusion layer by lithography, the alignment margin increases. The reason is
This is because the diffusion layer is formed on the element isolation insulating region and the contact hole may protrude above the element isolation insulating region.

The fifth effect is that a so-called short channel effect due to a deep diffusion layer can be prevented.
The reason is that the semiconductor substrate does not have a deep diffusion layer containing a high concentration of impurities.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of an insulated gate field effect transistor according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a main part of an insulated gate field effect transistor according to a third embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view of a manufacturing process of the insulated gate field effect transistor according to the embodiment of the present invention. (A) shows a state where an element isolation insulating region, a gate insulating film, a lower layer of a diffusion layer, a gate electrode, and an insulating film are formed on a semiconductor substrate.
(B) shows a state where the insulating gate side wall is formed and the gate insulating film is etched. (C) is a state where a polysilicon film is deposited. (D) shows a state in which a diffusion layer upper layer is formed from a polysilicon film. (E) shows a state in which an insulating film is deposited and an electrode metal is formed.

FIG. 4 is a schematic cross-sectional view showing a manufacturing process of a conventional insulated gate field effect transistor having a basic LDD structure. (A) shows a state where an element isolation insulating region, a gate insulating film, and a polysilicon film are grown on a semiconductor substrate.
(B) shows a state in which a gate electrode is formed from a polysilicon film and a diffusion layer is formed. (C) shows a state in which an insulating gate side wall is formed and a high concentration diffusion layer is formed.
(D) shows a state in which an insulating film is deposited and an electrode metal is formed.

FIG. 5 is a schematic cross-sectional view showing a manufacturing process of a conventional insulated gate field-effect transistor having a diffusion layer that partially runs on an element isolation insulating region. (A) grows an element isolation region, an oxide film, a polysilicon film on a semiconductor substrate,
This is a state where the polysilicon film is etched. (B) shows a state where the oxide film is removed and a silicon selective growth film is deposited. (C) shows a state where a gate insulating film, a gate electrode, an insulating gate side wall, and a diffusion layer are formed. (D) shows a state in which an insulating film is deposited and an electrode metal is formed.

FIG. 6 is a schematic cross-sectional view of a conventional insulated gate transistor having a diffusion layer having a structure rising upward from the surface of a semiconductor substrate.

[Explanation of symbols]

101, 201, 301, 401, 501, 601
Semiconductor substrate 102, 202, 302, 402, 502, 602
Element isolation insulating regions 103, 203, 303, 403, 503 Gate insulating films 105, 205, 305, 405, 505, 605
Gate electrode 107, 207, 307, 407, 507 Insulating gate side wall 109, 309, 409, 509, 609 Insulating film 110, 310, 410, 510, 610 Electrode metal 111, 611 Insulating film 112, 212, 312 Upper layer of diffusion layer 113, 213, 313 Diffusion layer lower layer 114, 214, 314, 414, 514, 614
N well 216 Silicide 315 Polysilicon film 404 Polysilicon film 406, 606 Diffusion layer 408, 508 Diffusion layer 517 Polysilicon film 518 Oxide film 519, 619 Silicon selective growth film

Claims (12)

[Claims] A gate electrode provided on a semiconductor substrate of a first conductivity type via a gate insulating film and having an insulating side wall; and a gate electrode formed on the semiconductor substrate at an interval around the gate electrode. An insulating gate type electric field having a diffusion layer forming a source and a diffusion layer forming a drain of a second conductivity type different from the substrate, wherein a current flowing between the two kinds of diffusion layers is controlled by the gate electrode. A semiconductor device provided with an effect transistor, wherein the element region is formed by being separated by an element isolation insulating region below the gate electrode in the semiconductor substrate forming the insulated gate field effect transistor; The distance between the position in contact with the element isolation insulating region in the portion where the two types of diffusion layers are formed and the side surface of the gate electrode is equal to the gate voltage. The two types of diffusion layers are both formed of an upper layer and a lower layer, and the distance between the end of the upper layer of the diffusion layer on the side of the gate electrode and the end of the upper layer of the element isolation insulating region is smaller than the height of the diffusion layer. A semiconductor device having a height not less than the height of the gate electrode and an end portion on the element isolation region side formed on the element isolation region. 2. The semiconductor device according to claim 1, wherein said upper layer of said diffusion layer is formed of polysilicon. 3. The semiconductor device according to claim 1, wherein said upper layer of said diffusion layer is formed of a metal. 4. A method for manufacturing an insulated gate field effect transistor formed in a semiconductor device, comprising:
In a conductive type semiconductor substrate, an element isolation insulating region formed surrounding an element region is formed at a position in contact with the element region on the side where a diffusion layer of the element insulating isolation region is formed, and at the element region. Forming a gap so as to be equal to or less than the height of the gate electrode, forming a well region in the device region, and forming a gate oxide film on the device region. Forming a gate electrode on the gate oxide film; implanting an impurity of a second conductivity type different from the first conductivity type by an ion implantation method using the gate electrode as a mask; Forming a shallow diffusion layer underlayer in the vicinity; depositing an oxide film on the gate insulating film by chemical vapor deposition, and removing unnecessary portions of the oxide film and the gate oxide film by anisotropic etching. Forming a self-aligned insulating gate sidewall on the side surface of the gate electrode, and forming an upper layer of a diffusion layer made of a conductive film on the gate electrode side end of the upper layer of the diffusion layer and the element isolation insulating region. Forming a distance such that the distance from the side of the gate electrode is equal to or greater than the height of the gate electrode, and the end on the side of the element isolation region is located on the element isolation region. Forming a contact hole in the interlayer film, and forming an electrode metal in the contact hole such that at least a part of the tip is connected to the upper layer of the diffusion layer. A method for manufacturing a semiconductor device. 5. The step of forming the upper layer of the diffusion layer made of a conductive film includes depositing a semiconductor film over the whole, removing an unnecessary portion of the semiconductor film by anisotropic etching, and removing the insulating gate side wall. 5. The method for manufacturing a semiconductor device according to claim 4, further comprising the step of forming an upper layer of the diffusion layer in a self-aligned manner in contact with the semiconductor layer, and implanting the impurity of the second conductivity type into the upper layer of the diffusion layer at a high concentration by ion implantation. . 6. The step of forming the upper layer of the diffusion layer made of a conductive film includes depositing a semiconductor film over the entire surface, removing an unnecessary portion of the semiconductor film by anisotropic etching, and removing the insulating gate side wall. 5. The method for manufacturing a semiconductor device according to claim 4, further comprising the step of forming an upper layer of the diffusion layer in a self-aligned manner in contact with the substrate, and forming a silicide film on the upper layer of the diffusion layer. 7. The method according to claim 5, wherein the method of depositing the semiconductor film for forming the upper layer of the diffusion layer is a chemical vapor deposition method. 8. The method of manufacturing a semiconductor device according to claim 5, wherein a method of depositing the semiconductor film for forming the upper layer of the diffusion layer is a sputtering method. 9. The method of manufacturing a semiconductor device according to claim 5, wherein said semiconductor film is a polysilicon film. 10. The step of forming the upper layer of the diffusion layer made of a conductive film includes: depositing a metal film over the entire surface; removing an unnecessary portion of the metal film by anisotropic etching; 5. The method for manufacturing a semiconductor device according to claim 4, further comprising the step of forming an upper layer of the diffusion layer in a self-aligned manner in contact with the semiconductor device. 11. The method according to claim 10, wherein the method of depositing the metal film for forming the upper layer of the diffusion layer is a chemical vapor deposition method. 12. The method according to claim 10, wherein the method of depositing the metal film for forming the upper layer of the diffusion layer is a sputtering method.