JPH07273183A - Semiconductor device and its fabrication - Google Patents

Abstract

PURPOSE:To prevent an electrode material from being left between an insulating film and a substrate at the time of etching by depositing a specific film, while tapering reversely, around a trench on the surface of an insulating film deposited on a substrate and then depositing an isolation film on the substrate while tapering forward thereby eliminating the level difference between the isolation film and the surface of the substrate. CONSTITUTION:A specific film is deposited, while tapering reversely, around a trench on a substrate 11 and an isolation film (oxide) 41 being deposited in a subsequent process covers the edge of the substrate 11 while tapering forward. Consequently, the level difference is eliminated between the isolation film (oxide) 41 and the semiconductor substrate 11 and no polysilicon film 51 is left at the border when a polysilicon film 51 is etched to form a gate electrode. This method prevents dielectric breakdown between gate electrodes thus enhancing the withstand voltage between gate electrode and thereby the reliability of an element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to an element isolation insulating film and a forming method thereof.

[0002]

2. Description of the Related Art When manufacturing a semiconductor device such as a transistor or a memory, element isolation regions are formed between elements in order to insulate and isolate the individual elements. As the element isolation region, a method of forming an oxide film on a semiconductor substrate by a selective oxidation method before forming an element, a method of forming a groove having a predetermined depth in the semiconductor substrate and forming an oxide film in the groove, etc. There is. The technique of forming a groove in a semiconductor substrate and filling an oxide film in the groove with an insulating film is a technique that is widely used throughout the manufacture of an LSI.

A conventional method for forming trench element isolation will be described below. First, as shown in FIG. 9, a first oxide film 92 is formed as an insulating film on the surface of a semiconductor substrate 91 on which elements such as transistors are not formed. Next, a polycrystalline silicon film 93 is deposited on the surface of the first oxide film 92, and a second oxide film 94 is further formed on the surface to apply a resist. A resist 95 is applied on the surface of the second oxide film 94, the resist 95 is patterned, and the polycrystalline silicon film 93 is used as a mask.
Then, the second oxide film 94 is etched by anisotropic etching.

Subsequently, as shown in FIG. 10, the resist 95 used as the mask is removed by ashing, and then the polycrystalline silicon film 93 is etched back to a predetermined position by a CDE (Chemical Dry Etching) method. Next, using the etched second oxide film 94 as a mask, the first oxide film 92 is etched by anisotropic etching, and then a groove having a predetermined depth is formed in the semiconductor substrate 91. Through the above steps, the trench for element isolation is formed in the semiconductor substrate.

Subsequently, as shown in FIG. 11, the inside of the groove is filled with C to the same height as the upper surface of the polycrystalline silicon film 93.
Oxide film 1 by VD (Chemical Vapor Deposition) method
11 is formed. This oxide film 111 serves as an insulating film for element isolation. Next, in order to form a gate electrode, the first and second oxide films 92 and 94 and the polycrystalline silicon film 93 are separated, and a gate oxide film 112 is newly formed on the semiconductor substrate 91. Next, a polycrystalline silicon film 113 is deposited on the surface of the oxide film 112 on the semiconductor substrate 91 and on the surface of the oxide film 111 for element isolation with a desired gate electrode thickness. Next, in order to form the gate electrode, the resist pattern 114 is formed so that the resist remains in the region where the gate electrode is to be formed.
To form.

Then, as shown in FIG. 12, the polycrystalline silicon film 113 is etched to form a gate electrode by using the resist pattern 114 as a mask to form a gate electrode pattern 122. Next, the resist pattern 114 is removed by ashing. Through the above steps, an oxide film for element isolation and a gate electrode are formed.

[0007]

In the conventional manufacturing method as described above, in order to protect the edge portion of the semiconductor substrate above the groove as shown in FIG. 12, the oxide film embedded in the groove is formed outside the groove. Is formed on the semiconductor substrate and the edge portion of the substrate is covered with an oxide film. However,
When this method is used, when the polycrystalline silicon film is etched to form the gate electrode, the oxide film for element isolation formed outside the groove to cover the edge portion of the semiconductor substrate and the semiconductor substrate surface There is a problem that a part of the polycrystalline silicon film is left without being removed at the step portion existing in. The remaining polycrystalline silicon of the electrode material remains around the insulating film for element isolation, which causes a dielectric breakdown between the gate electrodes located on both sides of the element isolation region, and causes a gap between the gate electrodes. However, there is a problem that the withstand voltage is significantly reduced.

[0008]

In view of the above problems, according to the present invention, a predetermined film formed on the surface of an insulating film on a semiconductor substrate is formed before forming an insulating film for element isolation. , A reverse taper shape is formed around the element isolation groove.
As a result, an insulating film for element isolation formed later covers the edge portion of the semiconductor substrate above the groove and is further formed in a forward tapered shape on the surface of the semiconductor substrate. Accordingly, there is no step between the insulating film for element isolation formed covering the edge portion of the semiconductor substrate and the surface of the semiconductor substrate, and when the polycrystalline silicon film is etched to form the gate electrode, The electrode material does not remain in the portion between the element isolation insulating film and the semiconductor substrate. Therefore, it is an object of the present invention to eliminate the dielectric breakdown between the gate electrodes due to the remaining electrode material of the polycrystalline silicon film, which has been a problem in the past, improve the breakdown voltage between the gate electrodes, and improve the reliability of the device. And

As a method for forming a predetermined film into a reverse taper shape, an impurity is introduced into the predetermined film, and an etching rate for etching is changed depending on the kind of the impurity and the concentration thereof.
The difference between the two is used. For example, in isotropic etching of polycrystalline silicon, N in the polycrystalline silicon film is increased.
When P, which is a type impurity, is introduced, the etching rate thereof is faster than that of a polycrystalline silicon film in which no impurity is introduced. When B, which is a P-type impurity, is introduced into the polycrystalline silicon film, the etching rate becomes slower than that of the polycrystalline silicon film containing no impurity. Therefore, by controlling the type and concentration of the impurities, a predetermined film having a reverse taper shape is formed.

[0010]

According to the present invention, in the method for forming an element isolation region, a predetermined film formed on a semiconductor substrate is formed in a reverse taper shape around a trench before forming an insulating film for element isolation. To do. As a result, an insulating film for element isolation formed in a later step covers the edge portion of the semiconductor substrate on the surface of the semiconductor substrate and is further formed in a forward tapered shape. Since the insulating film for element isolation is formed in a forward taper shape on the substrate, the step between the insulating film for element isolation and the semiconductor substrate is eliminated, so that polycrystalline silicon is used to form a gate electrode later. When the film is etched, the polycrystalline silicon film does not remain in this portion. Therefore, in the present invention, it is possible to eliminate the dielectric breakdown between the gate electrodes due to the remaining electrode material, which has been a problem in the past, improve the breakdown voltage between the gate electrodes, and improve the reliability of the device.

[0011]

Embodiments of the present invention will be described with reference to the drawings. As shown in FIG. 1, a 100-nm-thick first oxide film 12 is formed on the surface of a semiconductor substrate 11 by thermal oxidation, and a 200 nm-thick film is formed on the surface of the first oxide film 12 by a low pressure CVD method. One polycrystalline silicon film 13 is formed. Here, P that is an N-type impurity is diffused into the first polycrystalline silicon film 13 by thermal diffusion at 900 ° C. for 60 minutes in a POCl 3 atmosphere. Next, the second polycrystalline silicon film 14 having no impurities introduced therein is formed again to a film thickness of 200 nm by the low pressure CVD method. Next, in order to diffuse P into the second polycrystalline silicon film 14, 800 ° C.,
Heat treatment is performed in a nitrogen atmosphere for 10 minutes. FIG. 8 shows the relationship between the thickness of the polycrystalline silicon film and the concentration of P-type impurities in the polycrystalline silicon films 13 and 14 formed by the above method.
Shown in. The horizontal axis of the figure represents the thickness of the polycrystalline silicon film, and the positive direction is the semiconductor substrate surface side. The vertical axis represents the concentration of P-type impurities. As shown in the figure, the concentration of P in the first and second polycrystalline silicon films 13 and 14 is low on the surface side of the polycrystalline silicon film and increases as it approaches the semiconductor substrate surface side. Then, a second oxide film 15 is formed as an insulating film on the second polycrystalline silicon film 14 by atmospheric pressure CVD to have a film thickness of 300 nm. Next, in order to form a groove for element isolation in the semiconductor substrate 11, a resist 16 is patterned by lithography, and the second oxide film 1 is formed using this resist as a mask.
5 and the polycrystalline silicon films 13 and 14 are patterned by anisotropic etching.

Subsequently, as shown in FIG. 2, the polycrystalline silicon film 1 is formed using the first and second oxide films 12 and 15 as masks.
3 and 14 are etched to the extent that an insulating film for element isolation is formed. Here, in order to etch the polycrystalline silicon film into a reverse taper shape, isotropic etching is performed. This isotropic etching can be performed by CDE or wet etching. The impurity concentration of P in the polycrystalline silicon film increases as it approaches the surface of the semiconductor substrate, so the etching rate increases as it approaches the surface of the semiconductor substrate. Therefore, the etching amount increases as it approaches the surface of the semiconductor substrate, and the polycrystalline silicon film can be etched into an inverse taper shape.

Then, as shown in FIG. 3, the first oxide film 12 is formed using the resist 16 and the second oxide film 15 as a mask.
Is patterned by anisotropic etching. After removing the resist 16 by ashing, the first oxide film 12 is removed.
Using the second oxide film 15 as a mask, anisotropically etching is performed to form a groove 31 for element isolation in the semiconductor substrate 11. The groove has a width of 0.5 μm and a depth of 3 μm.

Subsequently, as shown in FIG. 4, the semiconductor substrate 11
An oxide film 41 is formed by a low pressure CVD method so that these space portions are filled up to the inside of the element isolation trench 31 formed in and the height of the upper surface of the polycrystalline silicon film 14. This oxide film 41 serves as an insulating film for element isolation. The oxide film 41 is formed in a space formed by etching the inversely tapered polycrystalline silicon films 13 and 14 without any gap. Therefore, the groove 3 for element isolation
1 for covering the upper edge portion of 1 and for further isolation 31
Is formed in a forward taper shape around. Next, the first and second oxide films 12 and 15 and the polycrystalline silicon films 13 and 14 are removed, and a gate oxide film 42 is newly formed on the surface of the semiconductor substrate 11.

Subsequently, as shown in FIG. 5, a polycrystalline silicon film 51 is formed on the surface of the oxide film 42 on the semiconductor substrate 11 for forming the gate electrode and on the surface of the oxide film 41 for separating the element, to form a desired gate electrode. And is patterned so that the resist remains on the region where the gate electrode is to be formed, to form a resist pattern 52. Next, the resist pattern 52
Using the as a mask, the polycrystalline silicon film 51 is etched by anisotropic etching to form a gate electrode. Since there is no step between the insulating film for element isolation and the semiconductor substrate, the polycrystalline silicon film other than the gate electrode portion must be completely removed when etching the polycrystalline silicon film to form the gate electrode. It is possible to prevent the polycrystalline silicon film from remaining.

Next, FIG. 6 shows the relationship between the impurity concentration of P and B in the polycrystalline silicon film and the etching rate. P
The etching methods and conditions for B and B are the same. The horizontal axis of the figure shows the impurity concentration, and the vertical axis shows the etching rate.
In the case of a polycrystalline silicon film in which P is introduced as shown in the figure, the etching rate increases as the concentration increases. On the other hand, in the case of a polycrystalline silicon film in which B is introduced, the etching rate becomes slower as the concentration becomes higher.

As a method of introducing impurities into the polycrystalline silicon film and changing the etching rate according to the difference in the type and concentration of the impurities, three types of impurities as shown in FIGS. A profile is possible. Here, the horizontal axis of the figure represents the thickness of the polycrystalline silicon film, and the vertical axis represents the impurity concentration. The film thickness is in the positive direction on the front surface side of the semiconductor substrate in this embodiment. The impurity concentration is N in the negative direction.
The positive and negative directions represent the P-type density. As the type of impurity, P or As can be used as the N-type impurity and B can be used as the P-type impurity. The pattern of FIG. 7A shows the case where the impurity is only P type, and the higher the impurity concentration is, the slower the etching rate is. Therefore, in the present invention, the upper surface side of the polycrystalline silicon film approaches the semiconductor substrate surface side. Therefore, the concentration of P-type impurities needs to be lowered. The pattern of FIG. 7B is for the case where the impurity is only N type, and the higher the impurity concentration is, the faster the etching rate is. Therefore, in the present invention, the upper surface side of the polycrystalline silicon film approaches the semiconductor substrate side. The higher the concentration of N-type impurities, the higher. Further, the pattern of FIG. 7C is a case where both N-type and P-type are used as impurities, which is a combination of FIGS. 7A and 7B. In the present invention, it is necessary to form the polycrystalline silicon film so that the concentration of the N-type impurity is high on the semiconductor substrate surface side and the concentration of the P-type impurity is high on the upper surface side of the polycrystalline silicon film. .

As a method of introducing impurities into polycrystalline silicon, there are the following first to seventh methods depending on the kind of impurities. The first to third introduction methods are methods of introducing only P-type impurities into the polycrystalline silicon film. The first introduction method is a method of forming a polycrystalline silicon film by two layers as shown in the above-mentioned embodiment. First, the first polycrystalline silicon film with no impurity introduced has a film thickness of 200 nm. Is formed on the surface of the oxide film of the semiconductor substrate, and then vapor phase diffusion is performed so that P-type impurities are introduced into the first polycrystalline silicon film. Subsequently, a second polycrystalline silicon film having a film thickness of 200 nm is formed on the surface of the first polycrystalline silicon film, thermal diffusion is performed, and impurities are diffused also in the second polycrystalline silicon film.

As a second introduction method, a polycrystalline silicon film in which a P-type impurity has been introduced in advance has a film thickness of 200 nm.
After depositing a second polycrystalline silicon film having no impurities introduced on the surface of the oxide film of the semiconductor substrate by the CVD method and having a film thickness of 200 nm on the surface of the first polycrystalline silicon film, This is a method of diffusing impurities into the second polycrystalline silicon film by solid phase diffusion. According to this method, the first polycrystalline silicon film can also be formed by the vapor phase diffusion method. In this case, when the first polycrystalline silicon film is formed by the low pressure CVD method, the SiH ₄ gas and the B ₂ H ₆ gas are caused to flow to form the first polycrystalline silicon film into which B is introduced. Is also possible.

The third introduction method is to form a polycrystalline silicon film in one layer. A polycrystalline silicon film having a thickness of 400 nm is formed on the surface of the oxide film on the semiconductor substrate,
B implantation energy 15 keV, dose 1 × 10 ¹⁶ a
This is a method in which ions are implanted at toms · cm ⁻² and thermal diffusion is performed in a nitrogen atmosphere at 800 ° C. for 10 minutes. When this method is used, it is not necessary to form the polycrystalline silicon film in two layers, so that the number of steps can be reduced.

The fourth to sixth introduction methods are methods of introducing N-type impurities into the polycrystalline silicon film. A fourth introduction method is a method of forming a polycrystalline silicon film in two layers. First, a first polycrystalline silicon film with no impurities introduced is formed on the oxide film surface of a semiconductor substrate to a thickness of 200 nm, and then a second polycrystalline silicon film with an N-type impurity introduced is first formed. Is deposited on the surface of the polycrystalline silicon film to a thickness of 200 nm, and then impurities are diffused into the first polycrystalline silicon film by thermal diffusion by solid phase diffusion. Here, it is also possible to form the second polycrystalline silicon film by a vapor phase diffusion method. in this case,
When the second polycrystalline silicon film is formed by the low pressure CVD method, SiH ₄ gas and PH ₃ gas are caused to flow so that P
It is also possible to form a first polycrystalline silicon film into which is introduced.

As a fifth introduction method, a polycrystalline silicon film is formed in a single layer, the polycrystalline silicon film having a film thickness of 400 nm is formed on the oxide film surface of the semiconductor substrate, and vapor phase diffusion is performed. This is a method of diffusing N-type impurities into the polycrystalline silicon film.

As a sixth introduction method, a polycrystalline silicon film is formed in a single layer, and the polycrystalline silicon film is formed in a thickness of 400 nm on the oxide film surface of the semiconductor substrate, and P
Acceleration energy of 30 keV, dose amount of 1 × 10 ¹⁶ at
This is a method in which ion implantation is performed at oms · cm ⁻² and thermal diffusion is performed in a nitrogen atmosphere at 800 ° C. for 10 minutes. When this method is used, it is not necessary to form the polycrystalline silicon film in two layers, so that the number of steps can be reduced.

The seventh introduction method is a method of introducing P-type and N-type impurities into the polycrystalline silicon film, respectively. In this case, a P-type impurity is introduced after forming a first polycrystalline silicon film with a thickness of 200 nm on the oxide film surface of the semiconductor substrate, and then a second polycrystalline silicon film is formed on the surface of the first polycrystalline silicon film. This is a method of forming a crystalline silicon film with a film thickness of 200 nm and introducing an N-type impurity, and can be carried out by the solid phase diffusion method or the vapor phase diffusion method as in the above-mentioned embodiment. When P-type and N-type impurities are introduced into the polycrystalline silicon film by the ion implantation method, P-type impurities are ion-implanted after forming the first polycrystalline silicon film, and then the first polycrystalline film is formed. In this method, a second polycrystalline silicon film is formed on the surface of the silicon film, N-type impurities are ion-implanted, and then thermal diffusion is performed. As described above, when the polycrystalline silicon film is etched into the inverse tapered shape as in the present invention, the desired shape can be obtained by changing the kind and concentration of impurities contained in the polycrystalline silicon film depending on the depth. Obtainable. Regarding the diffusion of impurities into the polycrystalline silicon film,
Depending on the type of impurities to be introduced into the polycrystalline silicon film like the introduction methods shown in the first to seventh, there are methods such as ion implantation, vapor phase diffusion, and solid phase diffusion. It is also possible to form a polycrystalline silicon film into which impurities of different types and concentrations are introduced by appropriately combining methods such as a vapor phase diffusion method and a solid phase diffusion method. Also,
In this embodiment, the polycrystalline silicon film is used as the film that is etched in the inverse taper shape. However, when the insulating film used for element isolation and the gate insulating film is an oxide film, the oxide film has a different etching rate and impurities. Any material can be used as long as it has a difference in etching rate depending on the type and concentration of the material, and a nitride film can also be used. Further, although the total thickness of the polycrystalline silicon film is shown to be 400 nm, the present invention is not limited to this, and may be varied depending on the height of the insulating film for element isolation formed in a later step. It will change.

[0025]

According to the method of forming the element isolation region of the present invention, the insulating film for element isolation is formed in a forward taper shape on the surface of the semiconductor substrate. This prevents the electrode material from remaining on the step between the insulating film for element isolation and the semiconductor substrate during the subsequent etching of the polycrystalline silicon film for forming the gate electrode. Therefore, the dielectric breakdown due to the remaining electrode material, which has been a problem in the past, can be eliminated, the breakdown voltage between the gate electrodes can be improved, and the reliability of the device can be improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining the manufacturing method of this embodiment.

FIG. 2 is a cross-sectional view for explaining the manufacturing method of this embodiment.

FIG. 3 is a cross-sectional view for explaining the manufacturing method of this embodiment.

FIG. 4 is a cross-sectional view for explaining the manufacturing method of this embodiment.

FIG. 5 is a cross-sectional view for explaining the manufacturing method of this embodiment.

FIG. 6 is a characteristic diagram showing the relationship between impurity concentration and etching rate.

FIG. 7 is an explanatory diagram showing a pattern of impurities.

FIG. 8 is a characteristic diagram showing the film thickness and impurity concentration of the polycrystalline silicon film of this example.

FIG. 9 is a sectional view showing a conventional manufacturing method.

FIG. 10 is a cross-sectional view showing a conventional manufacturing method.

FIG. 11 is a cross-sectional view showing a conventional manufacturing method.

FIG. 12 is a cross-sectional view showing a conventional manufacturing method.

[Explanation of symbols]

11, 91 semiconductor substrate 12, 15, 41, 42, 92, 94, 111, 112
Oxide film 13, 14, 51, 93, 113 Polycrystalline silicon film 16, 52, 95, 114 Resist pattern 31 Element isolation groove 41 Oxide film 122 Gate electrode

Claims (16)

[Claims] 1. A step of forming a first insulating film on a surface of a semiconductor substrate; a step of forming a predetermined film having a different etching rate on the surface of the insulating film according to a thickness direction of the film; Forming a second insulating film on the surface of the film, forming a hole in the second insulating film, and etching the predetermined film laterally through the opening to reverse the predetermined film. Tapering, forming a groove having a predetermined depth in the semiconductor substrate through the opening, and forming a third insulating film in the groove including at least the predetermined film formed in an inverse taper shape. And a step of forming an element isolation region having the following structure. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity is a P-type impurity, and is formed such that its concentration decreases from the upper surface side of the predetermined film to the semiconductor substrate surface side. A method of manufacturing a semiconductor device, comprising: 3. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity is an N-type impurity, and is formed such that its concentration increases from the upper surface side of the predetermined film to the semiconductor substrate surface side. A method of manufacturing a semiconductor device, comprising: 4. The method of manufacturing a semiconductor device according to claim 1, wherein the impurities are P-type and N-type impurities, and the concentration of the P-type impurities is from the upper surface of the predetermined film to the semiconductor substrate surface side. A method of manufacturing a semiconductor device, wherein the concentration of the N-type impurity is increased from the upper surface of the predetermined film toward the surface of the semiconductor substrate so as to be lower. 5. The method of manufacturing a semiconductor device according to claim 2, wherein the predetermined film is a first-layer film in which impurities are not introduced on the surface of the semiconductor substrate, and the predetermined film is formed on the first-layer film surface. A second-layer film in which the P-type impurity is introduced is formed on the substrate, and the P-impurity is diffused in the first-layer film and the second-layer film to form the semiconductor device. Method. 6. The method of manufacturing a semiconductor device according to claim 3, wherein the predetermined film is a first-layer film in which the N-type impurity is introduced, formed on the surface of the semiconductor substrate. A method of manufacturing a semiconductor device, comprising forming a second layer film in which no impurities are introduced on a film surface, and diffusing the N impurities in the first and second layers. 7. The method of manufacturing a semiconductor device according to claim 4, wherein the predetermined film is a first-layer film in which the N-type impurity is introduced, formed on the surface of the semiconductor substrate. A semiconductor characterized in that a second-layer film in which the P-type impurity is introduced is formed on a film surface, and the N-impurity and P-type impurity are diffused in the first and second layers. Device manufacturing method. 8. The method of manufacturing a semiconductor device according to claim 1, wherein impurities are introduced into the predetermined film by a solid phase diffusion method. 9. The method of manufacturing a semiconductor device according to claim 2, 3 or 4, wherein impurities are introduced into the predetermined film by an ion implantation method. 10. The method of manufacturing a semiconductor device according to claim 2, 3 or 4, wherein the etching of the predetermined film is performed by isotropic etching. 11. The method of manufacturing a semiconductor device according to claim 1, wherein the first and second insulating films are oxide films, and the predetermined film is a polycrystalline silicon film. Manufacturing method. 12. The method of manufacturing a semiconductor device according to claim 1, wherein the third insulating film is formed up to a space having a height of an upper surface of the predetermined film. . 13. A step of forming a predetermined layer on a surface of a semiconductor substrate; a step of forming a first groove in which a side of the predetermined layer closer to the surface of the semiconductor substrate is wider than a side farther from the side; A step of forming a second groove having a predetermined depth in the semiconductor substrate through the groove; and a step of forming an element isolation region by filling an insulating film in the first and second grooves, Of manufacturing a semiconductor device. 14. The method of manufacturing a semiconductor device according to claim 13, wherein the second groove is formed by anisotropic etching using the first groove as a mask. 15. A semiconductor substrate, a plurality of semiconductor elements formed on the semiconductor substrate, a groove having a predetermined depth formed between the plurality of semiconductor elements, and an upper portion of the groove filling the inside of the groove. A semiconductor device having an element isolation region formed of an insulating film formed to cover the element isolation region, the element isolation region being formed by covering an upper portion of the groove with an inverse taper shape. 16. The semiconductor device according to claim 15, wherein the semiconductor element is electrically isolated in the semiconductor substrate by the element isolation region, and is electrically isolated by a conductive layer formed on the element isolation region. A semiconductor device characterized by being connected to.