JPH09139382A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form channel stoppers in the positions suitable for the thicknesses of the respective field films even in the case where various kinds of field films with different film thicknesses are present. SOLUTION: After forming field oxide films 5a, 5b having different film thicknesses caused by a different element separation width, boron ions 7 are implanted twice 7 with acceleration energy 150keV and 190keV while a photoresist 6 as a mask. Boron implantation regions 8a, 8b, 9a, 9b thereby formed become channel stoppers 10a, 10b and 11 on the lower ends of the field oxide films 5a, 5b and on a silicon substrate 1 in the neighboring regions by a later heat treatment respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a channel stopper below an element isolation insulating film such as a field oxide film.

[0002]

2. Description of the Related Art As a technique for electrically separating a large number of elements such as transistors formed in a semiconductor device,
Dielectric isolation methods are known. The dielectric isolation method is to perform isolation between elements by forming an insulating film having a large film thickness (an insulating film for element isolation) surrounding an element such as a transistor, and as a typical method, a LOCOS method or There is a trench isolation method.

However, if wiring or the like is present on the element isolation insulating film, a parasitic channel is formed under the element isolation insulating film under the influence of the potential thereof, and an adjacent transistor may become conductive. is there. Therefore, by forming a relatively high-concentration impurity diffusion layer of the same conductivity type as the semiconductor substrate called a channel stopper under the element isolation insulating film and increasing the threshold voltage of the parasitic transistor,
We try to prevent such a situation.

A method of forming an element isolation structure using this channel stopper will be described with reference to FIG. 4 by taking the case of element isolation by the LOCOS method as an example. First,
As shown in FIG. 4A, a silicon nitride film 43 is formed on a P-type silicon substrate 41 with a silicon oxide film 42 interposed therebetween.

Next, as shown in FIG. 4B, the silicon nitride film 43 in the region to be an element isolation region is selectively removed by etching.

Next, as shown in FIG. 4C, boron (B) 44 is ion-implanted using the remaining silicon nitride film 43 as a mask to form a boron-implanted region 45 in the surface portion of the silicon substrate 41.

Next, as shown in FIG. 4D, heat treatment is performed using the silicon nitride film 43 as an anti-oxidation film, and the silicon substrate 41 in a region not covered with the silicon nitride film 43.
Is oxidized to form a field oxide film (silicon oxide film) 46 having a large film thickness, and the boron implantation region 45 is activated to form a channel stopper 47 which is a P-type impurity diffusion layer.
And

By thus forming the channel stopper 47 under the field oxide film 46, a parasitic channel is formed under the field oxide film 46 and it is possible to reliably prevent the parasitic transistor from conducting. .

[0009]

However, as elements such as transistors have become finer, the distance between adjacent elements has become smaller, resulting in the phenomenon that the threshold voltage of the parasitic transistor is lowered. Therefore, it has been necessary to increase the amount of impurities such as boron to be ion-implanted to increase the impurity concentration of the channel stopper so that the threshold voltage of the parasitic transistor does not decrease.
As described above, when the ion implantation amount of the impurity for forming the channel stopper is increased, the impurity is laterally diffused by the heat treatment at the time of forming the field oxide film and spreads to the element region. As a result, a narrow channel effect occurs, the junction breakdown voltage of the source / drain diffusion layer of the transistor decreases, the junction capacitance increases, and the operating speed of the transistor decreases, or the channel of the transistor formed in the element region is reduced. There is a problem that the width is reduced and the threshold voltage is significantly increased.

In order to prevent such a narrow channel effect, a method of performing selective oxidation for forming a field oxide film and then ion-implanting impurities for forming a channel stopper can be considered. That is, as shown in FIG. 5A, after the silicon nitride film 53 is patterned on the silicon substrate 51 with the silicon oxide film 52 interposed therebetween,
As shown in (b), the silicon nitride film 53 is used as an anti-oxidation film to selectively thermally oxidize the silicon substrate 51 to form a field oxide film 54. Further, as shown in FIG. Boron 56 is ion-implanted using the photoresist 55 patterned so as to have an opening on the film 54 as a mask to form a boron-implanted region 57 under the field oxide film 54. Then, heat treatment is performed to activate the boron implantation region 57 to form a channel stopper. According to the above steps, after the field oxide film 54 is formed, boron 56 is ion-implanted using the photoresist 55 having an opening having a width narrower than the width of the field oxide film 54 as a mask, so that the boron diffuses laterally. As a result, the narrow channel effect does not occur, and the above problem does not occur.

However, the film thickness of the field oxide film formed by the LOCOS method depends on the element isolation width,
If the element isolation width is about 1 μm or more, it becomes constant, but if the element isolation width becomes smaller than about 1 μm, a so-called field oxide thinning effect occurs, which sharply decreases. Further, it is known that the depth of the trench formed by the trench isolation method also depends on the element isolation width, and becomes smaller as the element isolation width becomes smaller than a certain value. On the other hand, the element isolation width in a semiconductor device in which a transistor or the like is integrated is not generally uniform.
In a RAM, a region having an extremely small isolation width such as in a memory cell array and a region having a relatively low integration degree and a large isolation width such as a peripheral circuit portion and a high breakdown voltage transistor portion are mixed.

Therefore, as described above, when boron is ion-implanted after forming the field oxide film, the vertical positional relationship between the boron-implanted region and the lower end of the field oxide film changes depending on the size of the element isolation width. Will end up. This point will be specifically described with reference to FIG.

FIG. 6 (a) shows that, of the two types of field oxide films having different film thicknesses formed with two different types of element isolation widths, the ion channel is formed under the condition of forming a better channel stopper in the smaller film thickness. It is a figure which shows the example at the time of injecting.
In FIG. 6A, the silicon substrate 61 is selectively oxidized with the silicon nitride film 63 selectively formed on the silicon substrate 61 via the silicon oxide film 62 as an anti-oxidation film, and the separation width and the film thickness are relatively large. Field oxide film 64a and field oxide film 64b having a relatively small separation width and film thickness
After the formation of and, the photoresist 65 having the openings 66a and 66b on the field oxide films 64a and 64b is used as a mask to form the smaller field oxide film 64b.
The boron 67 is ion-implanted with a relatively small implantation energy (acceleration energy), which forms the boron implantation region 68b immediately below. Then, since the film thickness of the field oxide film 64a is larger than the film thickness of the field oxide film 64b, the field oxide film 64a is formed on the side of the field oxide film 64a.
A boron implantation region 68a is formed inside the. Thus, when the boron implantation region 68a is formed inside the field oxide film 64a, the channel stopper is not formed on the field oxide film 64a side even if the heat treatment is performed later.

FIG. 6B shows an ion under the condition of forming a good channel stopper in the larger film thickness of the two kinds of field oxide films formed with two different kinds of element isolation widths and different in film thickness. It is a figure which shows the example at the time of injecting.
In FIG. 6B, the larger field oxide film 64a is formed by using the photoresist 65 having the openings 66a and 66b on the field oxide films 64a and 64b as a mask.
The boron 67 is ion-implanted with a relatively large implantation energy so that the boron implantation region 68a is formed immediately below. Then, on the side of the field oxide film 64b having the smaller film thickness, the boron implantation region 68b is formed at a position separated from the lower end of the field oxide film 64b. In this way, when the boron implantation region 68b is formed at a position separated from the lower end of the field oxide film 64b, the channel stopper formed by the subsequent heat treatment also functions as the field oxide film 64b.
Since it is formed at a position separated from the lower end of b, conduction of the parasitic transistor cannot be effectively prevented.

That is, when the method of forming a field oxide film and then implanting boron ions as described with reference to FIG. 5 is applied to a semiconductor device having two or more kinds of field oxide films having different film thicknesses. However, no matter how the implantation energy of the ion implantation is controlled, the conduction of the parasitic transistor cannot be prevented with high reliability.

Therefore, even if the object of the present invention is applied to a semiconductor device having at least two kinds of element isolation insulating films having different film thicknesses, a good channel stopper is formed in any region and high reliability is obtained. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of performing element isolation according to the characteristics.

[0017]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises forming at least two kinds of element isolation insulating films having different film thicknesses on a semiconductor substrate, In order to form a channel stopper on the semiconductor substrate in a region adjacent to the lower end of the element isolation insulating film, an implantation energy corresponding to the thickness of the element isolation insulating film is used for each type of the element isolation insulating film. Impurity is ion-implanted.

From another point of view, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming at least two kinds of field oxide films having different film thicknesses on a semiconductor substrate by a LOCOS method, and a step of forming on the field oxide film. Forming a coating pattern having openings; and using the coating pattern as a mask, adjoining the lower end of the field oxide film with implantation energy according to the film thickness of the field oxide film for each type of the field oxide film. Implanting impurities into the semiconductor substrate in the region.

From another point of view, in the method of manufacturing a semiconductor device of the present invention, at least two semiconductor substrates having different depths are provided.
A step of forming different kinds of trenches, a step of forming at least two kinds of insulating films for element isolation having different film thickness so as to fill the trenches, and a coating pattern having openings on the insulating film for element isolation. And a region adjacent to the lower end of the element isolation insulating film with the implantation energy corresponding to the thickness of the element isolation insulating film for each type of the element isolation insulating film, using the coating pattern as a mask And ion-implanting impurities into the semiconductor substrate.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

The first embodiment of the present invention is an example of the case where element isolation is performed by the LOCOS method, and the manufacturing process thereof is shown in FIG. First, as shown in FIG. 1A, a silicon oxide film 2 having a film thickness of about 20 nm is formed on a silicon substrate 1 by a thermal oxidation method, and then a film thickness of 10 nm is formed on the silicon oxide film 2.
A silicon nitride film 3 having a thickness of 0 to 300 nm is formed by a chemical vapor deposition method (CVD method).

Next, as shown in FIG. 1B, the silicon nitride film 3 is selectively removed by etching using a patterned photoresist (not shown) as a mask. An opening 4a having a width of about 0.5 μm and an opening 4b having a width of about 0.25 μm are formed.
It should be noted that three or more types of openings having different widths may be formed.

Next, as shown in FIG. 1C, the remaining silicon nitride film 3 is used as a mask to selectively oxidize the silicon nitride film 3 at a temperature of 1000 ° C. for 100 minutes in a water vapor atmosphere to form openings 4a in the silicon nitride film 3. The silicon substrate 1 under 4b is thermally oxidized to form field oxide films 5a and 5b for element isolation, respectively. At this time, the film thickness of the field oxide film 5a formed in the opening 4a is about 500 nm,
The film thickness of the field oxide film 5b formed in the opening 4b is about 400 nm.

Next, as shown in FIG. 1D, after the photoresist 6 is applied on the entire surface, the field oxide films 5a and 5b of the photoresist 6 are formed by the photolithography technique.
Form an aperture in the upper part. Then, using the photoresist 6 as a mask, the dose amount is 1 × 10 ¹² to 2 × 10 ¹³ (i
acceleration energy of boron ions 7 of about ons / cm ² ) 190
Inject at keV. By this ion implantation, a boron implantation region 8a is formed in the silicon substrate 1 in a region adjacent to the lower end of the field oxide film 5a, and a boron implantation region is formed in the silicon substrate 1 in a region separated by about 100 nm from the lower end of the field oxide film 5b. 8b is formed. In addition,
In addition to the photoresist 6, a film made of a material serving as a mask material for the boron ions 7 can be used.

The general relationship between the range of impurities (boron, phosphorus, arsenic, antimony) in the silicon oxide film (SiO ₂ film) and the acceleration energy of ion implantation will be described with reference to FIG. To do. In FIG. 2, the vertical axis represents the range of impurities in the silicon oxide film (unit: μm)
And the horizontal axis represents the acceleration energy of ion implantation (unit: keV). As is clear from this figure,
The range of impurities increases uniformly as the acceleration energy increases, and the acceleration energy and the range have a one-to-one relationship for each type of impurities. Therefore, by controlling the acceleration energy, the implantation depth of impurities can be controlled arbitrarily. In this embodiment, the boron in the boron-implanted region 8b has not only passed through the field oxide film 5b, which is a silicon oxide film, but also through the silicon substrate 1, but the silicon oxide film and the silicon substrate are impurities. Since there is no great difference in range, the position where the boron-implanted region 8b is formed can also be obtained from only the relationship shown in FIG.

Next, using the photoresist 6 as a mask,
Boron ions 7 with a dose amount of about 1 × 10 ^{12 to} 2 × 10 ¹³ (ions / cm ² ) are implanted at an acceleration energy of 150 keV.
By this ion implantation, a boron implantation region 9a is formed inside the field oxide film 5a, and a boron implantation region 9b is formed in the region adjacent to the lower end of the field oxide film 5b in the silicon substrate 1. Note that the film thickness is different 3
When forming more than one kind of field oxide film, boron may be ion-implanted with acceleration energy such that a boron-implanted region is formed in the silicon substrate in a region adjacent to the lower end of the field oxide film.

Next, as shown in FIG. 1E, after removing the photoresist 6 by ashing, the silicon nitride film 3 is wet-etched with a hot phosphoric acid solution. Then, the silicon oxide film 2 is wet-etched with a hydrofluoric acid solution. Through the steps up to this point, the structure of the element isolation region is completed. Thereafter, a gate oxide film 12 is formed on the silicon substrate 1 in the element region, a gate electrode 13 made of a polycrystalline silicon film is patterned, and ion implantation is performed using the gate electrode 13 as a mask to form a silicon substrate. A pair of impurity diffusion layers 14 having a conductivity type opposite to that of 1 and serving as a source and a drain are formed on the surface of the silicon substrate 1 on both sides of the gate electrode 13. Through the steps so far, the MOS transistor is formed in the element region.

In addition, during this time, for example, by heat treatment performed to form the impurity diffusion layer 14, the boron-implanted region 8 is formed.
a, 8b, 9b are activated, and these regions become channel stoppers 10a, 10b, 11 respectively. The channel stopper 10a is formed on the silicon substrate 1 in a region adjacent to the lower end of the field oxide film 5a, and the channel stoppers 10b and 11 are integrated by connecting the regions to each other and are adjacent to the lower end of the field oxide film 5b. Is formed on the silicon substrate 1. The boron implantation region 9a formed inside the field oxide film 5a does not become a channel stopper even by the heat treatment.

As described above, in this embodiment, boron is ion-implanted twice with acceleration energy corresponding to each of the two types of field oxide films 5a and 5b having different film thicknesses. Channel stoppers 10a, 10b, and 11 can be formed in the silicon substrate 1 in the regions adjacent to the respective lower ends of 5b. Therefore, even if there is a wiring in the upper layer, the potential of this wiring does not form a parasitic channel under the field oxide films 5a and 5b, and it is possible to reliably prevent the parasitic transistor from conducting. You can Further, since the boron 7 is implanted using the photoresist 6 as a mask, the boron implantation regions 8a, 8b, 9a, 9b can be formed in the central portions of the field oxide films 5a, 5b, so that the boron implanted by the subsequent heat treatment can be formed. Even if a little diffuses, the boron does not spread to the element region, and the narrow channel effect does not occur.

In this embodiment, the boron implantation region 8 is used.
Although the boron-implanted regions 9a and 9b are formed after forming a and 8b, the order of ion implantation may be reversed. Further, as a modified example of the element isolation by the LOCOS method as in the present embodiment, a polysilicon buffer LOCOS in which a polycrystalline silicon film is formed under a silicon nitride film as an antioxidant film.
Element isolation may be performed by the S method. Further, the impurities to be ion-implanted are not limited to boron, and impurities having the same conductivity type as that of the silicon substrate 1, for example, phosphorus, arsenic, antimony, etc. can be used by utilizing the relationship shown in FIG.

Next, regarding the second embodiment of the present invention,
This will be described with reference to FIG.

The second embodiment of the present invention is an example of a case where element isolation is performed by a trench (groove) isolation method, and its manufacturing process is shown in FIG. First, as shown in FIG. 3A, a silicon nitride film 3 having a film thickness of about 100 to 300 nm is formed on a silicon substrate 1 by a CVD method. Thereafter, the patterned photoresist (not shown) is used as a mask to selectively remove the silicon nitride film 3 by etching, so that the silicon nitride film 3 has a width of 0.5.
An opening 4a of about μm and an opening 4b of about 0.25 μm in width are formed. The silicon substrate 1 and the silicon nitride film 3
A silicon oxide film 2 having a film thickness of about 20 nm may be formed between and by a thermal oxidation method.

Next, as shown in FIG. 3 (b), anisotropic etching using SF ₆ gas is performed using the remaining silicon nitride film 3 as a mask to form a trench 21 having a width of about 0.5 μm and a width of 0.5 μm. A trench 22 of about 0.25 μm is formed in the silicon substrate 1. At this time, if etching is performed so that the depth of the trench 21 is about 500 nm, the depth of the trench 22 is only about 400 nm. It is considered that this is because the width of the trench 22 is small, so that SF ₆ gas hardly enters the trench 22 in the process of forming the trench 22. Further, for the same reason as this, the trench 22 has a tapered shape that opens upward.

Next, as shown in FIG. 3C, after removing the silicon nitride film 3, a film thickness of 600 to 600 is formed on the entire surface of the silicon substrate 1 by the CVD method so as to completely fill the trenches 21 and 22. A silicon oxide film 23 having a thickness of about 800 nm is formed.

Next, as shown in FIG. 3D, a photoresist (not shown) is applied to the entire surface, and then etched back until the silicon substrate 1 is exposed, so that the trenches 21 and 22 are formed. Silicon oxide film 23 for element isolation
The substrate surface is flattened so that a and 23b respectively remain. As a result, the film thickness of the silicon oxide film 23a formed in the trench 21 becomes about 500 nm, and the film thickness of the silicon oxide film 23b formed in the trench 22 becomes 4 nm.
It becomes about 00 nm. The planarization may be performed by another method such as a chemical mechanical polishing method (CMP method).

Next, as shown in FIG. 3E, a photoresist 24 is applied to the entire surface and then the silicon oxide film 23a of the photoresist 24 is formed by photolithography.
An opening is formed in a portion above 23b. Then, using the photoresist 24 as a mask, the dose amount is 1 × 10 ¹² to 2 ×.
Boron ions 7 of about 10 ¹³ (ions / cm ² ) are implanted with an acceleration energy of 190 keV. By this ion implantation, a boron implantation region 8a is formed in the silicon substrate 1 in a region adjacent to the lower end of the silicon oxide film 23a, and a boron implantation region is formed in the silicon substrate 1 in a region separated by about 100 nm from the lower end of the silicon oxide film 23b. 8b is formed.

Next, using the photoresist 24 as a mask, boron ions 7 with a dose amount of about 1 × 10 ¹² to 2 × 10 ¹³ (ions / cm ² ) are implanted at an acceleration energy of 150 keV. By this ion implantation, a boron-implanted region 9a is formed inside the silicon oxide film 23a, and the silicon substrate 1 in a region adjacent to the lower end of the silicon oxide film 23b is formed.
A boron-implanted region 9b is formed at.

Next, as shown in FIG. 3F, after removing the photoresist 6 by ashing, the silicon nitride film 3 is wet-etched with a hot phosphoric acid solution. Through the steps up to this point, the structure of the element isolation region is completed. After that, a gate oxide film 12 is formed on the silicon substrate 1 in the element region, and then a gate electrode 13 made of a polycrystalline silicon film is pattern-formed.
Is used as a mask to form a pair of impurity diffusion layers 14 having a conductivity type opposite to that of the silicon substrate 1 and serving as a source / drain, on both sides of the gate electrode 13.
Form on the surface. By the process up to here, M
An OS transistor is formed.

In addition, during this time, for example, by heat treatment performed to form the impurity diffusion layer 14, the boron-implanted region 8 is formed.
a, 8b, 9b are activated, and these regions become channel stoppers 10a, 10b, 11 respectively. The channel stopper 10a is formed on the silicon substrate 1 in a region adjacent to the lower end of the silicon oxide film 5a, and the channel stoppers 10b and 11 are integrated by connecting the regions to each other and are adjacent to the lower end of the silicon oxide film 5b. Is formed on the silicon substrate 1. The silicon oxide film 5
The boron-implanted region 9a formed inside a does not function as a channel stopper even by heat treatment.

As described above, in this embodiment, two types of element isolation silicon oxide films 23a and 23b having different film thicknesses are used.
By implanting boron twice with the acceleration energy corresponding to each of the two,
The channel stoppers 10a, 10b, 11 can be formed in the silicon substrate 1 in the regions adjacent to the respective lower ends of 23b. Therefore, even if wiring is present in the upper layer, the potential of this wiring causes the silicon oxide film 23a,
Since a parasitic channel is not formed under 23b, it is possible to reliably prevent the parasitic transistor from conducting. Also, using the photoresist 6 as a mask, boron 7 is used.
Is implanted, the boron implantation regions 8a, 8b, 9
Since a and 9b can be formed in the central portions of the silicon oxide films 23a and 23b, even if the implanted boron is diffused to some extent by the subsequent heat treatment, the boron does not spread to the element region and a narrow channel effect occurs. Absent.

In the first and second embodiments, L
Although the present invention is applied to the OCOS method and the trench isolation method, the present invention can also be applied to the manufacture of a semiconductor device in which elements are isolated by both the LOCOS method and the trench isolation method.

[0042]

As described above, according to the present invention,
A channel stopper is formed in a semiconductor substrate in a region adjacent to each lower end of the element isolation insulating film by ion-implanting impurities a plurality of times with implantation energy corresponding to each of at least two types of element isolation insulating films having different film thicknesses. Can be formed. Therefore, even if there is a wiring in the upper layer, the potential of this wiring does not form a parasitic channel under the insulating film for element isolation, and it is possible to reliably prevent the parasitic transistor from conducting. it can.
Therefore, a good channel stopper is formed in any region, and element isolation can be performed with high reliability.

Further, since the impurities are implanted using the covering pattern as a mask, the impurities can be formed in the central portion of the element isolation insulating film. Therefore, even if the implanted impurities are diffused to some extent by the subsequent heat treatment, the impurities can be diffused. Does not extend to the element region, and the narrow channel effect does not occur. Therefore, the semiconductor element can be further miniaturized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a graph showing the relationship between the range of impurities in a silicon oxide film and the acceleration energy.

FIG. 3 is a cross-sectional view for explaining the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps.

FIG. 4 is a cross-sectional view for explaining the conventional method for manufacturing a semiconductor device in the order of steps.

FIG. 5 is a cross-sectional view for explaining another conventional method of manufacturing a semiconductor device in the order of steps.

FIG. 6 is a cross-sectional view for explaining a problem of the method shown in FIG.

[Explanation of symbols]

 1 Silicon substrate 2 Silicon oxide film 3 Silicon nitride film 5a, 5b Field oxide film (insulating film for element isolation) 6 Photoresist (covering pattern) 7 Boron ion 8a, 8b, 9a, 9b Boron implantation region 10a, 10b, 11 channels Stoppers 23a, 23b Silicon oxide film (insulating film for element isolation)

Claims (3)

[Claims] 1. A channel stopper is formed on the semiconductor substrate in a region adjacent to a lower end of the element isolation insulating film after forming at least two kinds of element isolation insulating films having different film thicknesses on the semiconductor substrate. As described above, the method for manufacturing a semiconductor device is characterized in that the impurities are ion-implanted with the implantation energy according to the thickness of the element isolation insulating film for each type of the element isolation insulating film. 2. A step of forming at least two kinds of field oxide films having different film thicknesses on a semiconductor substrate by a LOCOS method, a step of forming a covering pattern having openings on the field oxide film, and the covering pattern. Using as a mask, with the implantation energy corresponding to the film thickness of the field oxide film for each type of the field oxide film, impurities are ion-implanted into the semiconductor substrate in a region adjacent to the lower end of the field oxide film. A method of manufacturing a semiconductor device, comprising: 3. A semiconductor substrate having at least two different depths.
A step of forming different kinds of trenches, a step of forming at least two kinds of element isolation insulating films having different film thicknesses so as to fill the trenches, and a coating pattern having openings on the element isolation insulating film. And a region adjacent to the lower end of the element isolation insulating film with implantation energy corresponding to the film thickness of the element isolation insulating film for each type of the element isolation insulating film using the coating pattern as a mask And a step of ion-implanting impurities into the semiconductor substrate.