JPH07106557A - Semiconductor device and manufacture of the same - Google Patents

Abstract

PURPOSE:To realize low resistance of a gate electrode by selectively allowing a tungsten film to grow on the surface of a polycrystalline silicon in the same width after forming a gate electrode consisting of polycrystalline silicon in the same width as an inlet of a recessed area formed on a substrate. CONSTITUTION:After a recessed area is formed on a substrate, the entire surface is etched and a polycrystalline silicon 9 is embedded in a groove. Tungsten 11 is caused to selectively grow on the surface of the polyscrystalline silicon. Tungsten grows only into the area where the polycrystalline silicon surface is exposed and does not grow at the surface of an insulating film 8. Therefore, tungsten grows only at the surface of the gate electrode 9 with limitation in the vertical direction of the groove and does not grow in lateral direction due to existence of the groove. Since the selectively grown tungsten having sufficient thickness can be used, a resistance of the gate electrode mainly composed of polycrystalline silicon can be reduced to about 1/10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a metal-oxide film-semiconductor type field effect semiconductor device which can be miniaturized and which utilizes a recess formed on the surface of a substrate. Metal Oxide Semiconductor field effec
t transistor; hereinafter abbreviated as MOSFET) and its manufacturing method.

[0002]

2. Description of the Related Art A dynamic random access memory, which is a typical example of an integrated circuit using silicon, is currently
Mass production of 4 megabits is carried out using 0.8 μ technology. In addition, 16-megabits, which uses the next-generation 0.5μ technology, have started to be mass-produced on a small scale. There is no doubt that semiconductor devices will be reduced in size and the degree of integration will be improved in combination with advances in fine processing technology.

By the way, the miniaturization of semiconductor devices has not been achieved merely by reducing the size, but the undesirable effects such as the short channel effect and the punch-through phenomenon, which become remarkable as the size is reduced, are effective. This is also the result of the effective suppression. The guideline in this case is the proportional reduction rule, and according to this, as the size is reduced, the substrate concentration is increased, the gate oxide film is thinned, and the diffusion layer of the source / drain is made shallow. Semiconductor devices, especially M
In order to miniaturize the OS type field effect element, it is unavoidable to follow this guideline, but it is a fact that the factor for inhibiting miniaturization is becoming clear.

For example, the thinning of the gate oxide film has a limit determined by the tunnel leak current, which is said to be about 3 to 4 nm. In addition, the depth of the source / drain diffusion layer is as long as it is formed by the current ion implantation.
There is a limit to shallow junction formation, and it is difficult to achieve 50 nm or less even in the case of arsenic which is an impurity for forming an n-type diffusion layer. Boron, which makes a p-type diffusion layer, has a large diffusion coefficient, making it difficult to realize a shallow junction.
The degree is said to be the limit.

Regarding the substrate concentration, which is another parameter for miniaturization, the increase of the concentration suppresses the extension of the depletion layer from the source / drain, so that the element size can be reduced accordingly. However, increasing the concentration of the entire substrate causes an increase in the threshold voltage, an increase in the junction capacitance formed by the junction between the diffusion layer and the substrate, and the like, which causes deterioration of the device characteristics.

Since the depletion layer from the drain region spreads inside the substrate away from the gate electrode, in order to suppress this, only the concentration inside the substrate needs to be increased. Therefore,
Up to now, as shown in Japanese Patent Laid-Open No. 62-271450 (an example is shown in FIG.
(Not the same as in 1450), the impurity layer 7 having a peak near the ends of the source / drain diffusion layers 12 and 14 is formed to suppress the extension of the depletion layer and maintain the substrate surface at a low concentration. Therefore, a structure for controlling the rise of the threshold voltage has been proposed. By this method, it was possible to achieve both suppression of the short channel effect and lowering of the threshold voltage up to a gate electrode size of about 0.3 μm. In particular, lowering the threshold voltage is very important for improving the device performance in view of the fact that the power supply voltage must be reduced with the miniaturization of the device dimensions.

In order to further miniaturize this structure, the impurity layer 7 must have a steeper distribution and a peak position closer to the surface. This is because the diffusion layers 12 and 14 also become shallower in accordance with the miniaturization, and the region where the depletion layer projects is closer to the surface. However, since the distribution of the impurity layer 7 has a spread determined by the characteristics of ion implantation, it is impossible to increase only the concentration inside the substrate while keeping the surface at a low concentration.

Therefore, from now on, a semiconductor device capable of structurally suppressing the extension of the depletion layer from the drain region is needed in addition to simply adjusting the impurity concentration distribution of the substrate.

In FIG. 3, 1 is a semiconductor substrate and 2 is a semiconductor substrate.
Is an element isolation oxide film, 3 is a high concentration impurity layer for improving the element isolation characteristics, 7 is a high concentration impurity layer for suppressing the extension of the depletion layer from the drain, 8 is a gate insulating film, 9 is a gate electrode, Reference numeral 11 'is a silicide layer, 12 and 14 are diffusion layers, 13 is a side wall insulating film of a gate electrode, 15 is an interlayer insulating film, 16 is a metal filling a contact hole, and 17 is a wiring metal.

One of the MOSFET candidates that can structurally suppress the extension of the depletion layer is described in Japanese Unexamined Patent Publication No. Sho 50-8483, which is a trench gate in which a trench is formed in the substrate and the periphery thereof is used as a channel. Type MOSFET. In Figure 4,
A cross-sectional view of one example is shown, but this is
It is not the same as the structure described in 50-8483.

In this way, the diffusion layer 12 is formed by digging a groove in the substrate.
By dividing the gate electrode 9 by the gate electrode 9, the effective channel dimension (distance traveled by carriers) can be increased even if the planar gate electrode dimension is the same. In addition to this effect, since the diffusion layer regions 12 and 14 of the source and drain are completely separated by the trench gate, the extension of the depletion layer from the drain region is suppressed, and the conventional structure shown in FIG. Type MOSFET has a structural advantage that a short channel effect is less likely to occur. By utilizing these effects, as compared with the conventional structure of FIG. 3, the impurity layer 9 inside the substrate is not made to have a too high concentration, that is, the threshold voltage and the parasitic capacitance are not increased, and a short time is obtained. The channel effect can be suppressed.

As described above, it is necessary to suppress the short channel effect without depending on the increase of the substrate concentration by making a device for the structure of the gate electrode. This groove gate type MOSF
It can be said that ET is the most promising candidate. However, in the structure of FIG. 4 in which the groove is simply dug, as described above, the effective gate dimension becomes long, and it is difficult to form a channel at the corner portion of the groove gate due to electric field concentration. Therefore, there is a drawback that the drain current is reduced. Furthermore, the increase in effective gate size means increase in gate capacitance, which, together with the decrease in current, causes a problem of increase in delay time when the circuit is configured. . In this case, by reducing the size, the advantage of the semiconductor element which has improved the circuit performance is lost, and there is no point in miniaturization.

In the trench gate type MOSFET shown in FIG. 4, a diffusion layer 12 is formed in advance in the active region surrounded by the element isolation oxide film 3 by using an impurity introduction technique typified by ion implantation. The method of dividing this with a groove is generally used. Therefore, the depth of the groove must be sufficiently deeper than the depth of the diffusion layer, which results in a decrease in drain current due to an increase in channel size, as described above. Further, when a diffusion layer is formed on the entire surface of the active region, a part of the diffusion layer is formed along the edge of the element isolation oxide film,
Diffuses under the oxide film. As shown in the figure, the element isolation oxide film has a shape such that the film thickness becomes thinner toward the active region.Therefore, if impurities are present in this portion, the oxide film will be formed when the trench is dug. It becomes a mask and impurities are likely to remain. If impurities remain, the diffusion layer will be connected,
Normal MOSFET operation cannot be obtained.

It is possible to put a mask around the element isolation oxide film so as to prevent impurities from entering at the time of ion implantation, but it is obvious that there is no room to put the mask in a fine element.

Therefore, as disclosed in Japanese Patent Application Laid-Open No. 4-346476, a groove is formed in the substrate using the insulating film deposited on the substrate as a mask, and the gate electrode is embedded in the groove to form a mask. There is proposed a manufacturing method in which the insulating film is removed, and further an impurity for forming a diffusion layer is implanted using the gate electrode as a mask. According to this, since the formation of the diffusion layer is the same as that of the conventional MOSFET, the depths of the diffusion layer and the groove can be adjusted by adjusting the energy of ions, and the leakage along the periphery of the element isolation oxide film can be adjusted. The current problem can be avoided.

[0016]

As described above, some problems caused by the groove gate structure can be solved by burying the gate electrode in the groove. However, in the method of burying the gate electrode in the groove, the gate electrode is It is impossible to reduce the resistance by forming a laminated film. This reduction in the resistance of the gate electrode is becoming more important as the gate electrode becomes finer, and even now, as shown in the conventional structure MOSFET of FIG. 3, silicide is formed only on the surface of the gate electrode and the surface of the diffusion layer. Forming layers is being done. Although not shown in the drawing, a polycide film or the like, which is a laminated film of a polycrystalline silicon film and a silicide film, is also used.

In the structure in which the gate electrode is embedded in the groove, as described above, the diffusion layer can be formed in the same manner as in the conventional MOSFET. Therefore, as shown in FIG. 3, the silicide layer is formed on the surface of the gate electrode and the surface of the diffusion layer. It's easy to do.
However, with the shallow junction of the diffusion layer, the silicide layer is also thinned, and the silicide film is no longer thick enough to reduce the resistance of the gate electrode.

[0018]

In the present invention, as shown in FIG. 1, the diffusion layers 12 and 1 are formed by the recesses formed in the substrate.
In a trench gate type MOSFET that divides into 4 parts, as shown in FIG. 1, a gate electrode 9 made of polycrystalline silicon having a width substantially equal to the width of the entrance of the recess is formed. By selectively growing the tungsten film 11 having a width almost equal to
The low resistance of the gate electrode of the OSFET is realized.

In order to form this structure, as described in detail in Examples to be described later, a groove is formed in an insulating film deposited on the surface of the substrate, and a recess is formed in the substrate using this insulating film as a mask. After the gate insulating film is grown, polycrystalline silicon is embedded in the groove so that it is lower than the insulating film, and tungsten is selectively grown only on the surface of the polycrystalline silicon to complete the groove. The process of backfilling is carried out.

The tungsten film does not grow except in the trench in which the polycrystalline silicon is buried. Further, since tungsten starts to grow from the surface of polycrystalline silicon, it grows along the width of the groove.

[0021]

With the semiconductor device of the present invention, the trench gate type MO
It becomes possible to solve the problem of SFET, and moreover,
A MOSFET that combines the advantages of conventional MOSFETs can be realized.

A conventional trench gate type MOSF has a structure in which a tungsten film is selectively grown on a polycrystalline silicon film.
It is possible to reduce the resistance of the gate electrode, which was difficult to realize with ET. In addition, the method of completely embedding the gate electrode in the trench makes it possible to form a diffusion layer that will become the source / drain after the gate electrode is formed. The problem of leakage current can be completely solved. Further, in the present invention, the excellent short channel characteristics, which are the characteristics of the trench gate type, and the characteristics that the parasitic capacitance is small are maintained. Furthermore, FIG.
The cross section of CMOS (Complementary MOS) is shown in
In the semiconductor device of the present invention, like the conventional MOSFET, since the source and drain are formed after the gate electrode is formed, impurities can be easily implanted by ion implantation, and CMOS formation is easy. It also has features.

[0023]

Embodiments of the present invention will be described in detail below with reference to FIGS. In this description, an n-type MOSFET
However, if the conductivity types of the substrate and the impurity region are reversed, a p-type MOSFET is obtained.

As shown in FIG. 5A, the element isolation oxide film 2 is grown on the semiconductor substrate 1 by using a known selective oxidation method. Specifically, the surface of the semiconductor substrate 1 has a thickness of 20 nm.
An oxide film is grown to a certain degree, and a nitride film is further deposited thereon by a known low pressure vapor deposition method, and then this nitride film is processed into a desired shape. The film thickness of the nitride film is about 100 nm. Next, by using a known ion implantation method, impurities are formed on the entire surface of the semiconductor substrate to form a region having the same conductivity type as the substrate. Specifically, BF ₂ is 5 × 10 ¹³ at 60 KeV.
I typed in / cm ² . At this time, no ions are implanted into the area where the nitride film is formed.

When this semiconductor substrate is exposed to an oxidizing atmosphere,
The oxide film 2 grows on the surface of the semiconductor substrate not covered with the nitride film. In this example, the oxide film 2 having a thickness of about 300 nm was grown by oxidizing in an atmosphere containing water vapor at 1100 ° C. for 30 minutes. Prior to the oxidation, heat treatment was performed for 10 minutes in a nitrogen atmosphere to diffuse the implanted boron 3 into the substrate. The high-concentration layer of boron improves element isolation characteristics. After that, the nitride film serving as a mask for selective oxidation is removed with a phosphoric acid solution heated to about 180 ° C., and further,
When the oxide film underlying the nitride film is removed with a hydrofluoric acid solution, the result shown in FIG.
The sectional view shown in FIG.

Next, as shown in FIG. 5B, an oxide film 4 having a thickness of about 5 nm is grown on the surface of the semiconductor substrate, and a 30 nm nitride film 5 and a 200 nm oxide film 6 are further formed thereon. accumulate. A known thermal oxidation method was used for growing the oxide film 4, and a known vapor layer growth method was used for depositing the nitride film 5 and the oxide film 6.

Next, as shown in FIG. 5C, a groove is formed in the oxide film on the substrate. For this, a mask formation by a known photolithography method and a dry etching technique for the insulating film were used. Although the width of the groove is determined by the size of the MOSFET required, the groove of about 0.2 μm is opened in this embodiment.

Further, as shown in FIG. 5D, a recess is formed in the substrate by using the insulating film having the groove as a mask. The dry etching technique of silicon was also used for the formation of the recess. Further, at this time, control was performed so that the corners of the groove were rounded. This is to prevent the electric field from being concentrated due to the acute angle of the groove.

Next, as shown in FIG. 5E, impurities that form a region of the same conductivity type as the substrate are ion-implanted through the opening of the groove so as to have a higher concentration than that of the substrate. Specifically, 1x BF ₂ with an energy of ₂₀ KeV
Implantation was performed with a dose amount of 10 ¹² / cm ² to 5 × 10 ¹² / cm ³ . This impurity layer is necessary for adjusting the threshold voltage of the MOSFET and suppressing the extension of the depletion layer from the drain. However, as described above, the groove gate type MOSFE
At T, the extension of the depletion layer is effectively suppressed by the effect of the corner of the groove.
It may be smaller than the SFET. In addition, p-type MOSF
In the case of ET, arsenic ions are implanted.

After removing the contaminants and the like caused by the ion implantation, the gate oxide film 8 is removed by 5 times as shown in FIG. 6 (a).
nm, and impurities (specifically phosphorus)
Is deposited in a high concentration, and a resist film 10 is applied. The film thickness of polycrystalline silicon is
0.15 to completely fill the 0.2 μm groove.
μm. Further, the resist film 10 is applied in order to make the surface of the substrate flat in advance when the entire surface is etched as described later.

Next, as shown in FIG. 6B, the entire surface is etched to fill the inside of the trench with the polycrystalline silicon 9. Then, tungsten 11 is selectively grown on the surface of this polycrystalline silicon. Tungsten grows only in the region where the surface of the polycrystalline silicon is exposed and does not grow on the surface of the insulating film. Therefore, tungsten grows only on the surface of the gate electrode. Also, its growth is restricted in the longitudinal direction of the trench and does not grow laterally due to the presence of the trench, so the sidewalls of the tungsten are very smooth.

Next, using the tungsten film as a mask, the insulating film in which the groove has been formed is etched into a shape as shown in FIG. 6C. At this time, since the nitride film 5 functions as a stopper for etching the oxide film 6, the element isolation oxide film is not removed.

Next, as shown in FIG. 6D, after the nitride film 5 is also removed, ion implantation is performed to form a diffusion layer. Here, arsenic is 1 × 10 at 20 KeV.
^I hit ¹⁵ / cm ² . In addition, the implantation conditions were set so that the depth of the diffusion layer and the depth of the recess were substantially the same.

Next, as shown in FIG. 7A, a sidewall insulating film is formed on the sidewalls of the gate electrodes 9 and 11 by using known insulating film deposition and anisotropic etching thereof. Then, in order to lower the resistance of the diffusion layer and further reduce the contact resistance with the wiring metal, arsenic was again added at 5 × 10 5 at 30 KeV.
^I hit ¹⁵ / cm ² .

Finally, in order to activate the impurity region,
Heat treatment is applied, and further, the interlayer insulating film 15, the metal 16 filling the contact hole, and the wiring layer 17 are formed to complete the semiconductor device of the present invention.

One of the characteristics of forming the gate electrode in the present invention is that the gate electrode is embedded in the groove. As described above, in the case where the width of the groove is small and the deposited polycrystalline silicon film completely fills the groove, a well-known whole surface etching technique is used to embed the gate electrode inside the groove. be able to.

However, the size of the gate electrode is the same LSI
Since there are differences on the chip as well, the groove is not always completely backfilled with the gate electrode. Therefore, a method of embedding the gate electrode in the groove will be described below when the width of the gate electrode is large. Since such a situation occurs in a place where a contact hole is formed on the gate electrode, an example of forming a wide gate region on the element isolation oxide film will be described here.

First of all, as shown in FIG.
A substrate on which an element isolation oxide film is formed is prepared. On this surface, as shown in FIG. 8B, laminated insulating films 5 and 6 for forming grooves are deposited. The type of insulating film is as described above. Grooves are formed in the laminated insulating films 5 and 6 as shown in FIG. At this time, it is necessary to set etching conditions so that the etching of the oxide film 6 stops at the nitride film 5 so that no trench is formed in the element isolation oxide film 3. After that, in the active region where the substrate is exposed, a step of forming a groove in the substrate is performed, but the element isolation oxide film is not affected.

Next, as shown in FIG. 8D, a polycrystalline silicon film 9 is deposited, and an organic film 10 is further applied to flatten the surface. Then, do a full etch,
When the polycrystalline silicon film deposited on the surface of the insulating film is removed and further the organic film filling the inside of the groove is removed, as shown in FIG. 9A, the inside of the wide groove is removed. Also, the gate electrode can be filled with the same width as the groove. Further, similar to the steps described so far, the selective growth of the tungsten film 11 (FIG. 9b) and the formation of the sidewall insulating film 13 (FIG. 9c) are performed, and as shown in FIG. Forming a wiring in contact with.

As described above, by using the flattening with the organic film, the gate electrode can be embedded also inside the grooves having different widths.

In the above embodiment, one conductivity type M
The case of manufacturing the OSFET has been described. Hereinafter, a case of manufacturing semiconductor devices of the present invention having different conductivity types on the same substrate will be described.

In the complementary MOSFET, it is necessary to form regions of different conductivity types (hereinafter referred to as wells) on the same substrate, but in this embodiment, a known method was used.

In order to form well regions having different conductivity types, first, as shown in FIG. 10A, the substrate 1 (p
An oxide film 4'is grown on the surface of the mold), and a nitride film 5'is further deposited. The oxide film has a thickness of 10 to 20 nm, and the nitride film has a thickness of 150 nm.

As shown in FIG. 10B, this nitride film 5'is processed into a desired shape by a dry etching method using a photoresist mask 20. At this time, it is necessary to leave the oxide film 4'on the surface.

Next, as shown in FIG. 10C, phosphorus is ion-implanted (21) using the nitride film as a mask to form an n-type well. Driving energy is 1
The implantation amount is 1 × 10 ¹³ / cm ³ at 25 KeV.
At this time, since the remaining nitride film 5 ′ serves as a mask for ion implantation, phosphorus ions are not implanted in the region where the nitride film exists.

Furthermore, when contaminants and the like due to ion implantation are removed and the substrate is placed in an oxidizing atmosphere, FIG.
As shown in, the selective oxidation occurs in which the oxide film 3'grows only in the region without the nitride film 5 ', that is, in the region where phosphorus is ion-implanted. In this embodiment, the thickness of the oxide film is 100 nm. This film thickness is set in consideration of boron ion implantation conditions described below.

Next, as shown in FIG. 11A, after the nitride film is selectively removed, B is formed in order to form a p-type well.
F ₂ was ion-implanted with 60 KeV at about 1 × 10 ¹³ / cm ³ (22). The n-well region where phosphorus is implanted is
Since it is masked by the oxide film 3 ', boron is not implanted.

When this substrate is heat-treated, the implanted impurities diffuse toward the inside of the substrate, so that FIG.
A well region as shown in FIG. Well depth is 3
To 4 μm.

Next, in order to grow an element isolation oxide film, as shown in FIG. 11C, the surface is oxidized by about 10 nm to form an oxide film 4 ', and further a nitride film 5'is formed. accumulate. Then, as shown in FIG. 11D, the photoresist film 20 is used to process the nitride film into a desired active region shape. Further, as shown in FIG. 12A, when the oxide film 2 is grown, the oxidation selectively progresses, and the element isolation oxide film 2 grows in a region not covered with the nitride film 5 '.
The film thickness is 400 nm.

In the actual manufacture of an LSI, in order to improve element isolation characteristics after growing an element isolation oxide film,
Impurities that form a region of the same conductivity type as the substrate are ion-implanted near the interface between the element isolation oxide film and the substrate. However, in this embodiment, this step is omitted to simplify the description.

The subsequent steps are as described in the first embodiment. First, the stacked insulating films 5 and 6 shown in FIG. 12B are deposited, the grooves shown in FIG. 12C are formed, 12
In (d), the high-concentration impurity regions 7 and 7'are formed, the gate oxide film 8 is grown, and the gate electrodes 9 and 11 are buried.
Then, the laminated insulating film of FIG. 13A is removed, and FIG.
The diffusion layers 12 and 14 and the side wall insulating film 13 are formed, and wiring is formed as shown in FIG. 13C to complete the semiconductor device of this embodiment.

[0052]

The following effects can be obtained by using the semiconductor device and the manufacturing method thereof according to the present invention.

First, by adopting the trench gate structure, it is possible to suppress the occurrence of the short channel effect, which is the greatest problem in the fine MOSFET. This is because the channel length is effectively lengthened by digging the groove and a shallow diffusion layer is formed. In the conventional type, it is necessary to make the ion implantation energy extremely small in order to form a shallow diffusion layer, which leads to an increase in device cost. On the other hand, when the semiconductor device of the present invention is used, a conventional ion implantation device can be used, so that it is not necessary to invest new equipment. .

Secondly, there is an effect that a metal such as tungsten can be used for a part of the gate electrode. Since, as in the present invention, selectively grown sufficiently thick tungsten can be used, it is possible to realize a gate resistance of about 1/10 that of a gate electrode mainly made of polycrystalline silicon. This can suppress an increase in gate resistance, which becomes remarkable as the gate electrode is miniaturized.

Further, by filling a part of the gate electrode in the groove, the shape of the metal such as tungsten which is difficult to process is defined by the shape of the groove, and the variation of the gate dimension due to the processing can be suppressed. You can

Further, since the process after forming the trench gate electrode, that is, the formation of the diffusion layer is exactly the same as that of the conventional MOSFET, the CMOS structure is realized by forming the diffusion layer differently as in the conventional MOSFET. There is also a feature that it is easy.

By using the semiconductor device and the manufacturing method thereof according to the present invention, a MOSFE having a gate length of 0.1 μm level is obtained.
Even in T, a high-performance MOSFET can be manufactured by using the conventional manufacturing process, and this MOSF
By applying ET to a memory, a memory of 1 gigabit or more can be realized.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view of a complementary semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view of a conventional semiconductor device.

FIG. 4 is a sectional view of a conventional trench gate type semiconductor device.

FIG. 5 is a manufacturing process diagram according to an embodiment of the present invention.

FIG. 6 is a manufacturing process diagram according to an embodiment of the present invention.

FIG. 7 is a manufacturing process diagram according to an embodiment of the present invention.

FIG. 8 is a manufacturing process drawing with another cross section according to the embodiment of the present invention.

FIG. 9 is a manufacturing process drawing with another cross section according to the embodiment of the present invention.

FIG. 10 is a manufacturing process diagram of a complementary MOSFET according to the present invention.

FIG. 11 is a manufacturing process diagram of a complementary MOSFET according to the present invention.

FIG. 12 is a manufacturing process diagram of a complementary MOSFET according to the present invention.

FIG. 13 is a manufacturing process diagram of a complementary MOSFET according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... High concentration impurity region, 3 ... Element isolation oxide film, 7 ... High concentration impurity region, 8 ... Gate oxide film, 9
... gate electrode, 11 ... tungsten film, 12 ... diffusion layer,
13 ... Sidewall insulating film, 14 ... Diffusion layer, 15 ... Interlayer insulating film,
16 ... Plug, 17 ... Wiring.

Claims (5)

[Claims] 1. A pair of impurity regions having a conductivity type different from that of a substrate are formed in a region of a semiconductor substrate surrounded by an element isolation insulating film, and a gate insulating film is formed with the semiconductor substrate. In the field-effect semiconductor device in which the electric potential flowing between the impurity regions is controlled by changing the potential of the gate electrode in contact with the gate insulating film, the gate insulating film is formed along the concave portion of the surface of the substrate. The width of the gate electrode is substantially equal to the width of the entrance of the recess, and the gate electrode is made of a laminated film of a polycrystalline silicon film and a metal film. 2. The metal film forming the gate electrode according to claim 1, which is a tungsten film selectively grown on a surface of a polycrystalline silicon film which is another film forming the gate electrode. Semiconductor device. 3. The semiconductor device according to claim 2, wherein the tungsten film is thicker than the polycrystalline silicon film. 4. A semiconductor device according to claim 1, wherein a plurality of semiconductor regions having different conductivity types are present in the same semiconductor substrate region and are formed in the semiconductor region. 5. A first step of forming a laminated film including an oxide film, a nitride film and an oxide film on a surface of a semiconductor substrate, and a second step of removing only the laminated film in a desired region to expose the surface of the substrate. A third step of forming a recess on the exposed surface of the substrate,
The fourth step of forming a gate insulating film on the exposed substrate surface, the laminated film formed in the first step, the fifth step of filling the inside of the groove formed by the concave portion of the substrate with polycrystalline silicon, and the polycrystalline A sixth step of selectively growing tungsten on a silicon surface, a seventh step of removing only the laminated film formed in the second step, and a substrate using a gate electrode made of a polycrystalline silicon film and a tungsten film as a mask. To form regions having different conductivity types, an eighth step of ion-implanting impurities, a ninth step of forming an insulating film on the side wall of the gate electrode, the gate electrode and the side wall insulating film as a mask To form regions of different conductivity types, a tenth step of ion-implanting impurities at a higher concentration than the eighth step, and covering the semiconductor surface with an interlayer insulating film to reach the substrate surface or the gate electrode. Contact holes, further characterized in that it consists eleventh step of forming the wiring layer,
Manufacturing method of semiconductor device.