JPS6055665A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit the effects of short channel and punch-through by a method wherein a gate electrode material layer is selectively removed by the use of a masking member formed on the layer, a gate electrode and an insulation film being formed and the masking member being then removed; thereafter ion implantation is carried out. CONSTITUTION:A field oxide film 22 and oxide film 23, and a phosphorus-doped polycrystalline Si layer 24 are formed on a P type Si substrate 21 the semiconductor substrate, a resist pattern being formed thereon, and the Si layer 24 being then selectively removed by the CDE method, resulting in the formation of a gate electrode 26. The N type source and drain regions 28 and 29 and an MOS transistor are formed by As ion implantation to the substrate with the gate electrode 26, a gate insulation film 27, and the oxide film 22 as a mask, and then by heat treatment. Since the gate insulation film 27 remains also in the periphery of the gate electrode 26, the improvement of withstand voltages of the electrode 26 and the regions 28 and 29, the omission of the treatment of oxidation in a succeeding process, and the shallowing of the junction can be contrived.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to an improvement in a method for manufacturing a semiconductor device.

[Technical background of the invention and its problems]

As is well known, in semiconductor devices such as MO8 type transistors, there is a remarkable trend toward miniaturization, speeding up, and higher density of elements, and this is due to PEP in the process.
This is largely due to advances in technology, ion implantation techniques that can form shallow junctions, and low-temperature processes.

In particular, the gate width of MO8 type transistors has been increasing to 3 μm in recent years.
It has been miniaturized from 2 μm to 2 μm, contributing to higher speed and higher density devices. However, the gate width is 2μm
Below this level, disadvantageous problems such as the so-called short channel effect and bunch-through become apparent.

BACKGROUND OF THE INVENTION Conventionally, MO8 type transistors, such as the one shown in FIG. 1, have been known. 1 in the figure is a P-type semiconductor substrate. On the surface of this substrate 1, N-type source and drain regions 2 and 3 are formed. A field oxide film 4 is formed on the substrate 1.
A gate electrode 7 is formed on the element region 5 of the substrate 1 surrounded by a gate insulating film 6 . According to the MO8 type transistor shown in FIG. 1, the formation of the source and drain regions 2 and 3 is generally carried out using a process of cell phasing, so the gap between the gate electrode 7 and the source and drain regions 2 and 3 is masked. There is no need for alignment, which is advantageous for miniaturization of elements. However, the source
The drain regions 2 and 3 will eventually have a diffusion depth of 0.5 to 1.5 μm, and considering the lateral diffusion isotropically, the source and drain regions 2 and 3 will have a diffusion depth of 0.5 to 1.5 μm.
is formed by invading the As a result, the effective channel becomes shorter than the design channel, resulting in a threshold value lower than a predetermined value, a so-called short channel effect.

Mayu, when the effective channel becomes shorter like this, the source,
The depletion layers of the drain regions 2 and 3 are connected 9 and punch-through occurs, degrading the withstand voltage of the device.

However, the most effective means for suppressing the short channel effect and punch-through phenomenon described above is to reduce the diffusion depth of the source and drain regions to prevent shortening of the effective channel length. However, if the overall depth of the diffusion layer is made shallow, the resistance of the diffusion layer increases, causing problems in circuit operation. For this reason, recently, the following L
D D (Lightly Doped Drain
) structure has been proposed. Next, the manufacturing method of this transistor is shown in Figs. 2(a) to (e).
Explain with reference to.

First, a field oxide film 4 is formed on a P-type semiconductor substrate 1 using a well-known technique.
A gate electrode 7' is formed on the element region 5 of the substrate 1 surrounded by a gate insulating film 6. Next, using this gate electrode 7 etc. as a mask, for example, arsenic is dosed. jk
10 Ion implantation is performed unevenly to form a shallow N-type impurity layer 11. ．．
11° (as shown in FIG. 2(a)). Next, a CVD 5in2 film 12'l is formed on the entire surface (tJf,
2 (as shown in Figure (b)).

Note that a Si s N4 film may be used instead of the CVD 5iQi film. Furthermore, the CVD5iO* film 12 is etched by reactive ion etching (RIE) to leave the CVPSIO film 12/ only on the side walls of the gate electrode 7, gate insulating film 6, and field oxide film 4 (second
Figure<c)Illustrated). After this, the example is arsenic t dose 1lt2
A deep N-type impurity layer 13.~3x10Ism1 is implanted again. .

132 is formed. As a result, the impurity layer 11. .

131 forms an N-type source region 14, and the impurity layer 11*113M forms an N-type drain region 15.
is formed (as shown in FIG. 2(d)).

Thereafter, the remaining CVNSTO film 12' is removed and a transistor is manufactured (FIG. 2(e)).
figure). Nao, the remaining CVD 8102g 72' does not necessarily have to be removed. Further, in the above manufacturing method, the shallow N-type impurity layer 11. ．． 112 was formed first, but
Conversely, deep N-type impurities +@131, 13. is formed, and then the remaining CVD 5iO film 12' is removed to form a deep N-type impurity layer 73. , JJ, may be formed. However, according to the MO8 type transistor of FIG. 2(e) manufactured as described above, although the short channel effect and punch-through can be improved, two ion implantations are required to form impurity layers with different depths. MO8 in Figure 1 is required.
Compared to conventional transistors, the process is more complicated, leading to higher costs.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and suppresses the short channel effect and punch-through phenomenon, and
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can simplify the process and reduce costs.

[Summary of the invention]

The present invention involves depositing a gate electrode material layer on an element region of a first conductivity type semiconductor substrate via an insulating film, forming a mask material on the gate electrode material layer, and then using this mask material. The gate electrode material layer is selectively removed to form a gate electrode, and the insulating film is selectively removed by reactive ion etching using the same mask material to form a gate insulating film. By performing ion implantation after removing the material, a MOB type transistor with, for example, an LDD structure is formed, and the main idea is to suppress short channel effects and punch-through phenomena, and to reduce costs.

[Embodiments of the invention]

Hereinafter, a case where the present invention is applied to an MO8 type transistor having an LDD structure will be described with reference to FIGS. 3(a) to 3(d).

[1] First, a field oxide film 22 was formed on a PM Si substrate 2 serving as a semiconductor substrate, and then an oxide film 23 was formed on the substrate 21 surrounded by the field oxide film 22. Subsequently, a phosphorus-doped polycrystalline silicon layer 24 was formed as a cathode electrode material layer on the entire surface (Fig. 3(a)).
As shown in the figure, a resist pattern 25 was then formed on this polycrystalline silicon layer 24. Furthermore, using this resist pattern 26 as a mask, the phosphorus-doped polycrystalline silicon layer 24 was selectively etched away by chemical dry etching (CDI) to form a μ gate electrode 26 (as shown in FIG. 3(b)).

In addition, in FIG. 2B, the side etching amount do of the phosphorus-doped polycrystalline silicon layer 24 was set to be approximately the same as the film thickness of the phosphorus-doped polycrystalline silicon layer 24. Here, the side etching amount di can be increased by reducing the etching amount by the CDE method, or conversely can be decreased by etching halfway by the RIE method and etching the remaining portion by the CDE method, so it can be adjusted as appropriate. .

Next, using the resist pattern 25 as a mask, the oxide film 23 is selectively etched away by RIE,
A gate insulating film 26 was formed. Subsequently, the resist pattern 25 is removed 7j (as shown in FIG. 3(c)). Then,
Using the gate electrode 26, gate insulating film 27, and field oxide film 22 as masks, ions of, for example, arsenic were implanted into the substrate 21, and heat treatment was performed. As a result, the N region near the gate electrode 26 is low-concentration and shallow, and the part farther away is high-concentration and deep N.
The source and drain regions 28 and 119 of the type were formed in a self-aligned manner, and an MO8m) transistor was formed (as shown in FIG. 3(d)).

According to the present invention, as shown in FIG. 3(b),
Using the resist pattern 25 as a mask, the phosphorus-doped polycrystalline silicon layer 24 is selectively etched away using the CDE method.
After forming the gate electrode 26, as shown in FIG. 3(e), the oxide film 23 is selectively etched away by RIE using the same resist pattern 25 as a mask to form the gate insulating film 2.
7, the width of the gate electrode 26 is narrower than that of the gate insulating film 27. Therefore, by ion-implanting arsenic into the St substrate 21 using the gate electrode 26, gate insulator M27, and field oxide film 22 as masks, the vicinity of the gate electrode 26 becomes shallow with a low concentration, and the part farther away becomes a deep N-type with a high concentration. If the source and drain regions 28 and 29 can be formed in a self-aligned manner, and the cost can be reduced by simplifying the process compared to the conventional method, short channel effects and punch-through phenomena can be suppressed.

tfc, as shown in FIG. 3(d), in order to leave the gate insulating film 27 not only directly under the gate electrode 26 but also around it, the gate electrode 26 and the source and drain regions 28 are
．． The breakdown voltage with respect to No. 29 can be improved compared to the normal MOS process, and the oxidation treatment in the post-process can be omitted.

Therefore, the source and drain regions 2B,i of the transistor
! 9 junctions are made shallower, making it suitable for miniaturization.

Note that in the above embodiments, a resist pattern is used as the mask material, but the present invention is not limited to this.

〔Effect of the invention〕

As described in detail above, according to the present invention, the MO8 of the LDD structure can suppress the short channel effect and punch-through phenomenon, and also simplify the process and reduce costs.
The present invention can provide a method for manufacturing semiconductor devices such as type transistors.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a conventional MO8 type transistor, FIG. )
1A and 1B are cross-sectional views illustrating a method for manufacturing an MO8 type transistor according to an embodiment of the present invention in order of steps. 21... P-type 81 substrate (semiconductor substrate), 22...
Field oxide film, 23... Oxide film, 24... Phosphorus-doped polycrystalline silicon layer (gate [Kiyoku Materials Co., Ltd., 25
...Resist pattern, 26...Gate electrode, 27
. . . N-type source region, 28 . . . N-type drain region. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] A step of depositing a gate electrode material layer on the element region of a first conductivity type semiconductor substrate via an insulating film, a step of forming a mask material on this gate electrode material layer, and a step of forming a gate electrode material layer using this mask material. a step of selectively removing a material layer to form a gate electrode; a step of selectively removing the insulating film by reactive ion etching using the same mask material to form a gate insulating film; and removing the mask material. A method for manufacturing a semiconductor device, comprising a step of performing post-ion implantation.