JPH0964361A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the manufacturing process of a MOS transistor with a pocket structure by simultaneously performing a process for implanting ions for controlling a threshold voltage and a process for implanting ions for forming a punch through stopper region. SOLUTION: After forming a gate electrode 4 on a P-type silicon substrate 1, a P-type impurity is subjected to ion implantation with an energy which passes through the gate electrode 4 and a P-type impurity layer 2 for controlling a threshold voltage and a punch through stopper region 6 are simultaneously formed directly below the gate electrode 4 and at the other parts, respectively. Then, an LDD layer 5 and a source/drain region 8 are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, for example, an MO having a so-called pocket structure.
It is particularly suitable when applied to a method of manufacturing an S-type semiconductor device.

[0002]

2. Description of the Related Art In recent years, MOS semiconductor devices have been miniaturized, and accordingly, there has been a problem of increase in leak current due to punch-through between source and drain.

Then, for example, Japanese Patent Laid-Open No. 6-151452.
As described in Japanese Patent Publication No. JP-A-2003-264, a diffusion layer of the same conductivity type as the substrate is formed in a higher concentration than the substrate as a punch-through stopper region around a low-concentration diffusion layer (LDD layer) having an LDD structure. By having a pocket structure,
It has been proposed to reduce the leakage current.

FIG. 2 shows a conventional MO having a pocket structure.
A method of manufacturing an S-type semiconductor device will be described.

First, as shown in FIG. 2A, after forming a gate oxide film 3 on a P-type silicon substrate 1, impurities (boron) 2 for controlling a gate threshold voltage are added to P-type silicon. It is introduced into the entire channel region of the substrate 1.

Next, as shown in FIG. 2B, about 3000 Å of polycrystalline silicon doped with N-type impurities is deposited and patterned to form a gate electrode 4.

Next, as shown in FIG. 2C, boron is ion-implanted into the P-type silicon substrate 1 using the gate electrode 4 as a mask to form a punch-through stopper region 6. At this time, the boron concentration is higher than the substrate concentration, and the boron accelerating voltage is such that the formation depth of the punch-through stopper region 6 is deeper than the LDD layer 5 to be formed later, and It is selected to be shallower than the source / drain region 8 to be formed.

Next, as shown in FIG. 2D, phosphorus is ion-implanted into the P-type silicon substrate 1 using the gate electrode 4 as a mask, and the LDD layer 5 is formed.

Next, as shown in FIG. 2E, a silicon oxide film is deposited on the entire surface and is etched back to form a gate side wall 7 on the side surface of the gate electrode 4.

Next, as shown in FIG. 2F, arsenic is introduced into the P-type silicon substrate 1 by ion implantation using the gate electrode 4 and the gate sidewall 7 as a mask to form the source / drain regions 8. To do. Then, the impurity layer is activated by annealing.

Through the above steps, an N-channel MOS transistor having a pocket structure is formed.

[0012]

In the conventional method of manufacturing a MOS type semiconductor device having a pocket structure, the boron for controlling the threshold voltage and the boron for preventing punch-through are separately formed. However, the number of manufacturing steps is increased and the manufacturing cost is increased as compared with the MOS type semiconductor device having no pocket structure.

Therefore, an object of the present invention is to simplify, for example, a method of manufacturing a MOS type semiconductor device having a pocket structure.

[0014]

A method of manufacturing a semiconductor device according to the present invention which solves the above-mentioned problems includes a step of forming a gate insulating film on a semiconductor substrate of a first conductivity type, and a gate on the gate insulating film. A step of forming an electrode, a step of ion-implanting an impurity of the first conductivity type into the entire surface of the semiconductor substrate including a portion immediately below the gate electrode, and a region where the gate electrode is not formed using the gate electrode as a mask Of implanting a second conductivity type impurity into the semiconductor substrate, forming a sidewall insulating film on a sidewall of the gate electrode, and using the gate electrode and the sidewall insulating film as a mask, the gate electrode And a step of ion-implanting a second conductivity type impurity into the semiconductor substrate in a region where the sidewall insulating film is not formed.

[0015]

In the present invention, for example, an M having a pocket structure
In the method of manufacturing an OS type semiconductor device, the impurity introduction for controlling the threshold voltage and the impurity introduction for forming the punch-through stopper region are performed in the same step, thereby reducing the number of manufacturing steps and reducing the manufacturing cost. Lower.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a method of manufacturing an N-channel MOS type semiconductor device having a pocket structure will be described below with reference to FIG.

First, as shown in FIG. 1 (a), 10Ω /
By thermally oxidizing the P-type silicon substrate 1 having a specific resistance of about cm ^2, a gate oxide film 3 having a film thickness of about 70 to 150 Å is formed on the surface of the element active region of the silicon substrate 1. Next, a polycrystalline silicon film having a thickness of about 3000 Å is deposited on the entire surface by the CVD method on the gate oxide film 3, and the polycrystalline silicon film is patterned by lithography into a linear shape having a width of 0.8 μm or less, A gate electrode 4 is formed on the gate oxide film 3.

Next, as shown in FIG. 1B, 3.0 ×
A region of the silicon substrate 1 that does not overlap with the gate electrode 4 by implanting boron (B) ions with a dose of about 10 ^{12 to} 5.0 × 10 ¹² / cm ² into the silicon substrate 1 with energy of about 100 to 150 KeV. At the same time as forming the punch-through stopper region 6 on the gate electrode 4
A P-type impurity diffusion layer 2 for controlling the threshold voltage is formed in the channel region immediately below.

Next, as shown in FIG. 1C, 1.0 × 10 ^{12 to} 3.0 × 10 ^{12 is used} with the gate electrode 4 as a mask.
50 to 8 of phosphorus (P) ions with a dose of about 1 / cm ²
Ions are implanted into the silicon substrate 1 with energy of about 0 KeV to form the LDD layer 5 which is an impurity diffusion layer having a shallow junction in the silicon substrate 1 on both sides of the gate electrode 4.

Next, as shown in FIG. 1D, SiO ₂
By depositing the film 7 on the entire surface of the silicon substrate 1 by the CVD method and etching back the SiO ₂ film 7,
A gate sidewall 7 which is a sidewall insulating film is formed on the side surface of the gate electrode 4.

Next, as shown in FIG. 1E, a dose of about 3.0 × 10 ^{15 to} 6.0 × 10 ¹⁵ / cm ^{2 is} applied by ion implantation using the gate electrode 4 and the gate sidewall 7 as a mask. A large amount of arsenic (As) ions is introduced into the silicon substrate 1 with an energy of about 60 to 90 KeV to form the source / drain regions 8 on the silicon substrate 1 in the region where the gate electrode 4 and the gate sidewall 7 are not formed. After that, the impurity diffusion layer and the low concentration impurity diffusion layer are activated by annealing. This annealing is performed, for example, at 950 ° C. for 10 minutes in an inert atmosphere of N ₂ or Ar. The annealing is performed after the boron implantation shown in FIG.
The steps may be separately performed after the phosphorus injection shown in FIG. 1C and the arsenic injection shown in FIG.

Through the above steps, an N-channel MOS transistor having a pocket structure is formed.

[0023]

According to the present invention, for example, in a method of manufacturing a MOS type semiconductor device having a pocket structure, an ion implantation step for controlling a threshold voltage and an ion implantation step for forming a punch through stopper region are performed. Therefore, the number of manufacturing steps can be reduced as compared with the conventional manufacturing method, and the manufacturing cost can be reduced.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a MOS transistor having a pocket structure according to an embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a method of manufacturing a conventional MOS transistor having a pocket structure in the order of steps.

[Explanation of symbols]

 1 P-type silicon substrate 2 P-type impurity diffusion layer 3 Gate oxide film 4 Gate electrode 5 LDD layer 6 Punch through stopper region 7 Gate sidewall 8 Source / drain region

Claims (1)

[Claims] 1. A step of forming a gate insulating film on a semiconductor substrate of the first conductivity type, a step of forming a gate electrode on the gate insulating film, and an entire surface of the semiconductor substrate including a portion immediately below the gate electrode. Ion implanting a first conductivity type impurity into the semiconductor substrate, ion implanting a second conductivity type impurity into the semiconductor substrate in a region where the gate electrode is not formed, using the gate electrode as a mask; Forming a sidewall insulating film on a sidewall of the electrode, and using the gate electrode and the sidewall insulating film as a mask, a second conductive film is formed on the semiconductor substrate in a region where the gate electrode and the sidewall insulating film are not formed. And a step of ion-implanting an impurity of a positive type.