JPH1056171A - Mis semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and its fabricating method which can be made high in reliability and driving force, suitable to micromachining. SOLUTION: A gate oxide film 4 and a gate electrode 5 are formed on a semiconductor substrate 1 and then a sidewall 6 is formed thereon. The substrate is subjected to an impurity implanting process at a low concentration with use of impurities such as arsenic (As+) ions and then phosphorus ions (P+) for activation to thereby form a source/drain region 8a and a low-resistance gate electrode 5a. Thereafter formed on the gate electrode 5a and source/drain region 8a is a silicide layer 31. Since arsenic is previously introduced prior to the implantation of phosphorus ions, increase in parasitic capacitance and leak can be avoided, and thus depletion of the gate electrode can be suppressed. Further, since a high concentration of arsenic ions is not used in a silicide step, increase in breakage of silicide fine lines or in resistive value can be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an MIS semiconductor device having a transistor in which impurities are introduced into a gate electrode and source / drain regions and having a silicide layer on the gate electrode and the source / drain regions. .

[0002]

2. Description of the Related Art In recent years, there has been a demand for higher integration, higher speed, and lower power consumption of semiconductor integrated circuits due to higher performance of electronic devices such as computers. Most of these semiconductor integrated circuits are composed of semiconductor elements called MOS transistors, so that miniaturization of MOS transistors is of utmost importance in order to realize the above demands. It is necessary to increase the speed of operation and decrease the operating voltage while miniaturizing the device.

Hereinafter, a conventional MOS transistor will be described with reference to the drawings.
An example of the type semiconductor device will be described.

FIGS. 7A to 7F show a conventional complementary MO.
FIG. 3 is a cross-sectional view illustrating a manufacturing process of an S (CMOS type) semiconductor device (FET).

First, as shown in FIG. 7 (a), a p-type semiconductor region 2a serving as an n-channel MOS transistor formation region and an n-type semiconductor serving as a p-channel MOS transistor formation region are formed on a p-type semiconductor substrate 1. A region 2b (n-well) and an element isolation region 3 for isolating between the p-type semiconductor region 2a and the n-type semiconductor region 2b are formed. And p
On the n-type semiconductor region 2b and on the n-type semiconductor region 2b.
Gate oxide film 4 and gate electrode 1 of MOS type transistor
5 are formed.

Next, as shown in FIG. 7 (b), after forming sidewalls 6 made of a silicon oxide film on both sides of each gate electrode 15, as shown in FIG. 7 (c), a p-type semiconductor is formed. An individual photoresist mask is formed in the region 2a and the n-type semiconductor region 2b (not shown), and impurity ions are implanted into each MOS transistor individually. That is,
Using a photoresist film (not shown) covering the n-type semiconductor region 2b as a mask, arsenic ions (As +) are applied to the gate electrode 15 and the regions 18 located on both sides of the gate electrode 15 in the p-type semiconductor region 2a. inject. The implantation conditions are, for example, an acceleration energy of 30 to 60 KeV and an implantation amount of 6 to 8
It is about × 10 ¹⁵ cm ^-2 . Further, the p-type semiconductor region 2a
Using a photoresist film (not shown) covering the mask as a mask,
Gate electrode 15 and gate electrode 1 in n-type semiconductor region 2b
Boron fluoride ions (BF2 +) are implanted into the region 19 located on both sides of the region 5. The implantation conditions are, for example, an acceleration energy of 10 to 40 KeV and an implantation amount of 3 to 8 × 10 ¹⁵ cm.
^-2 .

Next, in the step shown in FIG.
A heat treatment is performed at 10 ° C. for 10 seconds to activate the implanted impurity ions, so that an n-type source
A drain region 18a is formed, a p-type source / drain region 19a is formed in the n-type semiconductor region 2b, and a gate electrode 15 in each of the semiconductor regions 2a and 2b is made to have a low resistance, so that a low-resistance n-type gate electrode is formed. 15a and a p-type gate electrode 15b are formed.

Next, in a step shown in FIG. 7E, a metal film 30 of titanium or the like is deposited on the entire surface of the substrate to a thickness of 10 to 80 nm and heat-treated at 500 to 700 ° C.
5a, 15b and source / drain regions 18a, 19a
Silicon and titanium which constitute the vicinity of the surface are reacted with each other.

Next, in a step shown in FIG. 7 (f), the unreacted metal film is removed, and a heat treatment is performed at a temperature of 700 ° C. or more.
Gate electrodes 15a, 15b and source / drain region 1
A silicide layer 31 is formed on 8a and 19a.

That is, in the p-type semiconductor region 2a, a gate oxide film 4, an n-type gate electrode 15a having a silicide layer 31 on the surface, and an n-type source / drain region having a silicide layer 31 on the surface. 18a to form an n-channel MOS transistor 20a. The n-type semiconductor region 2b has a gate oxide film 4 and a p-type gate electrode 15b having a silicide layer 31 on the surface.
And a p-channel source / drain region 19a having a silicide layer 31 on the surface.
S transistor 20b is formed.

[0011]

However, the above-mentioned conventional MOS type semiconductor device, particularly the n-channel type MOS transistor 20a, has the following problems.

Generally, there are arsenic ions and phosphorus ions as n-type impurities to be implanted into the drain region 18a.
When phosphorus ions are implanted, the source / drain diffusion layers become deeper and the short channel effect increases, so arsenic ions are implanted as described above. However, when the silicide layer 31 is formed in the surface region of the gate electrode 15a and the source / drain region 18a of the n-channel MOS transistor, the dose of arsenic ions during the implantation of arsenic ions (As +) in the previous step When the amount is large, disconnection of the fine silicide wire, increase in resistance value, and the like occur. In particular, 0.25
In the case of a transistor having a μm rule or less, it is necessary to reduce the amount of arsenic implantation. On the other hand, if the dose of arsenic ions is reduced, the depletion of the n-type gate electrode and the increase in the sheet resistance of the n-type source / drain region 18a may occur, and the saturation current value may decrease.

The present invention has been made in view of the above points, and has as its object the purpose of
By using phosphorus as an impurity for forming the drain region and taking measures to suppress the spread of phosphorus in the semiconductor, the short-channel effect, the depletion of the gate electrode, etc. are prevented to drive the device. An object of the present invention is to obtain a MIS semiconductor device having high power and suitable for miniaturization, and at the same time, to effectively prevent disconnection of thin silicide wires and increase in resistance value.

[0014]

Means taken by the present invention to achieve the above object is to suppress the movement of phosphorus in a semiconductor before introducing phosphorus into a gate electrode and a source / drain region. Is to introduce an impurity having the following.

[0015] More specifically, M
Means relating to a method of manufacturing an IS semiconductor device;
13 means for the MIS semiconductor device.

According to a first aspect of the present invention, there is provided a method of manufacturing a MIS semiconductor device, comprising: a first step of forming a gate insulating film on an n-channel MIS transistor forming region of a semiconductor substrate; and forming a gate electrode on the gate insulating film. A second step of forming; a third step of forming sidewalls on both side surfaces of the gate electrode; and a step of forming the gate electrode and the gate electrode in the semiconductor substrate in the n-channel MIS transistor formation region. An impurity having a function of suppressing the movement of phosphorus in the semiconductor is introduced into the regions located on both sides, and then phosphorus is further introduced to form n-type source / drain regions and lower the resistance of the gate electrode. Forming a silicide layer in a region near the surface of at least one of the gate electrode and the source / drain region. And a fifth step of.

According to this method, the following effects can be obtained as compared with the conventional method. First, since the source / drain regions of the n-channel MOS transistor are formed by introducing phosphorus ions having a smaller ion radius than arsenic ions, the profile becomes gentle and the leakage current and the parasitic capacitance are reduced. Further, since the electric field in the drain region is alleviated, deterioration of transistor characteristics due to impact ionization of carriers is suppressed. Furthermore, without increasing the heat treatment conditions for the activity of impurity ions,
Since the depletion of the gate electrode is suppressed, the driving force of the transistor is also increased. On the other hand, the presence of the impurity having the function of suppressing the movement of phosphorus in the semiconductor allows the n-type source / drain diffusion layer to be formed shallowly, and the short channel effect can be suppressed while the source / drain region is formed by phosphorus ions. In addition, since high-concentration arsenic is not introduced into the gate electrode and the source / drain regions, disconnection of the fine silicide wire and increase in resistance value can be prevented. Therefore, it is possible to form a semiconductor device having high reliability and driving force, and including a transistor suitable for miniaturization.

According to a second aspect of the present invention, in the method for manufacturing a MIS semiconductor device according to the first aspect, in the first, second, and third steps, the gate is formed on the p-channel MIS transistor formation region of the semiconductor substrate. Forming an insulating film, a gate electrode, and a side wall; in the fourth step, in the p-channel type MIS transistor forming region, a region located on both sides of the gate electrode in the semiconductor substrate; To form a p-type source / drain region and reduce the resistance of the gate electrode in the pMIS transistor formation region. In the fifth step, the p-channel MIS transistor formation region A silicon layer in a region near the surface of at least one of the gate electrode and the source / drain region. It is a method of forming a de layer.

According to this method, the following operation and effect can be obtained in addition to the operation and effect of the first aspect. That is, since phosphorus ions are implanted into the n-type gate electrode in the MIS-type semiconductor device, short-term or low-temperature conditions such that p-type impurity ions do not penetrate from the gate electrode of the p-channel type MOS transistor to the channel side. Depletion of the gate electrode of the n-channel MOS transistor can be suppressed even by the lower heat treatment. Therefore, particularly high driving force M
A semiconductor device including an OS transistor can be formed.

In the first or second aspect, the following preferred modes can be adopted.

According to a third aspect of the invention, there is provided a method of manufacturing a MIS semiconductor device according to the first or second aspect, wherein the introduction of phosphorus in the fourth step is performed by using the gate electrode and the sidewall as a mask in the semiconductor substrate. This method is performed by activating phosphorus ions by heat treatment after ion implantation.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
4. The method according to claim 3, wherein the impurity having a function of suppressing the movement of phosphorus in the semiconductor is an impurity for preventing channeling at the time of implanting phosphorus ions by making the gate electrode and the semiconductor substrate amorphous.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
5. The method according to claim 4, wherein the introduction of the impurity for preventing channeling at the time of implanting the phosphorus ions in the fourth step is performed by accelerating the impurity ions with an acceleration energy of 40 to 80.
The implantation is performed by implanting at KeV with an implantation amount of 2 to 8 × 10 ¹⁴ cm ⁻² , and the phosphorus ion implantation conditions are set at an acceleration energy of 5 to 30 KeV and an implantation amount of 2 to 8 × 10 ¹⁵ cm ⁻² . Is the way.

According to a sixth aspect of the invention, there is provided a method of manufacturing a semiconductor device.
3. The method according to claim 1, wherein the impurity having a function of suppressing the movement of phosphorus in the semiconductor is an impurity that suppresses the movement of phosphorus in the semiconductor by trapping interstitial semiconductor atoms of the semiconductor. .

According to a seventh aspect of the invention, there is provided a method of manufacturing a semiconductor device.
3. The method according to claim 1, wherein the impurity having a function of suppressing the movement of phosphorus in the semiconductor is arsenic, silicon, or silicon.
In this method, at least one of germanium, nitrogen, and a halide is used.

The semiconductor device according to claim 8 is based on the premise that the MIS semiconductor device has at least an n-channel MIS transistor formed in a part of a semiconductor substrate.
The channel type MIS transistor includes a gate insulating film formed on the semiconductor substrate, and a gate formed on the gate insulating film and doped with an impurity having a function of suppressing movement of phosphorus in the semiconductor and phosphorus. An electrode, sidewalls formed on both side surfaces of the gate electrode, and impurities formed in regions of the semiconductor substrate located on both sides of the gate electrode and having a function of suppressing the movement of phosphorus in the semiconductor. And n-type source / drain regions into which phosphorus is introduced.

A semiconductor device according to a ninth aspect of the present invention is the semiconductor device according to the eighth aspect, further comprising a p-channel MIS transistor formed in a different portion of the semiconductor substrate from the n-channel transistor, Are a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film and doped with p-type impurities, and sidewalls formed on both side surfaces of the gate electrode. And p-type source / drain regions formed on both sides of the gate electrode of the semiconductor substrate and having p-type impurities introduced therein.

According to a tenth aspect of the present invention, there is provided a semiconductor device according to the eighth aspect.
In 9 or 9, the impurity having a function of suppressing the movement of phosphorus in the semiconductor is an impurity that prevents channeling at the time of implanting phosphorus ions by making the gate electrode and the semiconductor substrate amorphous.

The semiconductor device according to claim 11 is the semiconductor device according to claim 8
In 9 or 9, the impurity having a function of suppressing the movement of phosphorus in the semiconductor is an impurity that suppresses the movement of phosphorus in the semiconductor by trapping interstitial semiconductor atoms of the phosphorus semiconductor.

According to a twelfth aspect of the present invention, there is provided a semiconductor device according to the eighth aspect.
Or 9, wherein at least one of arsenic, silicon, germanium, nitrogen, and a halide is used as an impurity having a function of suppressing the transfer of phosphorus in the semiconductor during the ion implantation and thermal diffusion of phosphorus. It is.

According to the constitutions of claims 8 to 12, MIS semiconductor devices having the advantages corresponding to the above-mentioned claims 1 to 7, respectively, can be obtained.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIGS. 1A to 1F are cross-sectional views showing a manufacturing process of an n-channel MOS semiconductor device according to a first embodiment.

First, as shown in FIG. 1A, a gate made of a silicon oxide film having a thickness of 4 to 10 nm is formed on a p-type semiconductor substrate 1 (which functions as a p-type semiconductor region in this embodiment). An oxide film 4 and a gate electrode 5 made of a polysilicon film having a thickness of 100 to 300 nm are formed.

Next, as shown in FIG. 1B, a silicon oxide film 7 having a thickness of 100 to 200 nm is deposited on the gate electrode 5 and the p-type semiconductor substrate 1 by the CVD method.

Next, as shown in FIG. 1C, the silicon oxide film is etched back by performing anisotropic dry etching, and sidewalls 6 are formed on both side surfaces of the gate electrode 5.

Next, as shown in FIG. 1D, using the gate electrode 10 and the side wall 6 as a mask, the inside of the gate electrode 5 and the regions 8 located on both sides of the gate electrode 5 in the semiconductor substrate 1 are formed. Is implanted with arsenic ions (As @ +). The injection conditions at this time are, for example, an acceleration energy of 40
In ～80KeV, injection volume is 2~8 × 10 ¹⁴ cm ^-2. Subsequently, phosphorus ions (P +) are further implanted into the gate electrode 5 and the regions 8 located on both sides of the gate electrode 5 in the semiconductor substrate 1 using the gate electrode 10 and the sidewalls 6 as a mask. The implantation conditions at this time are, for example, an acceleration energy of 5 to 30 KeV and an implantation amount of 2 to 8 ×
It is 10 ¹⁵ cm ^-2 . At this time, an impurity-introduced layer to be the source / drain region 8a is formed, but in this state, it does not yet function as a source / drain which causes a carrier transfer action. Further, FIG.
At a temperature of 1000 to 1050 ° C. and a time of 1
~ 15 seconds, or at 850 ° C for 1 hour
A heat treatment under the conditions of 0 to 30 minutes is performed to activate the implanted impurity ions, that is, arsenic ions (As +) and phosphorus ions (P +). As a result, the resistance n
Formed gate electrode 5a and n-type source / drain regions 8a having a function of causing carrier movement are formed. At this time, the depth of the source / drain region 8a as a whole is, for example, 0.1 to 0.15 μm. However, since the concentration of arsenic ions (As +) is extremely low,
The role of the source / drain region 8a used for the movement of carriers is very small and almost negligible. In other words, regarding the function of the source / drain region 8a, the impurity concentration distribution may be considered only by considering the concentration of the phosphorus ions (P +).

Next, in the step shown in FIG. 1E, a metal film 30 of titanium or the like is deposited on the entire surface of the substrate to a thickness of 10 to 80 nm, and a heat treatment is performed at 500 to 700 ° C.
a and silicon constituting the vicinity of the surface of the source / drain region 8a are reacted with titanium or the like.

Next, in the step shown in FIG. 1 (f), the unreacted metal film is removed, and a heat treatment is performed at a temperature of 700 ° C. or more to form a silicide layer 31 on the gate electrode 5a and the source / drain regions 8a. Form. That is, an N-channel type MO
An S transistor 10a is formed.

Although the following steps are omitted, a semiconductor device is formed by forming several layers of metal wiring via an interlayer insulating film.

The M formed through such a series of steps is
The OS transistor has the following advantages as compared with the conventional MOS transistor.

The M formed through such a series of steps is
The OS transistor has the following advantages as compared with the conventional MOS transistor. Hereinafter, this point will be described with reference to data.

FIG. 2 shows the concentration of only phosphorus ions in the source / drain regions formed by implanting only phosphorus ions and the source / drain regions 8a formed by implanting arsenic ions and phosphorus ions of the present embodiment. It is SIMS data showing a distribution. As shown in the figure, the depth of the source / drain region (see the change curve A2) of the present embodiment is larger than the depth of the source / drain region (see the change curve A1) formed by implanting only phosphorus ions. Turns out to be quite shallow. The concentration of the phosphorus ions at a depth of 80 nm in the n-type source / drain region according to the present embodiment is 3 × 10 ^{17 to} 3 × 10 ¹⁸ / cm ⁻³ . Further, the depth 80 in the n-type source / drain region 8a is
The concentration of the arsenic ion at the position of nm is 3 × 10 ¹⁶
３3 × 10 ¹⁷ / cm ^-3 .

FIG. 3 shows a junction capacitance of the source / drain region formed by implantation of only general phosphorus ions (curve B1) and a junction capacitance of the source / drain region formed by implantation of only arsenic ions (curve). It is a characteristic view which compared with B2). As can be seen from FIG. 3, the junction capacitance of the source / drain region obtained by the implantation of phosphorus ions is small, and the impurity concentration distribution is gentle.

FIG. 4 shows the saturation current (curve C1) of a conventional MOS transistor having a source / drain region formed by implanting only arsenic ions, and the present embodiment formed by implanting arsenic ions and phosphorus ions. FIG. 11 is a characteristic diagram comparing a saturation current (curve C2) of a MOS transistor having a source / drain region. As can be seen from FIG. 4, the MOS transistor of the present embodiment has an improved saturation current value.

FIG. 5 shows the depletion rate (curve D1) of the conventional gate electrode formed by implanting only arsenic ions,
FIG. 9 is a characteristic diagram comparing a depletion rate (curve D2) of the gate electrode of the present embodiment formed by implantation of arsenic ions and phosphorus ions. However, a higher Cinv / Cox indicates a lower depletion rate. As can be seen from FIG. 5, the gate electrode of the MOS transistor of the present embodiment has a lower depletion rate.

The following can be understood from the above series of data.

First, in the source / drain region 8a, the source / drain region 8a
Arsenic ions are implanted into the regions that will become the source / drain regions before the phosphorus ions are implanted, as compared to the case where the source / drain regions are formed by introducing only arsenic. The impurity concentration profile of the drain region 8a becomes gentle (see FIG. 3). Therefore, deterioration of transistor characteristics due to impact ionization of carriers and increase in parasitic capacitance and leak current can be suppressed.

Second, in the step shown in FIG. 1D, when arsenic ions (As +) are implanted, the silicon single crystal in the semiconductor substrate 1 is partially amorphized. Then, mainly by the amorphized portion, phosphorus ions (P @ +) are formed in the next step shown in FIG.
Channeling at the time of injecting is suppressed. Therefore, as compared with the case where the source / drain regions are formed by implanting only phosphorus ions, the source / drain regions 8 are formed.
The depth of the diffusion layer a can be suppressed (see FIG. 2).
Therefore, the short channel effect can be suppressed.

Third, since it has an n-type gate electrode 5a formed by implantation of arsenic ions and phosphorus ions,
Phosphorus ions are sufficiently activated without performing a high-temperature, long-time heat treatment. Therefore, depletion of the gate electrode 5a due to inactivation of arsenic ions can be suppressed (see FIG. 5), and the driving power of the n-channel MOS transistor increases (see FIG. 4).

In addition, when forming a silicide layer in the surface region of the gate electrode 5a and the source / drain region 8a,
Since it does not contain a high concentration of arsenic, it does not cause disconnection of the fine silicide wire or increase in resistance value. Therefore, even in a fine semiconductor device having a design rule of 0.25 μm or less, a silicide layer can be formed without causing a problem such as a decrease in driving force due to gate depletion. In a semiconductor device equipped with a MOSFET having a so-called polycide structure or salicide structure, the resistance of the gate electrode and the source / drain electrodes can be extremely reduced.
Although the structure is suitable for lowering the voltage in accordance with miniaturization of a transistor, the present invention exerts a remarkable effect that reliability and driving force can be improved in a semiconductor device having such a fine structure. is there.

(Second Embodiment) Next, a second embodiment will be described. FIGS. 6A to 6F show the second embodiment of the present invention.
FIG. 14 is a cross-sectional view showing a manufacturing step of the CMOS semiconductor device according to the embodiment.

In the state shown in FIG. 6A, a p-type semiconductor region 2a, which is an n-channel MOS transistor formation region, is formed on the p-type semiconductor substrate 1 (in this embodiment, the same impurity as that of the p-type semiconductor substrate 1). Concentration region) and p-channel type M
N-type semiconductor region 2b which is an OS transistor formation region
And an element isolation region 3 for isolating the p-type semiconductor region 2a and the n-type semiconductor region 2b. From this state,
A gate oxide film 4 made of a silicon oxide film having a thickness of 4 to 10 nm and a gate electrode 5 made of a polysilicon film having a thickness of 100 to 300 nm are formed on the p-type semiconductor region 2a and the n-type semiconductor region 2b. .

Next, as shown in FIG. 6B, after a silicon oxide film having a thickness of 100 to 200 nm is deposited on the gate electrode 5 and the p-type semiconductor substrate 1 by the CVD method, anisotropic dry etching is performed. Then, the silicon oxide film is etched back to form sidewalls 6 on both side surfaces of the gate electrode 5.

Next, as shown in FIG. 6C, in the p-type semiconductor region 2a, a photoresist film (not shown) covering the n-type semiconductor region 2b, the gate electrode 5 and the sidewalls 6 are used as masks. In the same manner as in the step shown in FIG. 1D, arsenic ions are implanted, and then phosphorus ions are implanted, so as to be located on both sides of the gate electrode 5 and the gate electrode 5 in the p-type semiconductor region 2. Arsenic ions and phosphorus ions are introduced into the region 8 to be formed. The injection conditions at this time may be as described in the first embodiment.

In the n-type semiconductor region 2b, p
Boron fluoride ions (BF2 +) are implanted using the photoresist film (not shown) covering the type semiconductor region 2a, the gate electrode 5 and the sidewall 6 as a mask, and the gates in the gate electrode 5 and the n-type semiconductor region 2b are formed. Boron fluoride ions are introduced into the region 9 located on both sides of the electrode 5. At this time, the implantation conditions of boron fluoride ions are as follows: the acceleration energy is 10 to 60 KeV, and the implantation amount is 2 to 8 ×
It is 10 ¹⁵ cm ^-2 .

Further, in the state shown in FIG. 6 (d), heat treatment is performed under the condition of a temperature of 1000 to 1050 ° C. and a time of 1 to 15 seconds, or a condition of a temperature of 850 ° C. and a time of 10 to 30 minutes. Activate impurity ions. As a result, in the p-type semiconductor region 2a, an n-type gate electrode 5a with reduced resistance and an n-type source / drain region 8a are formed, and in the n-type semiconductor region 2b, p-type with reduced resistance is formed.
Gate electrode 5b and p-type source / drain region 9a
Are formed. In addition, any of the semiconductor regions 2a and 2b
Also, the depth of the source / drain regions 8a and 9a is 0.1 to 0.15 μm.

Next, in a step shown in FIG. 6E, a metal film 30 of titanium or the like is deposited on the entire surface of the substrate to a thickness of 10 to 80 nm, and a heat treatment is performed at 500 to 700 ° C.
a, 5b and silicon constituting the vicinity of the surface of the source / drain regions 8a, 9a are reacted with titanium or the like.

Next, in the step shown in FIG. 6 (f), the unreacted metal film is removed, and a heat treatment is performed at a temperature of 700 ° C. or more.
The gate electrodes 5a, 5b and the source / drain regions 8a,
A silicide layer 31 is formed on 9a.

That is, the p-type semiconductor region 2a has a gate oxide film 4, an n-type gate electrode 5a having a silicide layer 31 on the surface, and an n-type source / drain region having a silicide layer 31 on the surface. 8a to form an n-channel MOS transistor 10a.
The n-type semiconductor region 2b includes a gate oxide film 4, a p-type gate electrode 5b having a silicide layer 31 on the surface, and a p-type source / drain region 9a having a silicide layer 31 on the surface. A channel type MOS transistor 10b is formed.

Although the following steps are omitted, a semiconductor device is formed by forming several layers of metal wiring via an interlayer insulating film.

In the present embodiment, basically, the manufacturing process of the first embodiment is applied to a CMOS semiconductor device. The n-channel transistor 10a has the same structure as that of the first embodiment. It has characteristics and can exert the same effect.

In addition, the CM formed according to the present embodiment
The OS-type semiconductor device has the following advantages as compared with a conventional combination of an n-channel MOS transistor using arsenic ion implantation and a p-channel MOS transistor using boron fluoride ion implantation.

Since phosphorus ions are implanted into n-type gate electrode 5a of n-channel MOS transistor 10a, the p-type gate electrode of p-channel MOS transistor 10b is subjected to the heat treatment in the state shown in FIG. Even if heat treatment is performed for a short time or at a low temperature so as not to cause penetration of boron from 5b into the channel region, phosphorus ions in gate electrode 5a of n-channel MOS transistor 10a are sufficiently activated. Therefore, in the n-channel MOS transistor 10a, the depletion of the n-type gate electrode 5a can be suppressed, and a sufficiently high driving force can be obtained.

In the first and second embodiments, the function of amorphizing a single crystal (a silicon single crystal in this embodiment) constituting the semiconductor substrate in the semiconductor substrate 1 before implanting phosphorus ions is provided. Although arsenic ions were implanted as impurity ions, if a material having the same function (for example, silicon ions, germanium ions, etc.) is implanted, phosphorus ions may be implanted after implanting the ions of the substance.
The same effects as in the present embodiment can be exhibited. Furthermore, an impurity having a function of trapping interstitial silicon atoms, such as nitrogen or a halide, is introduced into the gate electrode and the source / drain region even if the impurity is not an impurity having a function of making the semiconductor crystal amorphous. Can also exhibit the same effect. This is because phosphorus diffuses by pairing with interstitial silicon atoms.

In the first and second embodiments, low-concentration n-type impurity ions (for example, phosphorus ions) are implanted in the steps shown in FIGS. 1 (a) and 2 (a). As a result, a so-called LDD region having a low-concentration source / drain region between the source / drain region 8a and the channel region can be formed.
An S transistor can be formed.

Further, in the first and second embodiments, the introduction of impurities into the gate electrode and the semiconductor substrate is entirely performed by ion implantation. However, the polysilicon film forming the gate electrode is formed by CVD. At this time, it is also possible to introduce impurities by vapor phase diffusion or diffusion from plasma after forming impurities in the polysilicon film or forming a gate electrode. Similarly, an impurity can be introduced into the semiconductor substrate by vapor phase diffusion or the like.

In the first and second embodiments, the gate insulating film is formed of a silicon oxide film. However, the gate insulating film is formed of a silicon nitride film or an oxynitride film instead of the silicon oxide film. It is needless to say that the same effects as those of the above embodiments can be exerted.

[0068]

According to the first to seventh aspects of the present invention, a method of manufacturing a MIS semiconductor device has a function of preventing channeling at the time of implanting phosphorus ions by using at least a gate electrode as a mask in an n-channel MOS transistor formation region. After implanting impurity ions, phosphorus ions are implanted, and the phosphorus ions are activated by heat treatment to form source / drain regions, and the gate electrodes are lowered in resistance, and then silicide is applied to the gate electrodes and the source / drain regions. Since the layer is formed, it is possible to suppress an increase in parasitic capacitance, an increase in leak current, depletion of the gate electrode, etc., while suppressing the short channel effect, and also to prevent a thin wire of the silicide layer from breaking or a resistance value. It is possible to prevent the semiconductor device from increasing, and thus to manufacture a semiconductor device having high reliability and driving force and suitable for miniaturization. It is possible to provide a method.

According to the eighth to twelfth aspects, the structure of the MIS semiconductor device has a gate electrode and source / drain regions formed by implanting arsenic ions and phosphorus ions, and a silicide layer formed thereon. Since the configuration includes the n-channel MOS transistor, it is possible to provide a semiconductor device having high reliability and driving force and suitable for miniaturization.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of an n-channel MOS transistor according to a first embodiment.

FIG. 2 is a concentration distribution diagram of phosphorus ions in a source / drain region and a source / drain region formed by introducing only phosphorus ions according to the first embodiment.

FIG. 3 is a characteristic diagram comparing a junction capacitance between a source / drain region formed by introducing phosphorus ions and a source / drain region formed by introducing arsenic ions.

FIG. 4 is a characteristic diagram comparing a saturation current value of the MOS transistor according to the first embodiment with a saturation current value of a conventional MOS transistor having a gate electrode by introducing arsenic ions.

FIG. 5 is a characteristic diagram comparing the depletion rate of the MOS transistor of the first embodiment with the depletion rate of a conventional MOS transistor having a gate electrode due to the introduction of arsenic ions.

FIG. 6 is a sectional view illustrating a manufacturing process of the CMOS transistor according to the second embodiment;

FIG. 7 is a cross-sectional view showing a manufacturing process of a conventional CMOS transistor.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2a p-type semiconductor region 2b n-type semiconductor region 3 element isolation region 4 gate oxide film 5 gate electrode 6 sidewall 7 silicon oxide film 8a n-type source / drain region 9a p-type source / drain region 10a n-channel MOSD Transistor 10b P-channel MOS transistor 30 Metal film 31 Silicide layer

Claims (12)

[Claims] A first step of forming a gate insulating film on an n-channel MIS transistor forming region of a semiconductor substrate; a second step of forming a gate electrode on the gate insulating film; A third step of forming sidewalls on both side surfaces of the semiconductor device; and, in the n-channel MIS transistor formation region, a region located on both sides of the gate electrode and the gate electrode in the semiconductor substrate. A fourth step of introducing n-type source / drain regions and lowering the resistance of the gate electrode by further introducing phosphorus after introducing an impurity having a function of suppressing the transfer of phosphorus in the gate electrode, A fifth step of forming a silicide layer in a region near the surface of at least one of the source / drain regions. Method of manufacturing MIS semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the first, second and third steps, a gate insulating film and a gate are also formed on a p-channel MIS transistor forming region of the semiconductor substrate. Forming an electrode and a side wall; in the fourth step, in the p-channel type MIS transistor forming region, a p-type impurity is formed in the gate electrode and regions located on both sides of the gate electrode in the semiconductor substrate. To form a p-type source / drain region and reduce the resistance of the gate electrode in the pMIS transistor formation region. In the fifth step, the gate electrode is also formed in the p-channel MIS transistor formation region. And forming a silicide layer in a region near the surface of at least one of the source and drain regions. A method for manufacturing a MIS semiconductor device, comprising: 3. The method for manufacturing a semiconductor device according to claim 1, wherein the phosphorus is introduced in the fourth step by implanting phosphorus ions into the semiconductor substrate using the gate electrode and the sidewall as a mask. Thereafter, the method is performed by activating phosphorous ions by heat treatment. 4. The method for manufacturing a MIS semiconductor device according to claim 3, wherein the impurity having a function of suppressing the movement of phosphorus in the semiconductor is implanted with phosphorus ions by making the gate electrode and the semiconductor substrate amorphous. MIS, which is an impurity for preventing channeling at the time
A method for manufacturing a semiconductor device. 5. The method of manufacturing a MIS semiconductor device according to claim 4, wherein the step of introducing the impurity for preventing channeling at the time of implanting the phosphorus ions in the fourth step comprises introducing the impurity ions with an acceleration energy of 40 to 80 KeV. And the injection volume is 2
Performed by injecting at ~8 × 10 ¹⁴ cm ^-2, the implantation conditions of the phosphorus ions, the acceleration energy is 5 to 30
A method for manufacturing a MIS semiconductor device, wherein the injection amount is 2 to 8 × 10 ¹⁵ cm ⁻² in KeV. 6. The method for manufacturing a MIS semiconductor device according to claim 1, wherein the impurity having a function of suppressing the movement of phosphorus in the semiconductor is formed by trapping interstitial semiconductor atoms of the semiconductor. A method for manufacturing a MIS semiconductor device, wherein the impurity is an impurity that suppresses movement in a semiconductor. 7. The method for manufacturing a MIS semiconductor device according to claim 1, wherein the impurity having a function of suppressing the transfer of phosphorus in the semiconductor is at least one of arsenic, silicon, germanium, nitrogen, and a halide. A method of manufacturing a MIS semiconductor device. 8. An MIS semiconductor device having at least an n-channel MIS transistor formed on a part of a semiconductor substrate, wherein the n-channel MIS transistor includes: a gate insulating film formed on the semiconductor substrate; A gate electrode formed on an insulating film and doped with phosphorus and an impurity having a function of suppressing the movement of phosphorus in the semiconductor; sidewalls formed on both side surfaces of the gate electrode; An n-type source doped with an impurity and phosphorus, which are formed in regions located on both sides of the gate electrode and have a function of suppressing the movement of phosphorus in the semiconductor.
A MIS semiconductor device comprising: a drain region. 9. The MIS semiconductor device according to claim 8, further comprising a p-channel MIS transistor formed in a portion of said semiconductor substrate other than said n-channel transistor, wherein said p-channel MIS transistor comprises: A gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film and doped with a p-type impurity, and sidewalls formed on both side surfaces of the gate electrode; An MIS semiconductor device comprising: a p-type source / drain region formed in a region on both sides of the gate electrode of the semiconductor substrate and having p-type impurities introduced therein. 10. The MIS semiconductor device according to claim 8, wherein the impurity having a function of suppressing the movement of phosphorus in the semiconductor is formed by making the gate electrode and the semiconductor substrate amorphous by implanting phosphorus ions. MIS, which is an impurity for preventing channeling in the MIS
Semiconductor device. 11. The MIS semiconductor device according to claim 8, wherein the impurity having a function of suppressing the movement of phosphorus in the semiconductor is formed by trapping interstitial semiconductor atoms of the phosphorus semiconductor. MIS semiconductor device, characterized in that the impurity is an impurity that suppresses migration in the semiconductor device. 12. The MIS semiconductor device according to claim 8, wherein the impurity having a function of suppressing the transfer of phosphorus in the semiconductor during the ion implantation and thermal diffusion of phosphorus is arsenic, silicon, germanium, or the like. An MIS semiconductor device comprising at least one of nitrogen and a halide.