US20060138567A1 - Semiconductor device and fabricating method thereof - Google Patents
Semiconductor device and fabricating method thereof Download PDFInfo
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- US20060138567A1 US20060138567A1 US11/230,697 US23069705A US2006138567A1 US 20060138567 A1 US20060138567 A1 US 20060138567A1 US 23069705 A US23069705 A US 23069705A US 2006138567 A1 US2006138567 A1 US 2006138567A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title abstract description 13
- 239000002019 doping agent Substances 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000009792 diffusion process Methods 0.000 claims abstract description 25
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 230000000694 effects Effects 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 125000006850 spacer group Chemical group 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Definitions
- the present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device and fabricating method thereof in which a lightly doped drain junction is graded using a diffusion property of dopant implanted in heavily doped source/drain region.
- the double diffused drain (DDD) structure has been used to improve the hot carrier effect and the like of a semiconductor device having a channel length greater than 0.35 ⁇ m.
- a semiconductor device having a channel length greater than 0.35 ⁇ m.
- Such a device is not concerned about breakdown voltage (BVDss) between source and drain as well as roll-off of threshold voltage.
- the DDD structure is being used less.
- the DDD structure is employed in part.
- the short channel device still has the above-noted difficulty in employing the DDD structure.
- a transistor as a low power device having small leakage current tends to employ the LDD (lightly doped drain) structure instead of the conventional DDD structure to enhance the short channel effect due to the reduced channel length.
- the junction configuration is modified, the breakdown voltage between source and drain is lowered. This may be explained as follows.
- the known process of implanting additional P-type dopant is mainly used in improving leakage characteristic and capacitance by grading a junction profile, not in the LDD region but in the source/drain region.
- FIG. 1A is a cross-sectional diagram of a known semiconductor device having a double diffused drain (DDD) and FIG. 1B is a cross-sectional diagram of a semiconductor device having a lightly doped drain (LDD).
- DDD double diffused drain
- LDD lightly doped drain
- FIG. 1A an STI layer 16 and an n-well or p-well 11 are formed on a semiconductor substrate.
- a gate oxide layer 12 is formed 30 ⁇ thick on the substrate, and a polysilicon layer 13 is deposited over the substrate.
- a gate 13 is then formed by patterning the polysilicon layer by photolithography.
- a PMOS or NMOS DDD region 14 is formed in the N- or P-well 11 by ion implantation.
- a sidewall spacer 18 is provided to the gate 13 by depositing a nitride layer over the substrate and by etching back the nitride layer. Subsequently, ion implantation is carried out on the substrate using dopant of As and P ions to form source and drain regions 15 and 19 , and silicidation is carried out on the substrate to form a Co-silicide 17 layer on the gate 13 and the source and drain regions 15 and 19 .
- a process of fabricating a semiconductor device having the LDD structure is similar to that of fabricating the semiconductor device having the DDD structure in FIG. 1A , except forming a PMOS or NMOS LDD region 24 instead of forming the PMOS or NMOS DDD region 14 in FIG. 1A by ion implantation.
- the short channel effect still takes place in case of applying the DDD or LDD structure to the known low power device.
- a high electric field is applied to the LDD region.
- FIG. 1A is a cross-sectional diagram of a known semiconductor device having a double diffused drain (DDD).
- DDD double diffused drain
- FIG. 1B is a cross-sectional diagram of a semiconductor device having a lightly doped drain (LDD).
- LDD lightly doped drain
- FIG. 2 is a cross-sectional diagram of an example semiconductor device having an LDD region enclosed by a diffusion source/drain region.
- FIGS. 3A to 3 F are cross-sectional diagrams depicting an example method of fabricating a semiconductor device having an LDD region enclosed by a diffusion source/drain region.
- FIG. 4 is a graph of a breakdown voltage between source and drain.
- FIG. 5 is a graph for showing short channel effect enhancement in the example semiconductor device described herein.
- the example apparatus and methods described herein provide a semiconductor device and fabricating method thereof, in which an LDD junction is graded using phosphorous dopant diffusion of a source/drain region and by which a roll-of characteristic of threshold voltage is enhanced as well as BVDss.
- an example semiconductor device includes a gate electrode having a gate insulating layer underneath a semiconductor substrate, a pair of lightly doped regions separated from each other in the semiconductor substrate to be aligned with the gate electrode, a pair of heavily doped regions separated from each other in the semiconductor substrate to be partially overlapped with a pair of the lightly doped regions, respectively, and a pair of diffusion source/drain regions enclosing a pair of the lightly doped regions therein, respectively.
- a pair of the diffusion source/drain regions are heavily doped with additional dopant, which is preferably phosphor (P). More preferably, junction profiles of the lightly doped regions are graded due to lateral diffusion of the additional dopant.
- An example method of fabricating a semiconductor device includes forming a gate electrode having a gate insulating layer underneath on a semiconductor substrate, forming a pair of lightly doped regions separated from each other in the semiconductor substrate to be aligned with the gate electrode, forming a spacer to a sidewall of the gate electrode, forming a pair of heavily doped regions separated from each other in the semiconductor substrate to be partially overlapped with a pair of the lightly doped regions, respectively, heavily doping the heavily doped regions with additional dopant, and diffusing the additional dopant in a lateral direction toward the lightly doped regions to form a pair of diffusion source/drain regions enclosing a pair of the lightly doped regions therein, respectively.
- the additional dopant is phosphor (P), and, preferably, the additional dopant is diffused to enclose a pair of the lightly doped regions to avoid a double diffused drain (DDD) structure.
- DDD double diffused drain
- junction profiles of the lightly doped regions are graded due to lateral diffusion of the additional dopant and, preferably, the method further includes the step of forming a silicide layer on the gate electrode and a pair of the heavily doped regions.
- the example semiconductor device described herein may be used to improve BVDss, which was degraded by high electric field impression on the source/drain region of the LDD semiconductor device and to improve the short channel effect.
- an LDD region is enclosed by P-type dopant using lateral diffusion of the P-type dopant added to a source/drain region, whereby the BVDss characteristic and short channel effect are improved to enhance a process margin.
- P-type dopant is implanted in a source/drain region of a device applicable to a low power device and an LDD region is enclosed by the added P-type dopant using lateral diffusion of the P-type dopant.
- the implantation energy and dopant are optimized to form a graded dopant profile of the LDD region to reduce an electric field impressed on the LDD junction, and the dopant profile is graded by lowering a junction depth of the LDD region to prevent the short channel effect and to improve a roll-of characteristic of threshold voltage.
- the examples described herein may be used to implement a MOS transistor, of which roll-of characteristic of threshold voltage and BVDss characteristic are improved by using P-type dopant diffusion after forming a gate sidewall spacer.
- CMOS complementary metal-oxide-semiconductor
- a gate is formed 2,500 ⁇ thick.
- N or P-type LDD is formed.
- a sidewall spacer is provided to the gate.
- As ion implantation is carried out to form heavily doped source and drain regions.
- P-type dopant is heavily re-implanted to form a diffusion source/drain region.
- the LDD region is enclosed by the P-type dopant using lateral diffusion of the P-type dopant by optimizing a dose and implantation energy of the P-type dopant.
- FIG. 2 is a cross-sectional diagram of an example semiconductor device having an LDD region enclosed by a diffusion source/drain region.
- a field oxide layer 36 is formed on a P- or N-type single crystalline semiconductor substrate to define an active area for an N or P-well 31 .
- a gate oxide layer 32 is formed on the active area of the substrate by oxidation.
- a gate electrode 33 of polysilicon is formed on the gate oxide layer 32 .
- LDD regions 34 lightly doped with dopant are formed in the active area of the substrate to be aligned with the gate electrode 33 .
- An insulating layer spacer 38 is provided to a sidewall of the gate electrode 33 .
- Source and drain regions 35 heavily doped with N or P-type dopant are formed in the active area of the substrate to be adjacent to the LDD regions 34 , respectively, using As impurity ions, and additional P-type dopant is implanted in the source and drain regions 35 to enclose the LDD regions therein, respectively.
- a Co-silicide layer 37 is formed on the gate electrode 33 and the source and drain regions 35 only.
- FIGS. 3A to 3 F are cross-sectional diagrams depicting an example method of fabricating a semiconductor device having an LDD region enclosed by a diffusion source/drain region in which the semiconductor device is a MOS transistor.
- a device isolation layer 36 is formed by a shallow trench isolation (STI) process in a field area on a semiconductor substrate to define an active area therein.
- the semiconductor substrate is an N or P-type single crystalline semiconductor substrate.
- a P or N-well 31 is formed in the active area of the semiconductor substrate. Ion implantation for threshold voltage adjustment is carried out on the semiconductor substrate.
- a thin oxide layer 32 is formed 30 ⁇ thick on the active area of the semiconductor substrate.
- a polysilicon layer 33 is formed 2500 ⁇ thick on the thin oxide layer 32 .
- the polysilicon layer 33 is patterned by photolithography to form a gate 33 .
- LDD ion implantation is carried out on the substrate to form LDD regions 34 to be aligned with the gate 33 using the gate 33 as an LDD ion implantation mask.
- an oxide layer 8 is deposited 1,000 ⁇ 1,300 ⁇ thick over the substrate.
- the oxide layer 8 is etched to remain on a sidewall of the gate 33 including the gate oxide layer 32 only to form a sidewall spacer 38 .
- Source/drain ion implantation is carried out on the substrate to form N+ or P+ source and drain regions 35 . In doing so, the source/drain regions 35 are aligned with the gate 33 and partially overlapped with the LDD regions 34 , respectively.
- P-type impurity ion implantation is carried out on the substrate to heavily dope the source and drain regions 35 with P-type dopant.
- P-type diffusion source/drain regions 39 are formed using lateral diffusion of the P-type dopant.
- a Co layer is formed 90 ⁇ thick over the substrate, and a TiN layer is stacked 150 ⁇ thick on the Co layer.
- First annealing is carried out on the substrate to form a silicide layer on the gate and the source and drain regions 39 .
- the Co and TiN layers failing to react are removed, and second annealing is carried out on the substrate to complete salicidation.
- P-type dopant is additionally implanted into the N+ source and drain regions 35 to form the P-type diffusion source and drain regions 39 , and a junction profile of the LDD region 34 is graded using the diffusion property of the P-type dopant.
- the examples described herein may be used to raise BVDss to enhance leakage current.
- FIG. 4 is a graph of a breakdown voltage (BVDss) between source and drain, in which ‘Ids’ indicates drain saturation current.
- BVDss breakdown voltage
- FIG. 5 is a graph depicting short channel effect enhancement in the example semiconductor device described herein, in which ‘Vt 1 ’ indicates threshold voltage.
- Vt 1 indicates threshold voltage.
- enhancement of short channel effect is shown in case of the example LDD structure.
- the junction profile of the LDD region is graded to raise the breakdown voltage between the source and drain, whereby the leakage current in the off-state of the MOS transistor can be enhanced.
- the example semiconductor device and method disclosed herein enhances the roll-off characteristic of the threshold voltage of the related art DDD structure.
- the example semiconductor device and method described herein applies the P and Co implantation to control the profile of the LDD region.
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Abstract
Description
- This application is a divisional application of U.S. application Ser. No. 11/021,056 filed on Dec. 23, 2004, which claims the benefit of Korean Application No. P2003-0096991 filed on Dec. 24, 2003, which is hereby incorporated by reference.
- The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device and fabricating method thereof in which a lightly doped drain junction is graded using a diffusion property of dopant implanted in heavily doped source/drain region.
- Generally, the double diffused drain (DDD) structure has been used to improve the hot carrier effect and the like of a semiconductor device having a channel length greater than 0.35 μm. Such a device is not concerned about breakdown voltage (BVDss) between source and drain as well as roll-off of threshold voltage.
- More recently, as channel length is shortened to achieve a high degree of integration in semiconductor devices to raise the short channel effect, the DDD structure is being used less. However, it is advantageous for a low power device to have high threshold voltage and BVDss in securing junction leakage. As a result, the DDD structure is employed in part. Yet, the short channel device still has the above-noted difficulty in employing the DDD structure. For instance, a transistor as a low power device having small leakage current tends to employ the LDD (lightly doped drain) structure instead of the conventional DDD structure to enhance the short channel effect due to the reduced channel length. As the junction configuration is modified, the breakdown voltage between source and drain is lowered. This may be explained as follows. When the LDD dopant increases, a junction between N-type LDD and a P-type well is abruptly formed to increase leakage from the junction region. Meanwhile, the known process of implanting additional P-type dopant is mainly used in improving leakage characteristic and capacitance by grading a junction profile, not in the LDD region but in the source/drain region.
-
FIG. 1A is a cross-sectional diagram of a known semiconductor device having a double diffused drain (DDD) andFIG. 1B is a cross-sectional diagram of a semiconductor device having a lightly doped drain (LDD). Referring toFIG. 1A , anSTI layer 16 and an n-well or p-well 11 are formed on a semiconductor substrate. Agate oxide layer 12 is formed 30 Å thick on the substrate, and apolysilicon layer 13 is deposited over the substrate. Agate 13 is then formed by patterning the polysilicon layer by photolithography. Subsequently, a PMOS orNMOS DDD region 14 is formed in the N- or P-well 11 by ion implantation. Asidewall spacer 18 is provided to thegate 13 by depositing a nitride layer over the substrate and by etching back the nitride layer. Subsequently, ion implantation is carried out on the substrate using dopant of As and P ions to form source anddrain regions Co-silicide 17 layer on thegate 13 and the source anddrain regions - Referring to
FIG. 1B , a process of fabricating a semiconductor device having the LDD structure is similar to that of fabricating the semiconductor device having the DDD structure inFIG. 1A , except forming a PMOS orNMOS LDD region 24 instead of forming the PMOS orNMOS DDD region 14 inFIG. 1A by ion implantation. However, the short channel effect still takes place in case of applying the DDD or LDD structure to the known low power device. Moreover, a high electric field is applied to the LDD region. -
FIG. 1A is a cross-sectional diagram of a known semiconductor device having a double diffused drain (DDD). -
FIG. 1B is a cross-sectional diagram of a semiconductor device having a lightly doped drain (LDD). -
FIG. 2 is a cross-sectional diagram of an example semiconductor device having an LDD region enclosed by a diffusion source/drain region. -
FIGS. 3A to 3F are cross-sectional diagrams depicting an example method of fabricating a semiconductor device having an LDD region enclosed by a diffusion source/drain region. -
FIG. 4 is a graph of a breakdown voltage between source and drain. -
FIG. 5 is a graph for showing short channel effect enhancement in the example semiconductor device described herein. - In general, the example apparatus and methods described herein provide a semiconductor device and fabricating method thereof, in which an LDD junction is graded using phosphorous dopant diffusion of a source/drain region and by which a roll-of characteristic of threshold voltage is enhanced as well as BVDss.
- More specifically, an example semiconductor device includes a gate electrode having a gate insulating layer underneath a semiconductor substrate, a pair of lightly doped regions separated from each other in the semiconductor substrate to be aligned with the gate electrode, a pair of heavily doped regions separated from each other in the semiconductor substrate to be partially overlapped with a pair of the lightly doped regions, respectively, and a pair of diffusion source/drain regions enclosing a pair of the lightly doped regions therein, respectively. Preferably, a pair of the diffusion source/drain regions are heavily doped with additional dopant, which is preferably phosphor (P). More preferably, junction profiles of the lightly doped regions are graded due to lateral diffusion of the additional dopant.
- An example method of fabricating a semiconductor device includes forming a gate electrode having a gate insulating layer underneath on a semiconductor substrate, forming a pair of lightly doped regions separated from each other in the semiconductor substrate to be aligned with the gate electrode, forming a spacer to a sidewall of the gate electrode, forming a pair of heavily doped regions separated from each other in the semiconductor substrate to be partially overlapped with a pair of the lightly doped regions, respectively, heavily doping the heavily doped regions with additional dopant, and diffusing the additional dopant in a lateral direction toward the lightly doped regions to form a pair of diffusion source/drain regions enclosing a pair of the lightly doped regions therein, respectively. Preferably, the additional dopant is phosphor (P), and, preferably, the additional dopant is diffused to enclose a pair of the lightly doped regions to avoid a double diffused drain (DDD) structure. Preferably, junction profiles of the lightly doped regions are graded due to lateral diffusion of the additional dopant and, preferably, the method further includes the step of forming a silicide layer on the gate electrode and a pair of the heavily doped regions.
- The example semiconductor device described herein may be used to improve BVDss, which was degraded by high electric field impression on the source/drain region of the LDD semiconductor device and to improve the short channel effect.
- In the example semiconductor described herein, an LDD region is enclosed by P-type dopant using lateral diffusion of the P-type dopant added to a source/drain region, whereby the BVDss characteristic and short channel effect are improved to enhance a process margin.
- In the examples disclosed herein, P-type dopant is implanted in a source/drain region of a device applicable to a low power device and an LDD region is enclosed by the added P-type dopant using lateral diffusion of the P-type dopant. In doing so, the implantation energy and dopant are optimized to form a graded dopant profile of the LDD region to reduce an electric field impressed on the LDD junction, and the dopant profile is graded by lowering a junction depth of the LDD region to prevent the short channel effect and to improve a roll-of characteristic of threshold voltage. In particular, the examples described herein may be used to implement a MOS transistor, of which roll-of characteristic of threshold voltage and BVDss characteristic are improved by using P-type dopant diffusion after forming a gate sidewall spacer.
- The examples described herein utilize the 0.18 μm standard CMOS process and may be fabricated using the operations described below. First, a gate is formed 2,500 Å thick. N or P-type LDD is formed. A sidewall spacer is provided to the gate. As ion implantation is carried out to form heavily doped source and drain regions. P-type dopant is heavily re-implanted to form a diffusion source/drain region. The LDD region is enclosed by the P-type dopant using lateral diffusion of the P-type dopant by optimizing a dose and implantation energy of the P-type dopant.
-
FIG. 2 is a cross-sectional diagram of an example semiconductor device having an LDD region enclosed by a diffusion source/drain region. Referring toFIG. 2 , afield oxide layer 36 is formed on a P- or N-type single crystalline semiconductor substrate to define an active area for an N or P-well 31. Agate oxide layer 32 is formed on the active area of the substrate by oxidation. Agate electrode 33 of polysilicon is formed on thegate oxide layer 32.LDD regions 34 lightly doped with dopant are formed in the active area of the substrate to be aligned with thegate electrode 33. An insulatinglayer spacer 38 is provided to a sidewall of thegate electrode 33. Source anddrain regions 35 heavily doped with N or P-type dopant are formed in the active area of the substrate to be adjacent to theLDD regions 34, respectively, using As impurity ions, and additional P-type dopant is implanted in the source and drainregions 35 to enclose the LDD regions therein, respectively. ACo-silicide layer 37 is formed on thegate electrode 33 and the source and drainregions 35 only. -
FIGS. 3A to 3F are cross-sectional diagrams depicting an example method of fabricating a semiconductor device having an LDD region enclosed by a diffusion source/drain region in which the semiconductor device is a MOS transistor. Referring toFIG. 3A , adevice isolation layer 36 is formed by a shallow trench isolation (STI) process in a field area on a semiconductor substrate to define an active area therein. In this case, the semiconductor substrate is an N or P-type single crystalline semiconductor substrate. A P or N-well 31 is formed in the active area of the semiconductor substrate. Ion implantation for threshold voltage adjustment is carried out on the semiconductor substrate. Athin oxide layer 32 is formed 30 Å thick on the active area of the semiconductor substrate. Apolysilicon layer 33 is formed 2500 Å thick on thethin oxide layer 32. - Referring to
FIG. 3B , thepolysilicon layer 33 is patterned by photolithography to form agate 33. LDD ion implantation is carried out on the substrate to formLDD regions 34 to be aligned with thegate 33 using thegate 33 as an LDD ion implantation mask. - Referring to
FIG. 3C , anoxide layer 8 is deposited 1,000˜1,300 Å thick over the substrate. - Referring to
FIG. 3D , theoxide layer 8 is etched to remain on a sidewall of thegate 33 including thegate oxide layer 32 only to form asidewall spacer 38. Source/drain ion implantation is carried out on the substrate to form N+ or P+ source and drainregions 35. In doing so, the source/drain regions 35 are aligned with thegate 33 and partially overlapped with theLDD regions 34, respectively. - Referring to
FIG. 3E , additional P-type impurity ion implantation is carried out on the substrate to heavily dope the source and drainregions 35 with P-type dopant. Hence, P-type diffusion source/drain regions 39 are formed using lateral diffusion of the P-type dopant. - Referring to
FIG. 3F , a Co layer is formed 90 Å thick over the substrate, and a TiN layer is stacked 150 Å thick on the Co layer. First annealing is carried out on the substrate to form a silicide layer on the gate and the source and drainregions 39. The Co and TiN layers failing to react are removed, and second annealing is carried out on the substrate to complete salicidation. - Namely, to implement a lower power device of a short channel device below 0.18 μm, P-type dopant is additionally implanted into the N+ source and drain
regions 35 to form the P-type diffusion source and drainregions 39, and a junction profile of theLDD region 34 is graded using the diffusion property of the P-type dopant. As a result, the examples described herein may be used to raise BVDss to enhance leakage current. -
FIG. 4 is a graph of a breakdown voltage (BVDss) between source and drain, in which ‘Ids’ indicates drain saturation current. Referring toFIG. 4 , a curve—A indicates an increment of BVDss in case of the new LDD structure according to the present invention. -
FIG. 5 is a graph depicting short channel effect enhancement in the example semiconductor device described herein, in which ‘Vt1’ indicates threshold voltage. Referring toFIG. 5 , enhancement of short channel effect is shown in case of the example LDD structure. Accordingly, in the examples described herein, the junction profile of the LDD region is graded to raise the breakdown voltage between the source and drain, whereby the leakage current in the off-state of the MOS transistor can be enhanced. Additionally, the example semiconductor device and method disclosed herein enhances the roll-off characteristic of the threshold voltage of the related art DDD structure. Still further, the example semiconductor device and method described herein applies the P and Co implantation to control the profile of the LDD region. - While the examples herein have been described in detail with reference to example embodiments, it is to be understood that the coverage of this patent is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the sprit and scope of the appended claims.
Claims (4)
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US11/230,697 US20060138567A1 (en) | 2003-12-24 | 2005-09-20 | Semiconductor device and fabricating method thereof |
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KR1020030096991A KR100552808B1 (en) | 2003-12-24 | 2003-12-24 | A semiconductor device with a diffused source/drain structure, and a method thereof |
KRP2003-0096991 | 2004-12-23 | ||
US11/021,056 US7368357B2 (en) | 2003-12-24 | 2004-12-23 | Semiconductor device having a graded LDD region and fabricating method thereof |
US11/230,697 US20060138567A1 (en) | 2003-12-24 | 2005-09-20 | Semiconductor device and fabricating method thereof |
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JP (1) | JP2005191576A (en) |
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US20080224210A1 (en) * | 2007-03-13 | 2008-09-18 | Jun Cai | Short channel lv, mv, and hv cmos devices |
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KR20090007053A (en) * | 2007-07-13 | 2009-01-16 | 매그나칩 반도체 유한회사 | High voltage device and method for manufacturing the same |
CN101740392B (en) * | 2008-11-27 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor, semiconductor device and manufacture method thereof |
US7977743B2 (en) * | 2009-02-25 | 2011-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Alternating-doping profile for source/drain of a FET |
US9117843B2 (en) * | 2011-09-14 | 2015-08-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device with engineered epitaxial region and methods of making same |
KR102259080B1 (en) | 2014-09-23 | 2021-06-03 | 삼성전자주식회사 | Semiconductor device and method of manufacturing the same |
KR102230198B1 (en) | 2014-09-23 | 2021-03-19 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the same |
US10636873B2 (en) * | 2017-11-22 | 2020-04-28 | Vanguard International Semiconductor Corporation | Method of fabricating semiconductor device |
CN114420760B (en) * | 2022-03-28 | 2022-05-31 | 北京芯可鉴科技有限公司 | Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
CN115020343B (en) * | 2022-07-19 | 2023-01-31 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device |
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-
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- 2004-12-22 DE DE102004063144A patent/DE102004063144A1/en not_active Withdrawn
- 2004-12-23 US US11/021,056 patent/US7368357B2/en active Active
- 2004-12-24 JP JP2004374418A patent/JP2005191576A/en active Pending
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KR20050065221A (en) | 2005-06-29 |
JP2005191576A (en) | 2005-07-14 |
US20050184335A1 (en) | 2005-08-25 |
KR100552808B1 (en) | 2006-02-20 |
US7368357B2 (en) | 2008-05-06 |
DE102004063144A1 (en) | 2005-08-04 |
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