CN114420760B - Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit - Google Patents
Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit Download PDFInfo
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- CN114420760B CN114420760B CN202210311019.2A CN202210311019A CN114420760B CN 114420760 B CN114420760 B CN 114420760B CN 202210311019 A CN202210311019 A CN 202210311019A CN 114420760 B CN114420760 B CN 114420760B
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
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- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The invention provides a transverse double-diffusion field effect transistor, a manufacturing method, a chip and a circuit. The transistor includes: a substrate; a first well region formed in the substrate and having a first conductivity type; the second well region is formed at two sides of the first well region and has a second conduction type; a body region, wherein one part of the body region is formed in the first well region, the other part of the body region protrudes out of the upper surface of the first well region, and the body region has a first conductivity type; the drift region is formed on two sides of the body region and comprises a first step close to the body region and a second step far away from the body region, the upper surface of the first step protrudes out of the surface of the first well region, the upper surface of the second step is flush with the surface of the first well region, and the drift region has a second conductive type; the source electrode is formed on the upper surface of the body region; the drain electrode is formed on the upper surface of the second step; and a gate formed on the body region and the upper surface of the first step. The transistor provided by the invention can increase the area of a depletion region, share part of the surface electric field and improve the breakdown voltage.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a transverse double-diffusion field effect transistor, the transverse double-diffusion field effect transistor, a chip and a circuit.
Background
As a Lateral power device, a Lateral Double-Diffused MOSFET (LDMOS) has electrodes on the surface of the device, which is easy to implement monolithic integration with a low-voltage signal circuit and other devices through internal connection, and has the advantages of high voltage endurance, large gain, good linearity, high efficiency, good broadband matching performance, etc., and is now widely used in power integrated circuits, especially low-power and high-frequency circuits.
In the prior art, in order to reduce the chip size, the size of the lateral double diffused field effect transistor is made smaller and smaller, and the breakdown voltage of the transistor is reduced as a result.
Disclosure of Invention
The invention provides a manufacturing method of a transverse double-diffusion field effect transistor, the transverse double-diffusion field effect transistor, a chip and a circuit, aiming at the technical problem that the breakdown voltage of the transverse double-diffusion field effect transistor in the prior art is small.
To achieve the above object, a first aspect of the present invention provides a lateral double diffused field effect transistor, comprising: a substrate; a first well region formed within the substrate, the first well region having a first conductivity type; the second well region is formed on two sides of the first well region and has a second conduction type different from the first conduction type; a body region, wherein one part of the body region is formed in the first well region, and the other part of the body region protrudes out of the upper surface of the first well region, and the body region has a first conductivity type; the drift region is formed on two sides of the body region and comprises a first step close to the body region and a second step far away from the body region, the upper surface of the first step protrudes out of the surface of the first well region, the upper surface of the second step is flush with the surface of the first well region, and the drift region has a second conductivity type; the source electrode is formed on the upper surface of the body region; the drain electrode is formed on the upper surface of the second step; and the grid is formed on the body region and the upper surface of the first step.
Furthermore, an oxide medium layer is formed on the side wall, close to the second step, of the first step; the polycrystalline silicon of the grid electrode covers the surfaces of the oxidation medium layer and the oxidation layer of the grid electrode.
Furthermore, a silicon local oxidation isolation is formed on one side, away from the body region, of the second step.
Further, a buried layer is formed in the substrate.
Further, a guard ring is formed in the second well region.
Further, the height of the oxidation dielectric layer is 8000-12000 angstroms; the thickness of the oxidation dielectric layer is between 1500 angstroms and 2000 angstroms.
The second aspect of the present invention provides a method for manufacturing a lateral double-diffused field effect transistor, where the method for manufacturing a lateral double-diffused field effect transistor includes: forming a substrate; forming a first well region and a second well region within the substrate, wherein the first well region has a first conductivity type and the second well region has a second conductivity type different from the first conductivity type; a body region is formed in the range of the first well region, one part of the body region is formed in the first well region, and the other part of the body region protrudes out of the upper surface of the first well region; forming drift regions on two sides of the body region, wherein each drift region comprises a first step close to the body region and a second step far away from the body region, the upper surface of the first step protrudes out of the surface of the first well region, the upper surface of the second step is flush with the surface of the first well region, and the drift regions have a second conduction type; forming a gate on the body region and the upper surface of the first step; forming a drain electrode on the upper surface of the second step; and forming a source electrode on the upper surface of the body region.
Further, forming drift regions on two sides of the body region includes: performing ion implantation on two sides of the body region to form an initial drift region; and partially etching one side of the initial drift region, which is far away from the body region, one side of the first well region, which is far away from the body region, and one side of the second well region, which is far away from the body region by using an etching process.
Further, the method further comprises: and after the drift region is formed, taking the side wall of the first step close to the second step as an oxidation isolation side wall, and forming an oxidation dielectric layer on the oxidation isolation side wall.
Further, the forming an oxide dielectric layer on the oxide isolation sidewall by using the sidewall of the first step close to the second step as an oxide isolation sidewall includes: forming a layer of silicon dioxide on the surface of the transverse double-diffusion field effect transistor after the drift region is formed by utilizing chemical vapor deposition; and removing the silicon dioxide outside the oxidation isolation side wall by using an etching process.
A third aspect of the invention provides a chip comprising a lateral double diffused field effect transistor as described above.
A fourth aspect of the invention provides a circuit comprising a lateral double diffused field effect transistor as described above.
Through the technical scheme provided by the invention, the invention at least has the following technical effects:
the transverse double-diffusion field effect transistor comprises a substrate, wherein a first well region and a second well region are formed in the substrate, a body region and a drift region are formed in the first well region, and the drift region is located on two sides of the body region. One part of the body region is formed in the first well region, and the other part of the body region protrudes out of the upper surface of the first well region and has the first conductivity type. The drift region is positioned on two sides of the body region and comprises a first step close to the body region and a second step far away from the body region, the upper surface of the first step protrudes out of the surface of the first well region, the upper surface of the second step is flush with the surface of the first well region, and the drift region has a second conduction type. The source electrode is formed on the upper surface of the body region, the drain electrode is formed on the upper surface of the second step, and the grid electrode is formed on the body region and the upper surface of the first step. The source electrode and the drain electrode of the transverse double-diffusion field effect transistor are not on the same plane, so that the area of a depletion region is increased, a part of surface electric field can be shared, and the breakdown voltage is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
fig. 1 is a cross-sectional view of a first well region and a second well region formed in a method for fabricating a lateral double diffused field effect transistor according to an embodiment of the present invention;
fig. 2 is a cross-sectional view of a body region and a drift region formed in a method for fabricating a lateral double diffused field effect transistor according to an embodiment of the present invention;
FIG. 3 is a cross-sectional view of a silicon local oxidation isolation and oxidation dielectric layer formed in a method for fabricating a lateral double-diffused field effect transistor according to an embodiment of the present invention;
fig. 4 is a cross-sectional view of a lateral double diffused field effect transistor formed in a method for fabricating a lateral double diffused field effect transistor according to an embodiment of the present invention;
fig. 5 is a flowchart of a method for fabricating a lateral double diffused field effect transistor according to an embodiment of the invention.
Description of the reference numerals
1-a silicon substrate; 2-buried layer; 3-an epitaxial layer; 4-a first well region; 5-a second well region; a 6-body region; 7-a drift region; 8-silicon local oxidation isolation; 9-oxidizing the dielectric layer; 10-a source electrode; 11-a drain electrode; 12-a gate; 13-a guard ring.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
In the present invention, unless specified to the contrary, use of the terms of orientation such as "upper, lower, top, bottom" or the like are generally described with respect to the orientation shown in the drawings or the positional relationship of the components with respect to each other in the vertical, or gravitational direction.
The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
Referring to fig. 4, an embodiment of the present invention provides a lateral double diffused field effect transistor, which includes: a substrate; a first well region 4 formed in the substrate, the first well region 4 having a first conductivity type; second well regions 5 formed on both sides of the first well regions 4, the second well regions 5 having a second conductivity type different from the first conductivity type; a body region 6, a portion of the body region 6 is formed in the first well region 4, and another portion of the body region 6 protrudes from the upper surface of the first well region 4, and the body region 6 has a first conductivity type; drift regions 7 formed on both sides of the body region 6, including a first step close to the body region 6 and a second step far from the body region 6, wherein an upper surface of the first step protrudes out of a surface of the first well region 4, an upper surface of the second step is flush with the surface of the first well region 4, and the drift regions 7 have a second conductivity type; a source electrode 10 formed on an upper surface of the body region 6; a drain electrode 11 formed on an upper surface of the second step; and a gate 12 formed on the body region 6 and the upper surface of the first step.
Specifically, in the embodiment of the present invention, the lateral double diffused field effect transistor includes a substrate, and the substrate is one of a silicon substrate, a silicon germanium substrate, a silicon-on-insulator substrate, and a germanium-on-insulator substrate. In the present embodiment, the substrate is a silicon substrate. The type of substrate may be selected by those skilled in the art based on the properties of the semiconductor device to be formed, and thus should not unduly limit the scope of the present invention.
A first well region 4 and a second well region 5 are formed in the substrate, the second well region 5 is formed on two sides of the first well region 4, the first well region 4 has a first conductive type, and the second well region 5 has a second conductive type different from the first conductive type. The body region 6 and the drift region 7 are both formed in the first well region 4, the body region 6 having the first conductivity type, a portion of the body region 6 being formed in the first well region 4, and another portion protruding above the upper surface of the first well region 4. The drift region 7 is located on two sides of the body region 6 and comprises a first step close to the body region 6 and a second step far away from the body region 6, the upper surface of the first step protrudes out of the surface of the first well region 4, the upper surface of the second step 5 is flush with the surface of the first well region 4, and the drift region 7 has a second conduction type. A source electrode 10 is formed on the upper surface of the body region 6, a drain electrode 11 is formed on the upper surface of the second step, and a gate electrode 12 is formed on the upper surfaces of the body region 6 and the first step.
According to the transverse double-diffusion field effect transistor provided by the invention, the source electrode 10 and the drain electrode 11 are arranged on different planes, so that the area of a depletion region is increased, a part of surface electric field can be shared, and the breakdown voltage is improved.
Furthermore, an oxide medium layer 9 is formed on the side wall of the first step close to the second step; the polysilicon of the gate 12 covers the surfaces of the oxide dielectric layer 9 and the oxide layer of the gate 12.
Further, the height of the oxide dielectric layer 9 is 8000-12000 angstroms; the thickness of the oxide dielectric layer 9 is between 1500 angstroms and 2000 angstroms.
Specifically, in the embodiment of the invention, the sidewall between the first step and the second step is used as an oxidation isolation sidewall, the oxidation dielectric layer 9 is formed on the oxidation isolation sidewall, and the oxidation dielectric layer 9 can reduce the electric field on the surface of the drain 11, thereby avoiding the breakdown of the drain 11. The polysilicon of the gate 12 covers the surfaces of the oxide dielectric layer 9 and the oxide layer of the gate 12, and can also reduce the surface electric field of the drain. The height of the oxidation dielectric layer 9 is between 10000 angstroms and 40000 angstroms, the thickness is between 1500 angstroms and 2000 angstroms, if the oxidation dielectric layer 9 is too thick, the polysilicon of the grid 12 can not completely cover the oxidation dielectric layer 9, and if the oxidation dielectric layer 9 is too thin, the effect of reducing the surface electric field of the drain electrode 11 is weaker.
Further, a silicon local oxidation isolation 8 is formed on one side of the second step far away from the body region 6.
Specifically, in the embodiment of the present invention, a Local Oxidation of Silicon (LOCOS) isolation 8 is formed on a side of the second step away from the body region 6, and the Local Oxidation of Silicon isolation 8 can perform a good isolation function, reduce the junction capacitance, and simultaneously improve the latch-up effect and the parasitic NMOS.
Further, a buried layer 2 is formed within the substrate.
In particular, in the embodiment of the invention, the buried layer 2 is formed in the substrate, the buried layer 2 can play a role in isolation and can also reduce the on-resistance of the transverse double-diffusion field effect transistor,
further, a guard ring 13 is formed in the second well region 5.
Specifically, in the embodiment of the present invention, a guard ring 13 is formed in the second well region 5, and the guard ring 13 can perform voltage protection on the lateral double diffused field effect transistor.
Referring to fig. 1 to fig. 5, a second aspect of the present invention provides a method for fabricating a lateral double diffused field effect transistor, the method comprising: s101: forming a substrate; s102: forming a first well region 4 and a second well region 5 within the substrate, wherein the first well region 4 has a first conductivity type and the second well region 5 has a second conductivity type different from the first conductivity type; s103: a body region 6 is formed in the range of the first well region 4, one part of the body region 6 is formed in the first well region 4, and the other part of the body region 6 protrudes out of the upper surface of the first well region 4; s104: forming drift regions 7 on two sides of the body region 6, wherein the drift regions 7 comprise a first step close to the body region 6 and a second step far away from the body region 6, the upper surface of the first step protrudes out of the surface of the first well region 4, the upper surface of the second step is flush with the surface of the first well region 4, and the drift regions 7 are of a second conductivity type; s105: forming a gate electrode 12 on the body region 6 and the upper surface of the first step; s106: forming a drain electrode 11 on the upper surface of the second step; s107: a source 10 is formed at the upper surface of the body region 6.
Step S101 is first executed: a substrate is formed.
Specifically, in the embodiments of the present invention, the lateral double-diffused field effect transistor can be an N-type lateral double-diffused field effect transistor, and can also be a P-type lateral double-diffused field effect transistor. When the transverse double-diffusion field effect transistor is an N-type transverse double-diffusion field effect transistor, the first doping type is a P type, and the second doping type is an N type; when the lateral double-diffused field effect transistor is a P-type lateral double-diffused field effect transistor, the first doping type is an N-type, and the second doping type is a P-type. In the embodiment of the present invention, a P-type silicon substrate 1 is provided, an N-type heavily doped buried layer 2 is formed on the P-type silicon substrate 1, and a P-type epitaxial layer 3 is formed on the buried layer 2 as the substrate in this embodiment.
Then, step S102 is executed: a first well region 4 and a second well region 5 are formed within the substrate, wherein the first well region 4 has a first conductivity type and the second well region 5 has a second conductivity type different from the first conductivity type.
Specifically, referring to fig. 1, in the embodiment of the invention, a thin silicon dioxide layer is first oxidized on the epitaxial layer 3 to protect the epitaxial layer 3, then a photoresist is formed on the surface of the epitaxial layer 3, the photoresist is etched to form an injection window of the first well region 4, and then N-type ion injection is performed through the injection window to form the first well region 4. And forming photoresist on the surface of the epitaxial layer 3, etching the photoresist to form an injection window of the second well region 5, and then performing P-type ion injection through the injection window to form the second well region 5.
Then, step 103 is executed: a body region 6 is formed within the first well region 4, and a portion of the body region 6 is formed within the first well region 4, and another portion thereof protrudes from the upper surface of the first well region 4.
Then, step S104 is executed: drift regions 7 are formed on two sides of the body region 6, the drift regions 7 include a first step close to the body region 6 and a second step far away from the body region 6, the upper surface of the first step protrudes out of the surface of the first well region 4, the upper surface of the second step is flush with the surface of the first well region 4, and the drift regions 7 are of a second conductivity type.
Further, forming drift regions 7 on two sides of the body region 6 includes: performing ion implantation on two sides of the body region 6 to form an initial drift region; and partially etching the side of the initial drift region far away from the body region 6, the side of the first well region 4 far away from the body region 6 and the side of the second well region 5 far away from the body region 6 by using an etching process.
Specifically, in the embodiment of the present invention, a relatively thick silicon dioxide is formed by oxidizing again, a photoresist is formed on the surface of the silicon dioxide, an implantation window is formed by photolithography, and a body region 6 is formed within the first well region 4 by performing P-type ion implantation through the implantation window.
After the body region 6 is formed, photoresist is formed on the surface of the transistor again, an injection window is formed through photoetching, N-type ion injection is carried out through the injection window, initial drift regions are formed on two sides of the body region 6 in the range of the first well region 4, and the surface photoresist is removed. And etching the upper end of the second well region 5 and the initial drift region far away from the body region 6 by using an etching process to form the structure shown in fig. 2. The body region 6 is formed partially in the first well region 4 and partially protrudes from the upper surface of the first well region 4. The drift region 7 is step-shaped and comprises a first step close to the body region 6 and a second step far away from the body region 6, the upper surface of the first step protrudes out of the surface of the first well region 4, and the upper surface of the second step is flush with the surface of the first well region 4.
Then, a pre-oxide layer is grown in order to buffer the stress of the silicon nitride layer on the substrate, the silicon nitride layer is formed through low-pressure chemical vapor deposition, the silicon nitride layer is etched in a dry mode, the silicon local oxidation isolation 8 is formed through oxidation on the side, far away from the body region 6, of the second step, and then the silicon nitride layer is removed through a wet method.
Further, the method further comprises: after the drift region 7 is formed, the side wall of the first step close to the second step is used as an oxidation isolation side wall, and an oxidation dielectric layer 9 is formed on the oxidation isolation side wall.
Further, the forming an oxide dielectric layer 9 on the oxidation isolation side wall by using the side wall of the first step close to the second step as the oxidation isolation side wall includes: forming a layer of silicon dioxide on the surface of the transverse double-diffused field effect transistor after the drift region 7 is formed by chemical vapor deposition; and removing the silicon dioxide outside the oxidation isolation side wall by using an etching process.
Specifically, in the embodiment of the present invention, after the drift region 7 is formed, a layer of silicon dioxide is vapor-deposited, silicon dioxide is formed on both the oxide isolation sidewall of the first step close to the second step and the surface of the transistor, and then silicon dioxide outside the oxide isolation sidewall is removed by chemical mechanical polishing, so as to form the oxide dielectric layer 9 on the oxide isolation sidewall, please refer to fig. 3.
In the prior art, when an oxide dielectric layer is manufactured, because a source electrode and a drain electrode are located on the same plane, when the oxide dielectric layer is formed, a silicon dioxide layer needs to be formed on the plane, then an oxide dielectric layer region is defined through a photoetching process, and then the oxide dielectric layer is formed through dry etching and wet etching. The step can be used as the oxidation isolation side wall, silicon dioxide on the body region 6, the surface of the first step, the surface of the second step and the surface of the second well region 5 is removed through chemical mechanical polishing, and the oxidation dielectric layer 9 can be formed on the side wall without a photoetching process, so that the manufacturing difficulty is reduced, and the manufacturing cost is reduced.
Then, step S105 is executed: a gate 12 is formed over the body region 6 and the upper surface of the first step.
Then, step S106 is executed: a drain electrode 11 is formed on the upper surface of the second step.
Then, step S107 is executed: a source 10 is formed at the upper surface of the body region 6.
Referring to fig. 4, in the embodiment of the invention, a gate 12 is formed on the body region 6 and the upper surface of the first step, and the polysilicon of the gate 12 covers the oxide dielectric layer 9. Carry out N+Ion implantation forms a drain 11 on the top surface of the second step and a source 10 on the top surface of the body region 6. Carry out P+And ion implantation is carried out, a guard ring 13 is formed in the second well region 5, and the guard ring 13 is connected with a low level and is connected with the substrate to carry out voltage protection on the transverse double-diffused field effect transistor.
A third aspect of the invention provides a chip comprising a lateral double diffused field effect transistor as described above.
A fourth aspect of the invention provides a circuit comprising a lateral double diffused field effect transistor as described above.
The preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, however, the present invention is not limited to the specific details of the above embodiments, and various simple modifications can be made to the technical solution of the present invention within the technical idea of the present invention, and these simple modifications are within the protective scope of the present invention.
It should be noted that the various technical features described in the above embodiments can be combined in any suitable manner without contradiction, and the invention is not described in any way for the possible combinations in order to avoid unnecessary repetition.
In addition, any combination of the various embodiments of the present invention can be made, and the same should be considered as the disclosure of the present invention as long as the idea of the present invention is not violated.
Claims (12)
1. A lateral double diffused field effect transistor, comprising:
a substrate;
a first well region formed within the substrate, the first well region having a first conductivity type;
the second well region is formed on two sides of the first well region and has a second conduction type different from the first conduction type;
a body region, wherein one part of the body region is formed in the first well region, and the other part of the body region protrudes out of the upper surface of the first well region, and the body region has a first conductivity type;
the drift region is formed on two sides of the body region and comprises a first step close to the body region and a second step far away from the body region, the upper surface of the first step protrudes out of the surface of the first well region, the upper surface of the second step is flush with the surface of the first well region, and the drift region has a second conductivity type;
the source electrode is formed on the upper surface of the body region;
the drain electrode is formed on the upper surface of the second step;
and the grid is formed on the body region and the upper surface of the first step.
2. The lateral double diffused field effect transistor of claim 1 wherein the first step is formed with a layer of oxide dielectric adjacent to the sidewalls of the second step;
the polycrystalline silicon of the grid electrode covers the surfaces of the oxidation dielectric layer and the oxidation layer of the grid electrode.
3. The lateral double diffused field effect transistor of claim 1 wherein a side of the second step remote from the body region is formed with a local oxide isolation of silicon.
4. The lateral double diffused field effect transistor of claim 1 wherein a buried layer is formed within the substrate.
5. The lateral double diffused field effect transistor of claim 1 wherein a guard ring is formed within the second well region.
6. The lateral double diffused field effect transistor of claim 2 wherein the height of the oxide dielectric layer is between 8000 a and 12000 a; the thickness of the oxidation dielectric layer is between 1500 angstroms and 2000 angstroms.
7. A method for manufacturing a transverse double-diffused field effect transistor is characterized by comprising the following steps:
forming a substrate;
forming a first well region and a second well region within the substrate, wherein the first well region has a first conductivity type and the second well region has a second conductivity type different from the first conductivity type;
a body region is formed in the range of the first well region, one part of the body region is formed in the first well region, and the other part of the body region protrudes out of the upper surface of the first well region;
forming drift regions on two sides of the body region, wherein the drift regions comprise a first step close to the body region and a second step far away from the body region, the upper surface of the first step protrudes out of the surface of the first well region, the upper surface of the second step is flush with the surface of the first well region, and the drift regions have a second conductivity type;
forming a gate on the body region and the upper surface of the first step;
forming a drain electrode on the upper surface of the second step;
and forming a source electrode on the upper surface of the body region.
8. The method of claim 7, wherein forming drift regions on both sides of the body region comprises:
performing ion implantation on two sides of the body region to form an initial drift region;
and partially etching one side of the initial drift region far away from the body region, one side of the first well region far away from the body region and one side of the second well region far away from the body region by using an etching process.
9. The method of fabricating a lateral double diffused field effect transistor according to claim 7, further comprising:
and after the drift region is formed, taking the side wall of the first step close to the second step as an oxidation isolation side wall, and forming an oxidation dielectric layer on the oxidation isolation side wall.
10. The method for manufacturing a lateral double-diffused field effect transistor according to claim 9, wherein the step of forming an oxide dielectric layer on the oxide isolation sidewall by using the sidewall of the first step close to the second step as an oxide isolation sidewall comprises:
forming a layer of silicon dioxide on the surface of the transverse double-diffusion field effect transistor after the drift region is formed by utilizing chemical vapor deposition;
and removing the silicon dioxide outside the oxidation isolation side wall by using an etching process.
11. A chip comprising a lateral double diffused field effect transistor according to any one of claims 1 to 6.
12. A circuit comprising a lateral double diffused field effect transistor according to any one of claims 1 to 6.
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| CN115528117B (en) * | 2022-11-16 | 2023-06-27 | 北京智芯微电子科技有限公司 | Lateral double-diffusion field effect transistor, manufacturing method, chip and circuit |
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| CN101099242A (en) * | 2005-01-06 | 2008-01-02 | 英飞凌科技股份公司 | Ldmos transistor |
| CN111092123A (en) * | 2019-12-10 | 2020-05-01 | 杰华特微电子（杭州）有限公司 | Lateral double-diffused transistor and manufacturing method thereof |
| CN111785634A (en) * | 2020-06-30 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | LDMOS device and technological method |
| CN112002759A (en) * | 2020-08-20 | 2020-11-27 | 杰华特微电子（杭州）有限公司 | Lateral diffusion transistor and manufacturing method thereof |
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| CN101099242A (en) * | 2005-01-06 | 2008-01-02 | 英飞凌科技股份公司 | Ldmos transistor |
| CN111092123A (en) * | 2019-12-10 | 2020-05-01 | 杰华特微电子（杭州）有限公司 | Lateral double-diffused transistor and manufacturing method thereof |
| CN111785634A (en) * | 2020-06-30 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | LDMOS device and technological method |
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