CN115084232B - Heterojunction transverse double-diffusion field effect transistor, manufacturing method, chip and circuit - Google Patents

Heterojunction transverse double-diffusion field effect transistor, manufacturing method, chip and circuit Download PDF

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CN115084232B
CN115084232B CN202210858457.0A CN202210858457A CN115084232B CN 115084232 B CN115084232 B CN 115084232B CN 202210858457 A CN202210858457 A CN 202210858457A CN 115084232 B CN115084232 B CN 115084232B
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gallium nitride
region
layer
metal electrode
barrier layer
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CN115084232A (en
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余山
赵东艳
王于波
陈燕宁
付振
刘芳
王凯
吴波
邓永峰
刘倩倩
郁文
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Beijing Smartchip Microelectronics Technology Co Ltd
Beijing Core Kejian Technology Co Ltd
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Beijing Smartchip Microelectronics Technology Co Ltd
Beijing Core Kejian Technology Co Ltd
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    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

The invention provides a heterojunction transverse double-diffusion field effect transistor, a manufacturing method, a chip and a circuit, and relates to the technical field of semiconductors. The transistor includes: a substrate; a gallium nitride buffer layer formed on the substrate; a source region doped region, a gallium nitride body region, a gallium nitride drift region and a drain region doped region which are formed on the gallium nitride buffer layer side by side; the AlGaN barrier layer is formed on part of the gallium nitride drift region; the gate oxide dielectric layer is formed on the gallium nitride body region, the AlGaN barrier layer and the gallium nitride drift region which is partially not covered by the AlGaN barrier layer; a source metal electrode formed on the source region doped region; a drain metal electrode formed on the drain region doped region; and the grid metal electrode is formed on part of the grid oxide dielectric layer. The transistor provided by the invention can improve the breakdown voltage of the transistor, improve the electron mobility, ensure the speed of a device, reduce a complex field plate structure, reduce the manufacturing difficulty and reduce the production cost.

Description

Heterojunction transverse double-diffusion field effect transistor, manufacturing method, chip and circuit
Technical Field
The invention relates to the technical field of semiconductors, in particular to a heterojunction transverse double-diffusion field effect transistor, a manufacturing method of the heterojunction transverse double-diffusion field effect transistor, a chip and a circuit.
Background
As a Lateral power device, a Lateral Double-Diffused MOSFET (LDMOS) has electrodes on the surface of the device, which is easy to implement monolithic integration with a low-voltage signal circuit and other devices through internal connection, and has the advantages of high voltage endurance, large gain, good linearity, high efficiency, good broadband matching performance, etc., and is now widely used in power integrated circuits, especially low-power and high-frequency circuits.
In the prior art, the breakdown voltage of the transverse double-diffused field effect transistor is low, the electron mobility is low, the speed of a device is influenced, the surface electric field of a drift region is large, and the breakdown voltage of the transverse double-diffused field effect transistor is also reduced. The field plate can increase the surface electric field of the drift region, reduce the electric field peak value, thereby achieving the purposes of inhibiting the hot carrier effect and improving the breakdown voltage, and therefore, the field plate structure can be designed for the transverse double-diffusion field effect transistor generally, but the field plate structure has complex process, large manufacturing difficulty, high production cost and lower improvement effect on the breakdown voltage and the device speed.
Disclosure of Invention
The invention provides a heterojunction transverse double-diffusion field effect transistor manufacturing method, a heterojunction transverse double-diffusion field effect transistor, a chip and a circuit, aiming at the technical problems that in the prior art, a transverse double-diffusion field effect transistor is small in breakdown voltage, low in electron mobility, low in device speed, complex in field plate structure process, large in manufacturing difficulty, high in production cost and low in improvement effect on the breakdown voltage and the device speed.
To achieve the above object, a first aspect of the present invention provides a heterojunction lateral double diffused field effect transistor comprising: a substrate; a gallium nitride buffer layer formed on the substrate; the source region doped region, the gallium nitride body region, the gallium nitride drift region and the drain region doped region are formed on the gallium nitride buffer layer in parallel; wherein the gallium nitride body region has a first conductivity type, and the source, gallium nitride drift, and drain doped regions have a second conductivity type; the AlGaN barrier layer is formed on part of the GaN drift region; the gate oxide dielectric layer is formed on the gallium nitride body region, the aluminum gallium nitrogen barrier layer and the gallium nitride drift region which is partially uncovered by the aluminum gallium nitrogen barrier layer; the source metal electrode is formed on the source region doped region; the drain electrode metal electrode is formed on the drain region doping region; and the grid metal electrode is formed on part of the grid oxide dielectric layer.
Furthermore, the thickness of the gate oxide dielectric layer between the gate metal electrode and the gallium nitride body region is 50-150 nm.
Further, the thickness of the AlGaN barrier layer is between 20 and 50nm.
Further, the source region doped region and the drain region doped region are heavily doped with a second conductivity type.
Further, the source metal electrode and the drain metal electrode are made of Ti/Al/Ti/Au metal.
Further, the gate metal electrode is made of Ni/Au metal.
The invention provides a method for manufacturing a heterojunction transverse double-diffused field effect transistor, which comprises the following steps: forming a substrate; forming a gallium nitride buffer layer on the substrate; forming a gallium nitride drift region, a gallium nitride body region, an aluminum gallium nitrogen barrier layer, a gate oxide dielectric layer, a source region doped region and a drain region doped region; the source region doped region, the gallium nitride drift region, the gallium nitride body region and the drain region doped region are formed on the gallium nitride buffer layer side by side, the aluminum gallium nitride barrier layer is formed on part of the gallium nitride drift region, and the gate oxide dielectric layer is formed on the gallium nitride body region, the aluminum gallium nitride barrier layer and part of the gallium nitride drift region which is not covered by the aluminum gallium nitride barrier layer; the gallium nitride body region has a first conductivity type, and the source region doped region, the gallium nitride drift region, and the drain region doped region have a second conductivity type; forming a source metal electrode on the source region doped region; forming a drain metal electrode on the drain region doped region; and forming a grid metal electrode on part of the grid oxide dielectric layer.
Further, the forming of the gallium nitride drift region, the gallium nitride body region, the aluminum gallium nitride barrier layer, the gate oxide dielectric layer, the source region doped region and the drain region doped region includes: forming a first conductive type gallium nitride layer and a second conductive type gallium nitride layer which are arranged side by side on the gallium nitride buffer layer; forming the AlGaN barrier layer on part of the second conduction type GaN layer; forming the gate oxide dielectric layer on the AlGaN barrier layer, part of the first conductive type GaN layer and part of the second conductive type GaN layer which is not covered by the AlGaN barrier layer; and forming the source region doped region on the first conductive type gallium nitride layer which is not covered by the gate oxide dielectric layer through ion implantation, and forming the drain region doped region on the second conductive type gallium nitride layer which is not covered by the gate oxide dielectric layer, wherein the first conductive type gallium nitride layer which is not implanted by the ions is the gallium nitride body region, and the second conductive type gallium nitride layer which is not implanted by the ions is the gallium nitride drift region.
Further, the thickness of the gate oxide dielectric layer between the gate metal electrode and the gallium nitride body region is 50-150 nm.
Further, the thickness of the AlGaN barrier layer is between 20 and 50nm.
Further, the source region doped region and the drain region doped region are heavily doped with the second conductivity type.
Further, the source metal electrode and the drain metal electrode are made of Ti/Al/Ti/Au metal.
Further, the gate metal electrode is made of Ni/Au metal.
A third aspect of the invention provides a chip comprising a heterojunction lateral double diffused field effect transistor as described above.
A fourth aspect of the invention provides a circuit comprising a heterojunction lateral double-diffused field effect transistor as described above.
Through the technical scheme provided by the invention, the invention at least has the following technical effects:
the heterojunction transverse double-diffusion field effect transistor comprises a substrate, wherein a gallium nitride buffer layer is formed on the substrate, a source region doped region, a gallium nitride body region, a gallium nitride drift region and a drain region doped region are formed on the gallium nitride buffer layer side by side, the gallium nitride body region has a first conduction type, the source region doped region, the gallium nitride drift region and the drain region doped region have a second conduction type, an aluminum gallium nitrogen barrier layer is formed on part of the gallium nitride drift region, a gate oxide dielectric layer is formed on the gallium nitride body region, the aluminum gallium nitrogen barrier layer and the gallium nitride drift region which is not partially covered by the aluminum gallium nitrogen barrier layer, a source metal electrode is formed on the source region doped region, a drain metal electrode is formed on the drain region doped region, and a gate metal electrode is formed on part of the gate oxide dielectric layer. The heterojunction that aluminium gallium nitrogen barrier layer and gallium nitride drift region below formed produces two-dimentional electron gas, utilize the electron concentration of two-dimentional electron gas can improve electron mobility, improve horizontal double-diffused field effect transistor's device speed, the high advantage of gallium nitride wide band gap and critical breakdown field has been utilized simultaneously has improved horizontal double-diffused field effect transistor's breakdown voltage, avoid the problem that the breakdown voltage that horizontal double-diffused field effect transistor drift region surface electric field arouses is low, and need not add complicated field plate structure, reduce the preparation degree of difficulty, reduce manufacturing cost.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
fig. 1 is a cross-sectional view of a gan buffer layer formed in a method for fabricating a heterojunction lateral double-diffused fet according to an embodiment of the present invention;
fig. 2 is a cross-sectional view of a second conductivity type gallium nitride layer formed in a method for fabricating a heterojunction lateral double-diffused field effect transistor according to an embodiment of the present invention;
fig. 3 is a cross-sectional view of a first conductivity type gallium nitride layer formed in a method for fabricating a heterojunction lateral double-diffused field effect transistor according to an embodiment of the present invention;
fig. 4 is a cross-sectional view of an aluminum-gallium-nitrogen barrier layer formed in a method for manufacturing a heterojunction lateral double-diffused field effect transistor according to an embodiment of the present invention;
FIG. 5 is a cross-sectional view of a gate oxide dielectric layer formed in a method for fabricating a heterojunction lateral double-diffused field effect transistor according to an embodiment of the present invention;
fig. 6 is a cross-sectional view of a source region doped region, a drain region doped region, a gallium nitride body region and a gallium nitride drift region formed in a method for manufacturing a heterojunction lateral double-diffused field effect transistor according to an embodiment of the present invention;
fig. 7 is a cross-sectional view of a source metal electrode and a drain metal electrode formed in a method for fabricating a heterojunction lateral double-diffused field effect transistor according to an embodiment of the present invention;
FIG. 8 is a cross-sectional view of a heterojunction lateral double-diffused field effect transistor formed in a method of fabricating a heterojunction lateral double-diffused field effect transistor according to an embodiment of the present invention;
fig. 9 is a flowchart of a method for fabricating a heterojunction lateral double-diffused field effect transistor according to an embodiment of the present invention.
Description of the reference numerals
1-a substrate; 2-a gallium nitride buffer layer; 3-a second conductivity type gallium nitride layer; 4-a first conductivity type gallium nitride layer; 5-AlGaN barrier layer; 6-a gate oxide dielectric layer; 7-source region doped region; 8-a drain region doped region; 9-gallium nitride body region; a 10-gallium nitride drift region; 11-source metal electrode; 12-a drain metal electrode; 13-gate metal electrode.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
In the present invention, unless specified to the contrary, use of the terms of orientation such as "upper, lower, top, bottom" or the like are generally described with respect to the orientation shown in the drawings or the positional relationship of the components with respect to each other in the vertical, or gravitational direction.
The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
Referring to fig. 8, a first aspect of the present invention provides a heterojunction lateral double-diffused field effect transistor, comprising: a substrate 1; a gallium nitride buffer layer 2 formed on the substrate 1; a source region doped region 7, a gallium nitride body region 9, a gallium nitride drift region 10 and a drain region doped region 8 which are formed on the gallium nitride buffer layer 2 side by side; wherein the gallium nitride body region 9 has a first conductivity type, the source region doped region 7, the gallium nitride drift region 10 and the drain region doped region 8 have a second conductivity type; an AlGaN barrier layer 5 formed on a part of the GaN drift region 10; a gate oxide dielectric layer 6 formed on the gallium nitride body region 9, the AlGaN barrier layer 5 and the gallium nitride drift region 10 not covered by the AlGaN barrier layer 5; a source metal electrode 11 formed on the source region doped region 7; a drain metal electrode 12 formed on the drain region doped region 8; and a gate metal electrode 13 formed on a part of the gate oxide dielectric layer 6.
Specifically, in the embodiment of the present invention, the substrate 1 is a silicon substrate or a silicon carbide substrate. In the present embodiment, the substrate 1 is a silicon carbide substrate. The type of substrate may be selected by those skilled in the art based on the properties of the semiconductor device to be formed, and thus should not unduly limit the scope of the present invention. A gan buffer layer 2 is formed on the substrate 1, and the gan buffer layer 2 is lightly doped with a first conductive type. An active region doping region 7, a gallium nitride body region 9, a gallium nitride drift region 10 and a drain region doping region 8 are formed on the gallium nitride buffer layer 2 side by side, the gallium nitride body region 9 has a first conductivity type, the source region doping region 7, the gallium nitride drift region 10 and the drain region doping region 8 have a second conductivity type, and the first conductivity type lightly doped gallium nitride buffer layer 2, the source region doping region 7 and the drain region doping region 8 can form a reverse PN junction to avoid electric leakage of the device.
An aluminum gallium nitride barrier layer 5 is formed on a part of the gallium nitride body region 9 close to the joint of the drain region doping region 8 and the gallium nitride body region 9, and a gallium nitride drift region 10 is far thicker than the aluminum gallium nitride barrier layer 5 and only has spontaneous polarization; the aluminum gallium nitrogen barrier layer 5 is thin, the lattice constant of the aluminum gallium nitrogen (AlGaN) material is larger than that of the gallium nitride (GaN) material, the aluminum gallium nitrogen barrier layer 5 is under tensile stress due to the lattice mismatch of the aluminum gallium nitrogen barrier layer and the gallium nitrogen (AlGaN) material, and the aluminum gallium nitrogen barrier layer 5 has piezoelectric polarization and spontaneous polarization. At this time, the total polarization of the aluminum-gallium-nitrogen blocking layer 5 and the spontaneous polarization of the gallium nitride drift region 10 partially cancel each other, and the polarization of the two layers are negative, that is, positive polarization charges are generated at the respective lower interfaces, negative polarization charges are generated at the upper interfaces, and finally, since the spontaneous polarization and the compressive polarization of the aluminum-gallium-nitrogen blocking layer 5 are both stronger than those of the gallium nitride drift region 10, a net positive polarization charge is formed after the charges cancel at the interfaces. According to the charge balance principle, negatively charged electrons with the same magnitude as the positive polarization charge density are induced at the interface of the gallium nitride drift region 10 and the aluminum gallium nitride barrier layer 5.
Because the forbidden bandwidth of the materials of the gallium nitride drift region 10 and the aluminum gallium nitrogen barrier layer 5 are different, the forbidden bandwidth of the aluminum gallium nitrogen is higher than that of the gallium nitride, so that a band step difference exists at the bottom of the conduction band of the gallium nitride and the gallium nitride, the band step difference of the conduction band and a large amount of positive charges at the interface can bend the energy band at the bottom of the conduction band, and the energy band bending can form a two-dimensional potential well at the heterojunction interface. The two-dimensional potential well can limit polarization-induced electrons in the potential well, and the electrons can only do two-dimensional motion in the potential well along a plane parallel to the abrupt junction interface to form a two-dimensional electron gas. The electron mobility of the two-dimensional electron gas structure is more than 2 times of the electron mobility of the body, the electron mobility can be improved by utilizing the electron concentration of the two-dimensional electron gas, and the device speed of the transverse double-diffusion field effect transistor is improved. In the AlGaN/GaN heterojunction structure, even if the AlGaN barrier layer is not doped at all, the surface density of the induced two-dimensional electron gas can reach 2 multiplied by 10 by virtue of huge polarized positive charges 13 cm -2 The above.
Meanwhile, the forbidden bandwidth of the gallium nitride body region 9 and the gallium nitride drift region 10 is high in critical breakdown electric field, the breakdown voltage of the transverse double-diffusion field effect transistor is improved, and the problem of low breakdown voltage caused by the surface electric field of the drift region of the transverse double-diffusion field effect transistor can be solved, so that a complicated field plate structure is not needed to be added, only a grid needs to be manufactured, namely, the grid oxide dielectric layer 6 is formed on the gallium nitride body region 9, the aluminum gallium nitrogen barrier layer 5 and the gallium nitride drift region 10 which is not covered by the aluminum gallium nitrogen barrier layer 5, and the grid metal electrode 13 is formed on part of the grid oxide dielectric layer 6, the manufacturing difficulty is reduced, and the production cost is reduced. The gate oxide dielectric layer 6 is formed over the gallium nitride body region 9 and the aluminum gallium nitride barrier layer 5, and over the gallium nitride drift region 10 not covered by the aluminum gallium nitride barrier layer 5 and in contact with the gallium nitride body region 9. A gate metal electrode 13 is formed on a portion of the gate oxide dielectric layer 6.
The source metal electrode 11 is formed on the source region doped region 7, and forms a source electrode with the source metal electrode 11, and the drain metal electrode 12 is formed on the drain region doped region 8, and forms a drain electrode with the drain metal electrode 12. The two-dimensional electron gas between the aluminum gallium nitride barrier layer 5 and the gallium nitride body region 9 below is transverse, and the source electrode and the drain electrode are respectively arranged on one side of the gallium nitride body region 9 and one side of the gallium nitride drift region 10, so that the on-resistance of the transverse double-diffusion field effect transistor can be reduced, the on-speed of the device is further improved, and the on-characteristic of the device is improved.
According to the heterojunction transverse double-diffusion field effect transistor provided by the invention, the two-dimensional electron gas is generated through the heterojunction formed by the aluminum gallium nitrogen barrier layer and the gallium nitride drift region 10 below the aluminum gallium nitrogen barrier layer, the electron mobility can be improved by utilizing the electron concentration of the two-dimensional electron gas, the device speed of the transverse double-diffusion field effect transistor is improved, meanwhile, the breakdown voltage of the transverse double-diffusion field effect transistor is improved by utilizing the advantages of a gallium nitride wide forbidden band and high critical breakdown electric field, the problem of low breakdown voltage caused by the surface electric field of the drift region of the transverse double-diffusion field effect transistor is solved, a complex field plate structure is not required to be added, the manufacturing difficulty is reduced, and the production cost is reduced.
Further, the thickness of the gate oxide dielectric layer 6 between the gate metal electrode 13 and the gallium nitride body region 9 is 50-150 nm.
Specifically, in the embodiment of the present invention, the thickness of the gate oxide dielectric layer 6 between the gate metal electrode 13 and the gallium nitride body region 9 is 50 to 150nm, and if the gate oxide dielectric layer 6 is too thick, the threshold voltage is large, and the switching speed is reduced; if the gate oxide dielectric layer 6 is too thin, defects are easily generated during chemical vapor deposition, breakdown is easy, and the chemical vapor deposition process is not easy to control, so that the uniformity of the gate oxide dielectric layer 6 is affected. Preferably, the thickness of the gate oxide dielectric layer 6 between the gate metal electrode 13 and said gallium nitride body region 9 is 100nm.
Further, the thickness of the AlGaN barrier layer 5 is between 20 and 50nm.
Specifically, in the embodiment of the invention, the thickness of the AlGaN barrier layer 5 is 20-50 nm, and if the AlGaN barrier layer 5 is too thick, the thickness of the gate oxide dielectric layer 6 is not easy to control; if the AlGaN barrier layer 5 is too thin, the formed AlGaN barrier layer 5 has more defects, and the device is easy to break down. Preferably, the thickness of the AlGaN barrier layer 5 is 30nm.
Further, the thickness of the gan buffer layer 2 is 1-2 um, and if the gan buffer layer 2 is too thick, the manufacturing cost of the device will be increased; if the gan buffer layer 2 is too thin, it has no buffering effect.
Further, the thickness of the gallium nitride body region 9 and the gallium nitride drift region 10 is 50-100 nm, if the gallium nitride body region 9 and the gallium nitride drift region 10 are too thick, the production cost is increased, the flatness of the surface is affected, and the uniformity of doping is poor; if the gallium nitride body region 9 and the gallium nitride drift region 10 are too thin, the epitaxial process is not easy to control, the gallium nitride body region 9 and the gallium nitride drift region 10 are easy to have defects, and the on-resistance during working is too large, so that the loss of the device is increased, and the device characteristics are influenced.
Further, the source region doped region 7 and the drain region doped region 8 are heavily doped with the second conductivity type.
Further, the source metal electrode 11 and the drain metal electrode 12 are made of Ti/Al/Ti/Au metal.
Specifically, in the embodiment of the present invention, the source metal electrode 11 and the drain metal electrode 12 can form ohmic contacts in the source region doped region 7 and the drain region doped region 8, respectively, so as to shield partial high voltage influence, reduce leakage current injection of the source ohmic contact, and thereby improve off-state breakdown voltage of the lateral double-diffused field effect transistor.
Further, the gate metal electrode 13 is made of Ni/Au metal.
Referring to fig. 1 to fig. 9, a second aspect of the present invention provides a method for fabricating a heterojunction lateral double-diffused field effect transistor, the method comprising: s101: forming a substrate 1; s102: forming a gallium nitride buffer layer 2 on the substrate 1; s103: forming a gallium nitride drift region 10, a gallium nitride body region 9, an aluminum gallium nitrogen barrier layer 5, a gate oxide dielectric layer 6, a source region doped region 7 and a drain region doped region 8; the source region doped region 7, the gallium nitride drift region 10, the gallium nitride body region 9 and the drain region doped region 8 are formed on the gallium nitride buffer layer 2 side by side, the aluminum gallium nitride barrier layer 5 is formed on a part of the gallium nitride drift region 10, and the gate oxide dielectric layer 6 is formed on the gallium nitride body region 9, the aluminum gallium nitride barrier layer 5 and the gallium nitride drift region 10 which is not covered by the aluminum gallium nitride barrier layer 5; the gallium nitride body region 9 has a first conductivity type, the source doped region 7, the gallium nitride drift region 10 and the drain doped region 8 have a second conductivity type; s104: forming a source metal electrode 11 on the source region doped region 7; s105: forming a drain metal electrode 12 on the drain region doped region 8; s106: and forming a gate metal electrode 13 on part of the gate oxide dielectric layer 6.
First, step S101 is executed: a substrate 1 is formed.
Referring to fig. 1, in detail, in the embodiment of the invention, the lateral double-diffused field effect transistor can be an N-type lateral double-diffused field effect transistor and can also be a P-type lateral double-diffused field effect transistor. When the transverse double-diffusion field effect transistor is an N-type transverse double-diffusion field effect transistor, the first conduction type is a P type, and the second conduction type is an N type; when the lateral double-diffused field effect transistor is a P-type lateral double-diffused field effect transistor, the first conductivity type is an N-type, and the second conductivity type is a P-type.
Then, step S102 is executed: a gallium nitride buffer layer 2 is formed on the substrate 1.
Specifically, in the embodiment of the present invention, the gallium nitride buffer layer 2 is formed on the substrate 1 by an epitaxial process.
Step S103 is then executed: forming a gallium nitride drift region 10, a gallium nitride body region 9, an aluminum gallium nitride barrier layer 5, a gate oxide dielectric layer 6, a source region doped region 7 and a drain region doped region 8; the source region doped region 7, the gallium nitride drift region 10, the gallium nitride body region 9 and the drain region doped region 8 are formed on the gallium nitride buffer layer 2 side by side, the aluminum gallium nitride barrier layer 5 is formed on a part of the gallium nitride drift region 10, and the gate oxide dielectric layer 6 is formed on the gallium nitride body region 9, the aluminum gallium nitride barrier layer 5 and the gallium nitride drift region 10 which is not covered by the aluminum gallium nitride barrier layer 5; the gallium nitride body region 9 has a first conductivity type and the source region doped region 7, the gallium nitride drift region 10 and the drain region doped region 8 have a second conductivity type.
Further, the forming of the gallium nitride drift region 10, the gallium nitride body region 9, the aluminum gallium nitride barrier layer 5, the gate oxide dielectric layer 6, the source region doped region 7 and the drain region doped region 8 includes: forming a first conductive type gallium nitride layer 4 and a second conductive type gallium nitride layer 3 which are arranged side by side on the gallium nitride buffer layer 2; forming the aluminum gallium nitride barrier layer 5 on part of the second conductive type gallium nitride layer 3; forming the gate oxide dielectric layer 6 on the aluminum gallium nitride barrier layer 5, part of the first conductive type gallium nitride layer 4 and part of the second conductive type gallium nitride layer 3 which is not covered by the aluminum gallium nitride barrier layer 5; forming the source region doped region 7 on the first conductive type gallium nitride layer 4 which is not covered by the gate oxide dielectric layer 6 through ion implantation, and forming the drain region doped region 8 on the second conductive type gallium nitride layer 3 which is not covered by the gate oxide dielectric layer 6, wherein the first conductive type gallium nitride layer 4 which is not ion implanted is the gallium nitride body region 9, and the second conductive type gallium nitride layer 3 which is not ion implanted is the gallium nitride drift region 10.
Further, the source region doped region 7 and the drain region doped region 8 are heavily doped with the second conductivity type.
Specifically, in the embodiment of the present invention, after the gallium nitride buffer layer 2 is formed, a layer of N-type gallium nitride is epitaxially grown to form the second conductive type gallium nitride layer 3, a layer of silicon dioxide is chemically vapor-deposited on the upper surface of the second conductive type gallium nitride layer 3, a photoresist is formed on the surface of the silicon dioxide, the photoresist is etched to form the first etching window, and the silicon dioxide and the second conductive type gallium nitride layer 3 are dry-etched through the first etching window, so as to form the structure shown in fig. 2. Then, P-type gan is selectively epitaxial, the silicon dioxide on the surface of the second conductive type gan layer 3 is removed, and the excess P-type gan is chemically and mechanically polished to form the first conductive type gan layer 4 shown in fig. 3. And then extending a layer of AlGaN, and etching the AlGaN to obtain the AlGaN barrier layer 5 in the figure 4, wherein the AlGaN barrier layer 5 is formed on a part of the gallium nitride body region 9, and is close to the joint of the drain region doping region 8 and the gallium nitride body region 9. Then, a layer of silicon dioxide is chemically and vapor-phase deposited on the surface, the silicon dioxide is dry-etched, and a gate oxide dielectric layer 6 is formed on the aluminum gallium nitride barrier layer 5, a part of the first conductive type gallium nitride layer 4 and the second conductive type gallium nitride layer 3 which is not covered by the aluminum gallium nitride barrier layer 5, as shown in fig. 5. Then, heavily doping N-type ions, forming a source region doped region 7 on the first conductive type gallium nitride layer 4 not covered by the gate oxide dielectric layer 6, forming a drain region doped region 8 on the second conductive type gallium nitride layer 3 not covered by the gate oxide dielectric layer 6, forming a gallium nitride body region 9 on the first conductive type gallium nitride layer 4 not ion-implanted, and forming a gallium nitride drift region 10 on the second conductive type gallium nitride layer 3 not ion-implanted, as shown in fig. 6.
Then, step S104 is executed: and forming a source metal electrode 11 on the source region doped region 7.
Then, step S105 is executed: and forming a drain metal electrode 12 on the drain region doped region 8.
Further, the source metal electrode 11 and the drain metal electrode 12 are made of Ti/Al/Ti/Au metal.
Referring to fig. 7, specifically, in the embodiment of the invention, after forming the source region doped region 7 and the drain region doped region 8, a layer of Ti/Al/Ti/Au metal is deposited by physical vapor deposition, and is etched, the metal material on the source region doped region 7 and the drain region doped region 8 is retained, the source metal electrode 11 is formed on the source region doped region 7, and the drain metal electrode 12 is formed on the drain region doped region 8.
Finally, step S106 is executed: and forming a gate metal electrode 13 on part of the gate oxide dielectric layer 6.
Further, the gate metal electrode 13 is made of Ni/Au metal.
Referring to fig. 8, in the embodiment of the invention, a layer of Ni/Au metal is physically vapor deposited on the surface of the device, and the Ni/Au metal near the source metal electrode 11 and the drain metal electrode 12 is removed by etching, so as to form the gate metal electrode 13 on a portion of the gate oxide dielectric layer 6.
Further, the thickness of the gate oxide dielectric layer 6 between the gate metal electrode 13 and the gallium nitride body region 9 is 50-150 nm.
Further, the thickness of the AlGaN barrier layer 5 is between 20 and 50nm.
A third aspect of the invention provides a chip comprising a heterojunction lateral double-diffused field effect transistor as described above.
A fourth aspect of the invention provides a circuit comprising a heterojunction lateral double-diffused field effect transistor as described above.
The preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, however, the present invention is not limited to the specific details of the above embodiments, and various simple modifications can be made to the technical solution of the present invention within the technical idea of the present invention, and these simple modifications are within the protective scope of the present invention.
It should be noted that the various technical features described in the above embodiments can be combined in any suitable manner without contradiction, and the invention is not described in any way for the possible combinations in order to avoid unnecessary repetition.
In addition, any combination of the various embodiments of the present invention can be made, and the same should be considered as the disclosure of the present invention as long as the idea of the present invention is not violated.

Claims (15)

1. A heterojunction lateral double-diffused field effect transistor, comprising:
a substrate;
the gallium nitride buffer layer is formed on the substrate and is lightly doped with a first conductive type;
the source region doped region, the gallium nitride body region, the gallium nitride drift region and the drain region doped region are formed on the gallium nitride buffer layer in parallel; wherein the gallium nitride body region has a first conductivity type, and the source region doped region, the gallium nitride drift region, and the drain region doped region have a second conductivity type;
the AlGaN barrier layer is formed on part of the GaN drift region;
the gate oxide dielectric layer is formed on the gallium nitride body region, the aluminum gallium nitrogen barrier layer and the gallium nitride drift region which is partially uncovered by the aluminum gallium nitrogen barrier layer;
the source metal electrode is formed on the source region doped region;
the drain electrode metal electrode is formed on the drain region doping region;
and the grid metal electrode is formed on part of the grid oxide dielectric layer.
2. The heterojunction lateral double-diffused field effect transistor of claim 1, wherein the thickness of the gate oxide dielectric layer between the gate metal electrode and the gallium nitride body region is between 50 and 150nm.
3. The heterojunction lateral double-diffused field effect transistor according to claim 1, wherein the thickness of the aluminum gallium nitride barrier layer is 20 to 50nm.
4. The heterojunction lateral double diffused field effect transistor of claim 1, wherein said source region doped region and said drain region doped region are heavily doped of a second conductivity type.
5. The heterojunction lateral double-diffused field effect transistor of claim 1, wherein the source metal electrode and the drain metal electrode are made of Ti/Al/Ti/Au metal.
6. The heterojunction lateral double-diffused field effect transistor of claim 1, wherein the gate metal electrode is made of Ni/Au metal.
7. A method for manufacturing a heterojunction transverse double-diffused field effect transistor is characterized by comprising the following steps:
forming a substrate;
forming a gallium nitride buffer layer on the substrate, wherein the gallium nitride buffer layer is lightly doped with a first conductive type;
forming a gallium nitride drift region, a gallium nitride body region, an aluminum gallium nitrogen barrier layer, a gate oxide dielectric layer, a source region doped region and a drain region doped region; the source region doped region, the gallium nitride drift region, the gallium nitride body region and the drain region doped region are formed on the gallium nitride buffer layer side by side, the aluminum gallium nitride barrier layer is formed on part of the gallium nitride drift region, and the gate oxide dielectric layer is formed on the gallium nitride body region, the aluminum gallium nitride barrier layer and part of the gallium nitride drift region which is not covered by the aluminum gallium nitride barrier layer; the gallium nitride body region has a first conductivity type, and the source region doped region, the gallium nitride drift region, and the drain region doped region have a second conductivity type;
forming a source metal electrode on the source region doped region;
forming a drain metal electrode on the drain region doped region;
and forming a grid metal electrode on part of the grid oxide dielectric layer.
8. The method of claim 7, wherein the forming of the gan drift region, gan body region, algan barrier layer, gate oxide dielectric layer, source region doped region and drain region doped region comprises:
forming a first conductive type gallium nitride layer and a second conductive type gallium nitride layer which are arranged side by side on the gallium nitride buffer layer;
forming the AlGaN barrier layer on part of the second conduction type GaN layer;
forming the gate oxide dielectric layer on the AlGaN barrier layer, part of the first conductive type GaN layer and part of the second conductive type GaN layer which is not covered by the AlGaN barrier layer;
and forming the source region doped region on the first conductive type gallium nitride layer which is not covered by the gate oxide dielectric layer through ion implantation, and forming the drain region doped region on the second conductive type gallium nitride layer which is not covered by the gate oxide dielectric layer, wherein the first conductive type gallium nitride layer which is not implanted by the ions is the gallium nitride body region, and the second conductive type gallium nitride layer which is not implanted by the ions is the gallium nitride drift region.
9. The method of claim 7, wherein the thickness of the gate oxide dielectric layer between the gate metal electrode and the gallium nitride body region is between 50nm and 150nm.
10. The method according to claim 7, wherein the thickness of the AlGaN barrier layer is 20-50 nm.
11. The method of claim 7, wherein the source region doped region and the drain region doped region are heavily doped with the second conductivity type.
12. The method according to claim 7, wherein the source metal electrode and the drain metal electrode are made of Ti/Al/Ti/Au metal.
13. A method of fabricating a heterojunction lateral double-diffused field effect transistor according to claim 7, wherein said gate metal electrode is made of Ni/Au metal.
14. A chip comprising a heterojunction lateral double-diffused field effect transistor according to any one of claims 1 to 6.
15. A circuit comprising a heterojunction lateral double-diffused field effect transistor according to any of claims 1 to 6.
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