CN114447102A - Gallium nitride heterojunction field effect transistor with compound semiconductor layer on substrate - Google Patents
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 109
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 98
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 239000000758 substrate Substances 0.000 title claims abstract description 33
- 230000005669 field effect Effects 0.000 title claims abstract description 21
- 150000001875 compounds Chemical class 0.000 title claims description 10
- 230000004888 barrier function Effects 0.000 claims abstract description 31
- 239000002131 composite material Substances 0.000 claims abstract description 23
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims abstract description 19
- 238000002161 passivation Methods 0.000 claims abstract description 7
- 230000005684 electric field Effects 0.000 abstract description 32
- 230000015556 catabolic process Effects 0.000 abstract description 24
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 15
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 9
- 230000002829 reductive effect Effects 0.000 abstract description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 7
- 238000004088 simulation Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005036 potential barrier Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 208000032750 Device leakage Diseases 0.000 description 1
- 241001089723 Metaphycus omega Species 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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Abstract
The invention provides a gallium nitride heterojunction field effect transistor with a composite semiconductor layer on a substrate, which sequentially comprises the following components from bottom to top: the device comprises a substrate, a gallium nitride buffer layer, a gallium nitride channel layer and an aluminum gallium nitrogen barrier layer, wherein a source electrode, a drain electrode, a P-type gallium nitride layer and a grid electrode are arranged above the aluminum gallium nitrogen barrier layer, and a passivation layer covers the upper surface of the device between the source electrode and the grid electrode and between the grid electrode and the drain electrode; a composite semiconductor structure layer formed by transversely arranging a P-type doped region and an N-type doped region is arranged between the gallium nitride buffer layer and the substrate, and the composite structure formed by the P-type doped region and the N-type doped region is introduced between the gallium nitride buffer layer and the substrate, so that the leakage current of the buffer layer can be effectively reduced, the electric field distribution of a channel and the buffer layer can be improved, the breakdown voltage of the device can be improved, and the on-resistance of the device can not be increased.
Description
Technical Field
The invention belongs to the field of microelectronics, relates to a semiconductor transistor, and particularly relates to a gallium nitride heterojunction field effect transistor with a composite semiconductor structure layer on a substrate, which can effectively improve the breakdown voltage of a device.
Background
The gallium nitride-based heterojunction field effect transistor (GaN HFET) has the excellent characteristics of large forbidden bandwidth, high critical breakdown electric field, high electron saturation velocity, good heat conduction performance, radiation resistance, good chemical stability and the like, and meanwhile, a two-dimensional electron gas heterojunction channel with high concentration and high mobility can be formed by a heterojunction structure formed by a GaN material and materials such as aluminum gallium nitrogen (AlGaN) and the like. Gallium nitride-based heterojunction field effect transistors are particularly suitable for high-voltage and high-power applications, and gallium nitride-based power devices are becoming the primary choice of high-voltage power switch modules.
The conventional GaN HFET is a lateral device, and the structure of the conventional enhancement mode GaN HFET is schematically shown in fig. 1. The structure mainly comprises a substrate, a gallium nitride (GaN) buffer layer, a gallium nitride (GaN) channel layer, an aluminum gallium nitrogen (AlGaN) potential barrier, a P-type gallium nitride layer and a source electrode, a drain electrode and a grid electrode which are formed on the aluminum gallium nitrogen (AlGaN) potential barrier, wherein the source electrode and the drain electrode form ohmic contact with the aluminum gallium nitrogen (AlGaN) potential barrier layer, and the grid electrode forms ohmic contact with the P-type gallium nitride layer.
For conventional GaN HFETs, the channel two-dimensional electron gas distribution between the gate and drain is uniform and cannot be fully depleted when the device is subjected to withstand voltages. The channel electric field is therefore concentrated primarily at the gate edge or drain edge, resulting in device breakdown at lower drain voltages. In addition, the gallium nitride (GaN) buffer layer has no limiting effect on the two-dimensional electron gas of the gallium nitride (GaN) channel layer, so that the buffer layer provides a leakage channel when the device is subjected to withstand voltage. Thus, the two-dimensional electron gas in the channel is more difficult to be depleted, and the breakdown voltage of the device is further reduced.
In order to fully exert the high critical breakdown electric field characteristics of the GaN material, researchers have proposed many technical measures for improving the voltage endurance of the device, wherein typical measures mainly include: field plate technology (e.g., gate field plate, source field plate, drain field plate), substrate transfer technology, ion implantation, buffer layer doping, superlattice buffer layer and back barrier technology, etc.
In 2001, Li J et al, in the literature (Li J, Cai S J, Pan G Z, et al. high breakdown voltage GaN HFET with field plate [ J ]. Electronics Letters,2001,37(3): 196) -197.), disclosed for the first time that a field plate shorted to the gate was used, the introduction of the gate field plate could effectively reduce the electric field peak at the gate edge, expand the channel 2DEG depletion region between the gate and the drain, make the electric field distribution between the gate and the drain more uniform, and thus improve the withstand voltage. But an additional capacitance is formed between the field plate and the channel, which degrades the frequency characteristics and switching characteristics of the device.
In 2001, Karmalkar et al used a P-type buffer layer for the first time in the literature (Karmalkar S, Deng J, Shur M S. RESURF AlGaN/GaN HEMT for high voltage power switching [ J ]. IEEE Electron Device Letters,2001,22(8):373-375.), and the channel electric field region could be extended between the entire gates and drains, thereby improving the Device channel electric field uniformity and breakdown voltage. However, the device only uses the P-type buffer layer, the withstand voltage is not improved much, and the P-type buffer layer is partially depleted of 2DEG, so that the on-resistance of the device is increased. Meanwhile, because the two-dimensional electron gas below the gate is also partially consumed, the threshold voltage of the device can float along with the thickness of the P-type buffer layer and the change of the doping concentration, which is not beneficial to the design of an enhancement type device for stabilizing the threshold voltage.
In 2016, Luo Jun et al used a structure in which a Double Buried P-Type layer was inserted into an N-doped buffer layer, and used a P-Type Buried layer to partially deplete a channel 2DEG, which is a major improvement in withstand Voltage, in a literature (Luo J, Zhao S L, Lin Z Y, et al. This approach also partially depletes the 2DEG, resulting in an increase in the on-resistance of the device. Partial depletion of the two-dimensional electron gas under the gate also affects the device threshold voltage. N-type doping of the buffer layer also results in increased device leakage.
The P-type gallium nitride back barrier layer is arranged below the gallium nitride buffer layer, the breakdown voltage of the device can be remarkably improved by inhibiting the leakage of the buffer layer and improving the electric field distribution of the buffer layer and the channel layer, and the on-resistance of the device can not be increased at the same time, the breakdown voltage of the device with the P-type gallium nitride back barrier layer is 735V as shown in fig. 2, while the withstand voltage of the conventional device shown in fig. 1 is only 485V.
However, the use of only the P-type gan back barrier layer has limited effect on the electric field modulation of the channel and buffer layers, and large electric field spikes still exist at the gate and drain edges. The average breakdown electric field intensity of the GaN HFET with the P-type gallium nitride back barrier layer is still far lower than the critical breakdown electric field intensity of a GaN material by 3 MV/cm.
Fig. 1 is a schematic structural view of a general gallium nitride-based heterojunction field effect transistor (GaN HFET), which mainly includes, from bottom to top, a substrate 101, a gallium nitride buffer layer 104, a gallium nitride channel layer 105, an aluminum-gallium-nitrogen barrier layer 106, and a source 107, a drain 111, a P-type gallium nitride layer 109, a gate 110 and a silicon nitride passivation layer 108 formed on the aluminum-gallium-nitrogen barrier layer, wherein the source and the drain respectively form ohmic contacts with the aluminum-gallium-nitrogen barrier layer, and the gate forms ohmic contacts with the P-type gallium nitride layer.
Fig. 2 is a schematic structural diagram of a conventional gallium nitride-based heterojunction field effect transistor (GaN HFET) with a P-type gallium nitride back barrier layer, which mainly includes, from bottom to top, a substrate 101, a P-type gallium nitride back barrier layer 112, a gallium nitride buffer layer 104, a gallium nitride channel layer 105, an aluminum gallium nitride barrier layer 106, and a source 107, a drain 111, a P-type gallium nitride layer 109, a gate 110 and a silicon nitride passivation layer 108 formed on the aluminum gallium nitride barrier layer, wherein the source and the drain form ohmic contacts with the aluminum gallium nitride barrier layer, and the gate forms ohmic contact with the P-type gallium nitride layer.
In summary, in the field of power electronic device application, a GaN-based HFET implementation with high voltage endurance, high threshold voltage, and low on-resistance is needed. It is important to provide a new gan device structure to solve the above problems.
Disclosure of Invention
The invention aims to modulate a channel electric field to make the distribution of the channel electric field more uniform by introducing a composite doping insertion layer on a substrate, and simultaneously avoid the degradation of saturated output current and the increase of on-resistance of a device, thereby improving the breakdown voltage and the excellent value of the device.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a gallium nitride heterojunction field effect transistor with a compound semiconductor layer on a substrate sequentially comprises from bottom to top: the device comprises a substrate 101, a gallium nitride buffer layer 104, a gallium nitride channel layer 105 and an aluminum gallium nitride barrier layer 106, wherein a source 107, a drain 111, a P-type gallium nitride layer 109 and a gate 110 are arranged above the aluminum gallium nitride barrier layer 106, wherein the source 107 and the drain 111 are in ohmic contact with the aluminum gallium nitride barrier layer 106, the gate 110 is in ohmic contact with the P-type gallium nitride layer 109 below, and a passivation layer 108 covers the upper surface of the device between the source 107 and the gate 110 and between the gate 110 and the drain 111; a composite semiconductor structure layer formed by transversely arranging a P-type doped region 102 and an N-type doped region 103 is further arranged between the gallium nitride buffer layer 104 and the substrate 101.
Preferably, an intrinsic semiconductor region 113 is also present between the P-doped region 102 and the N-doped region 103.
Preferably, the contact interface between the P-type doped region 102 and the N-type doped region 103, the contact interface between the P-type doped region 102 and the intrinsic semiconductor region 113, and the contact interface between the intrinsic semiconductor region 113 and the N-type doped region 103 are located between the left side of the source 107 and the right side of the drain 111.
Preferably, the composite semiconductor structure layer is AlxInyGazAnd N, wherein x + y + z is 1, x is more than or equal to 0 and less than or equal to 1, y is more than or equal to 0 and less than or equal to 1, and z is more than or equal to 0 and less than or equal to 1.
Preferably, the doping concentration of the P-type doped region 102 is 1 × 1016cm-3～1×1019cm-3(ii) a The doping concentration of the N-type doped region 103 is 1 × 1016cm-3～1×1020cm-3。
Preferably, the P-type doped region 102, the N-type doped region 103, and the intrinsic semiconductor region 113 are all thicker than 0 and different in thickness.
Preferably, the composite structure of the P-type doped region 102 and the N-type doped region 103 is repeatedly arranged along the source-drain direction.
The invention aims to overcome the problem of insufficient voltage endurance capability of a gallium nitride-based heterojunction field effect transistor (GaN HFET), and provides a gallium nitride heterojunction field effect transistor with a composite semiconductor structure layer on a substrate. A longitudinal electric field is introduced into a P-type doped region 102 and an N-type doped region 103 in a composite semiconductor structure layer in a device, and a buffer layer and a channel electric field are modulated together, wherein the P-type doped region 102 enables a depletion region to expand towards a drain electrode when the device is resistant to voltage, and simultaneously reduces the channel electric field near a grid electrode, the N-type doped region 103 reduces the channel electric field near the drain electrode, and meanwhile, an electric field peak is generated at a contact interface of the P-type doped region 102 and the N-type doped region 103, so that the electric field distribution of the buffer layer and a channel can be modulated effectively, the electric field distribution of the channel layer and the buffer layer is more uniform, and the breakdown voltage of the device is improved effectively.
The invention has the beneficial effects that:
1) the P-type doped region 102 allows the depletion region to expand towards the drain while the device is withstanding voltage, while reducing the channel peak electric field near the gate.
2) The N-doped region 103 can reduce the electric field concentration effect near the drain, reducing the channel peak electric field near the drain.
3) The P-type doped region 102 and the N-type doped region 103 act together to effectively modulate the electric field distribution of the buffer layer and the channel, improve the transverse electric field of the middle region of the channel, and simultaneously make the electric field distribution of the channel layer and the buffer layer more uniform, thereby effectively improving the breakdown voltage of the device.
4) The composite semiconductor structure layer is far away from the channel layer, and the middle of the composite semiconductor structure layer is shielded by the thicker gallium nitride buffer layer, so that the two-dimensional electron gas concentration of the channel layer is hardly influenced, and the on-resistance and the saturated output current of a device with the composite semiconductor structure layer on the substrate are not degraded compared with those of a conventional structure device.
Drawings
Fig. 1 is a schematic view of a conventional gallium nitride based heterojunction field effect transistor (GaN HFET) structure.
Fig. 2 is a schematic structural view of a conventional gallium nitride-based heterojunction field effect transistor (GaN HFET) with a P-type gallium nitride back barrier layer.
Fig. 3 is a schematic structural diagram of a GaN HFET having a composite semiconductor structure layer on a substrate according to embodiment 1 of the present invention.
Fig. 4 is a schematic structural diagram of a GaN HFET having a composite semiconductor structure layer on a substrate according to embodiment 2 of the present invention.
Fig. 5 is a schematic structural diagram of a GaN HFET having a composite semiconductor structure layer on a substrate according to embodiment 3 of the present invention.
FIG. 6 is a comparison of the breakdown characteristics of example 1 provided by the present invention with a conventional GaN HFET and a GaN HFET with a P-type gallium nitride back barrier layer.
FIG. 7 is a comparison of the channel electric field profiles for example 1 in accordance with the present invention in breakdown with conventional GaN HFETs and GaN HFETs with P-type gallium nitride back barrier layers.
101 is a substrate, 102 is a P-type doped region, 103 is an N-type doped region, 104 is a gallium nitride buffer layer, 105 is a gallium nitride channel layer, 106 is an aluminum gallium nitride barrier layer, 107 is a source, 108 is a passivation layer, 109 is a P-type doped gallium nitride layer, 110 is a gate, 111 is a drain, and 113 is an intrinsic semiconductor region.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
As shown in fig. 3, a gan heterojunction field effect transistor with a composite semiconductor structure layer on a substrate comprises, from bottom to top: the device comprises a substrate 101, a gallium nitride buffer layer 104, a gallium nitride channel layer 105 and an aluminum gallium nitride barrier layer 106, wherein a source 107, a drain 111, a P-type gallium nitride layer 109 and a gate 110 are arranged above the aluminum gallium nitride barrier layer 106, wherein the source 107 and the drain 111 are in ohmic contact with the aluminum gallium nitride barrier layer 106, the gate 110 is in ohmic contact with the P-type gallium nitride layer 109 below, and a passivation layer 108 covers the upper surface of the device between the source 107 and the gate 110 and between the gate 110 and the drain 111; a composite semiconductor structure layer formed by transversely arranging a P-type doped region 102 and an N-type doped region 103 is further arranged between the gallium nitride buffer layer 104 and the substrate 101.
Preferably, the position of the contact interface between the P-type doped region 102 and the N-type doped region 103 is arbitrarily set between the left side of the source 107 and the right side of the drain 111.
Preferably, the composite semiconductor structure layer is AlxInyGazAnd (3) N material. Wherein x + y + z is 1, x is more than or equal to 0 and less than or equal to 1, y is more than or equal to 0 and less than or equal to 1, and z is more than or equal to 0 and less than or equal to 1.
Preferably, the doping concentration of the P-type doped region 102 is 1 × 1016cm-3～1×1019cm-3(ii) a The doping concentration of the N-type doped region 103 is 1 × 1016cm-3～1×1020cm-3。
In order to better implement the present invention, the contact interface between the P-type doped region 102 and the N-type doped region 103 should be located as close to the drain edge as possible.
Preferably, the P-type doped region 102, the N-type doped region 103, and the intrinsic semiconductor region 113 have thicknesses greater than 0 and different thicknesses.
Simulation parameter settings for example 1 and comparative conventional GaN HFETs and P-GaN back barrier GaN HFETs are shown in table 1.
TABLE 1 device simulation Structure parameters
The simulation results of example 1 and the comparative conventional GaN HFET and P-GaN back barrier GaN HFET are shown in table 2.
TABLE 2 comparison of device simulation results
The on-resistances of the device structures in example 1 shown in Table 2 were 0.4 m.OMEGA.. multidot.cm in the same manner as those of the conventional devices2It is demonstrated that the device structure of the present invention does not cause degradation of the on-resistance. Fig. 6 and 7 show simulation results of this embodiment 1, which fully embody the advantages of the invention of raising the breakdown voltage. From the simulation results, as shown in fig. 6, the breakdown voltage of the conventional GaN HFET device is 485V, the breakdown voltage of the GaN HFET device with the P-type GaN back barrier is 734V, and the device breakdown voltage of the embodiment 1 of the present invention is increased to 1210V.
Comparison of the channel electric field intensity distribution at break-down of fig. 7 shows that example 1 can significantly reduce the electric field spike near the drain while making the electric field distribution of the channel layer more uniform.
Example 2
As shown in fig. 4, the present embodiment is different from embodiment 1 in that: an intrinsic semiconductor region 113 is also present between the P-doped region 102 and the N-doped region 103.
Preferably, the contact interface of the P-type doped region 102 and the intrinsic semiconductor region 113, and the contact interface of the intrinsic semiconductor region 113 and the N-type doped region 103 are located between the left side of the source 107 and the right side of the drain 111.
Example 3
As shown in fig. 5, the present embodiment is different from embodiment 1 in that: the composite structure of the P-type doped region 102 and the N-type doped region 103 is repeatedly arranged along the gate-to-drain direction.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (7)
1. A gallium nitride heterojunction field effect transistor having a compound semiconductor layer on a substrate, characterized in that: from supreme including in proper order down: the device comprises a substrate (101), a gallium nitride buffer layer (104), a gallium nitride channel layer (105) and an aluminum gallium nitride barrier layer (106), wherein a source electrode (107), a drain electrode (111), a P-type gallium nitride layer (109) and a grid electrode (110) are arranged above the aluminum gallium nitride barrier layer (106), the source electrode (107) and the drain electrode (111) form ohmic contact with the aluminum gallium nitride barrier layer (106), the grid electrode (110) forms ohmic contact with the P-type gallium nitride layer (109) below, and a passivation layer (108) covers the space between the source electrode (107) and the grid electrode (110) and the space between the grid electrode (110) and the drain electrode (111) on the upper surface of the device; and a composite semiconductor structure layer formed by transversely arranging a P-type doped region (102) and an N-type doped region (103) is arranged between the gallium nitride buffer layer (104) and the substrate (101).
2. A gallium nitride heterojunction field effect transistor having a compound semiconductor layer on a substrate according to claim 1, wherein: an intrinsic semiconductor region (113) is also present between the P-doped region (102) and the N-doped region (103).
3. A gallium nitride heterojunction field effect transistor having a compound semiconductor layer on a substrate according to claim 1 or 2, wherein: the contact interface of the P-type doped region (102) and the N-type doped region (103), the contact interface of the P-type doped region (102) and the intrinsic semiconductor region (113), and the contact interface of the intrinsic semiconductor region (113) and the N-type doped region (103) are positioned between the left side of the source (107) and the right side of the drain (111).
4. A gallium nitride heterojunction field effect transistor having a compound semiconductor layer on a substrate according to claim 1 or 2, wherein: the composite semiconductor structure layer is AlxInyGazAnd N, wherein x + y + z is 1, x is more than or equal to 0 and less than or equal to 1, y is more than or equal to 0 and less than or equal to 1, and z is more than or equal to 0 and less than or equal to 1.
5. A gallium nitride heterojunction field effect transistor having a compound semiconductor layer on a substrate according to claim 1 or 2, wherein: the doping concentration of the P-type doped region (102) is 1 multiplied by 1016cm-3～1×1019cm-3(ii) a The doping concentration of the N-type doped region (103) is 1 x 1016cm-3～1×1020cm-3。
6. A gallium nitride heterojunction field effect transistor having a compound semiconductor layer on a substrate according to claim 1 or 2, wherein: the thickness of the P-type doped region (102), the N-type doped region (103) and the intrinsic semiconductor region (113) is larger than 0 and different.
7. A gallium nitride heterojunction field effect transistor having a compound semiconductor layer on a substrate according to claim 1, wherein: the composite structure of the P-type doped region (102) and the N-type doped region (103) is repeatedly arranged along the direction from the source electrode to the drain electrode.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115084232A (en) * | 2022-07-21 | 2022-09-20 | 北京芯可鉴科技有限公司 | Heterojunction transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
| CN117199137A (en) * | 2023-09-18 | 2023-12-08 | 先之科半导体科技(东莞)有限公司 | Field effect transistor with pulse power amplifier |
| CN117476763A (en) * | 2023-12-28 | 2024-01-30 | 深圳天狼芯半导体有限公司 | E-HEMT with low leakage current and preparation method |
| CN117542876A (en) * | 2024-01-10 | 2024-02-09 | 英诺赛科（珠海）科技有限公司 | Semiconductor device and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194819A (en) * | 2011-04-26 | 2011-09-21 | 电子科技大学 | Enhanced GaN heterojunction field effect transistor based on metal oxide semiconductor (MOS) control |
| CN103035706A (en) * | 2013-01-04 | 2013-04-10 | 电子科技大学 | Vertical gallium nitride based nitride heterojunction field effect transistor with polarized doped current barrier layer |
| CN103531615A (en) * | 2013-10-15 | 2014-01-22 | 苏州晶湛半导体有限公司 | Nitride power transistor and manufacturing method thereof |
| CN104347701A (en) * | 2014-09-10 | 2015-02-11 | 电子科技大学 | Field effect transistor with composite passivation-layer structure |
-
2022
- 2022-01-25 CN CN202210085762.0A patent/CN114447102A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194819A (en) * | 2011-04-26 | 2011-09-21 | 电子科技大学 | Enhanced GaN heterojunction field effect transistor based on metal oxide semiconductor (MOS) control |
| CN103035706A (en) * | 2013-01-04 | 2013-04-10 | 电子科技大学 | Vertical gallium nitride based nitride heterojunction field effect transistor with polarized doped current barrier layer |
| CN103531615A (en) * | 2013-10-15 | 2014-01-22 | 苏州晶湛半导体有限公司 | Nitride power transistor and manufacturing method thereof |
| CN104347701A (en) * | 2014-09-10 | 2015-02-11 | 电子科技大学 | Field effect transistor with composite passivation-layer structure |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115084232A (en) * | 2022-07-21 | 2022-09-20 | 北京芯可鉴科技有限公司 | Heterojunction transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
| CN117199137A (en) * | 2023-09-18 | 2023-12-08 | 先之科半导体科技(东莞)有限公司 | Field effect transistor with pulse power amplifier |
| CN117476763A (en) * | 2023-12-28 | 2024-01-30 | 深圳天狼芯半导体有限公司 | E-HEMT with low leakage current and preparation method |
| CN117476763B (en) * | 2023-12-28 | 2024-05-28 | 深圳天狼芯半导体有限公司 | E-HEMT with low leakage current and preparation method |
| CN117542876A (en) * | 2024-01-10 | 2024-02-09 | 英诺赛科（珠海）科技有限公司 | Semiconductor device and manufacturing method thereof |
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