CN115172451A - Junction type grid enhanced GaN device based on PP heterojunction - Google Patents
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Abstract
The invention belongs to the technical field of power semiconductors, and particularly provides a junction-type grid-enhanced GaN device based on a PP heterojunction, which is used for solving the problems of narrow grid voltage swing, large grid leakage, high process requirement, high cost and the like of the conventional device. The invention uses the P-type wide bandgap semiconductor layer to exhaust the high-concentration two-dimensional electron gas below the P-type wide bandgap semiconductor layer to obtain an enhancement device; meanwhile, a P-type polycrystalline silicon layer is arranged on the P-type wide bandgap semiconductor layer, and a PP heterojunction formed by the P-type polycrystalline silicon layer and the P-type wide bandgap semiconductor layer can prevent a grid from injecting current into the P-type wide bandgap semiconductor layer, so that extremely low grid leakage is obtained; in addition, the novel junction gate can avoid the gate Schottky thermoelectric instability of the p-GaNHEMT and the influence of interface charges or traps of the dielectric layer and the semiconductor layer in the MIS structure on the reliability and the stability of the threshold voltage; finally, the invention has the advantages of large gate voltage swing, low gate leakage, small channel specific on resistance, high threshold voltage consistency, high stability and the like.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, relates to a high-voltage longitudinal/transverse semiconductor device, and particularly provides a junction-type grid-enhanced GaN device based on a PP heterojunction.
Background
The GaN device is used as a third-generation semiconductor device, and the inherent physical properties of the GaN device make the GaN device very suitable for high-frequency, high-power and other applications; the enhancement GaN device is a key point of research because it can omit the protection circuit and improve the system reliability in power electronic application.
The traditional enhancement type transverse GaN device mainly comprises a p-GaN gate or p-AlGaN gate enhancement type HEMT device, a process-gate HEMT and a HEMT adopting fluorine ion implantation. p-GaN Gate or p-AlGaN Gate enhancement HEMT device is a two-dimensional electron gas depletion device using p-GaN or p-AlGaN at the channel, as described in the documents "y.uemoto et al", "Gate Injection Transistor (GIT) -a normal-off AlGaN/GaN power transistor using reduction modulation," ieee trans. Electron Devices, vol.54, no.12, pp.3393-3399, dec.2007 ", the structure of which is shown in fig. 1; however, a PN diode formed by p-GaN or p-AlGaN and a barrier layer is conducted when the grid voltage is 3V, so that a large grid current is introduced, the driving loss is increased, the grid voltage swing is limited by the characteristic and generally does not exceed 5V, and the design difficulty of a driving circuit is increased; in addition, a reverse bias schottky contact is generally formed between the p-GaN gate and the metal gate electrode to reduce gate current, and the schottky contact has low reliability and stability, so that the reliability and stability of gate leakage are low. Recycled-gate HEMTs are obtained by etching away a portion of the barrier layer (residual thickness d) under the gate dielectric, as described in the documents "y.zhao, et al," Effects of depth on performance of AlGaN/GaN power MIS-HEMTs on the Si substrates and threshold voltage model of diffusion depth for the using HfO2 gate insulator, "Solid-State Electronics,2020, 163"; in addition, the threshold voltage of the device is increased along with the reduction of the thickness of the barrier layer reserved under the channel gate dielectric, generally about 1V-2V, and when the reserved barrier layer is thinned to a few nm, the electron mobility in the channel is greatly reduced along with the damage of the channel, so that the specific on-resistance is multiplied; moreover, the precision of the thickness d reserved by etching is very difficult to control, and the threshold voltage uniformity of the device on the wafer is obviously influenced. An enhancement type device can be realized by injecting fluorine ions into the MIS-HEMT structure below the grid channel, but the electron mobility is reduced by scattering introduced by F ions, the resistance of the device is increased, meanwhile, the problems of thermal stability and the like exist, and the interface charges of a medium I and a semiconductor S of the MIS grid structure are usually very large, so that the stability and the reliability of threshold voltage are seriously influenced.
The vertical GaN device can be used for manufacturing a device with higher breakdown voltage and lower specific on-resistance than a horizontal HEMT, and the traditional enhanced vertical GaN device mainly takes a CAVET structure and an inversion layer channel MIS structure manufactured by a p-GaN base region as main parts. Compared with an inversion layer channel MIS structure, the CAVET structure utilizes two-dimensional electron gas as a grid control channel, and the total specific on-resistance of the device can be greatly reduced due to the extremely high electron mobility; as disclosed in "Ji, dong, et al," normaly OFF transistor CAVET with active Mg-doped GaN as current blocking layer, "IEEE Transactions on Electron Devices 64.3,805-808,2016," a CAVET structure formed of MIS gates, as shown in fig. 3, has similar disadvantages as MIS-HEMTs, such as: enhancement type devices are difficult to form or need to be formed by manufacturing the accessed-gate, so that the process difficulty is increased, the process consistency is poor, channels are damaged, the channel resistance is multiplied, and the like. However, the traditional CAVET structure of metal gate can only form depletion mode devices, such as "chowdour, et al," Enhancement and depletion mode AlGaN/GaN CAVET with Mg-ion-implanted GaN as current blocking layer, "IEEE Electron devices Letters 29.6,543-545,2008", which is not favorable for power electronic system applications. CAVET structure of p-GaN gate is disclosed in Nie, hui, et al, "1.5-kV and 2.2-m Ω cm 2 The structure of the Vertical GaN Transistors on Bulk-GaN substrates, "IEEE Electron Device Letters,35.9,939-941,2014", as shown in FIG. 4, suffers from similar disadvantages of p-GaN HEMTs, such as: the grid voltage swing is small, the grid current is obviously increased after the grid voltage is higher than 3V, the difficulty of a driving circuit is high, and the like.
To overcome the above problems, the applicant has filed the following application numbers: 202210146339.7, a patent document entitled enhanced MIS-GaN device, discloses a structure with a MIS gate portion; however, the introduction of this MIS structure brings high dielectric (I)/semiconductor (S) interface charges or traps, thereby affecting threshold voltage stability and reliability.
Disclosure of Invention
The invention aims to provide a junction-type gate-enhanced GaN device based on a PP heterojunction, aiming at the problems of poor threshold voltage consistency, poor stability and reliability, channel damage, high channel resistance, narrow gate voltage swing, large gate leakage, complex drive design and the like of the conventional enhanced GaN device; the invention has the advantages of large gate voltage swing, low gate leakage, small channel resistance, small total specific on resistance, high threshold voltage consistency, high reliability of electrothermal stability, simple process, low cost and the like.
In order to realize the purpose, the technical scheme adopted by the invention is as follows:
a PP heterojunction-based junction-type gate-enhanced GaN device comprises: the semiconductor device comprises a substrate 1-9, buffer layers 1-8 arranged on the substrate, channel layers 1-5 arranged on the buffer layers, barrier layers 1-4 arranged on the channel layers, source ohmic contact metal layers 1-6 arranged on the barrier layers 1-4, drain ohmic contact metal layers 1-7 and junction type grid parts, and first dielectric passivation layers 1-10 and second dielectric passivation layers 1-11; it is characterized in that the preparation method is characterized in that,
a metal source electrode 1-12 is arranged on the source electrode ohmic contact metal layer 1-6, a metal drain electrode 1-13 is arranged on the drain electrode ohmic contact metal layer 1-7, and the junction-type gate part is positioned between the source electrode ohmic contact metal layer 1-6 and the drain electrode ohmic contact metal layer 1-7 and is arranged adjacent to the source electrode ohmic contact metal layer 1-6; the junction type grid electrode part is composed of a P type wide bandgap semiconductor layer 1-1, a P type polycrystalline silicon layer 1-3 and a metal grid electrode 1-2 which are sequentially stacked from bottom to top, namely: the P-type wide bandgap semiconductor layer is arranged on the barrier layers 1-4, the P-type polycrystalline silicon layer is arranged on the P-type wide bandgap semiconductor layer, and the metal grid is arranged on the P-type polycrystalline silicon layer; the first dielectric passivation layer 1-10 is located on the upper surface of the barrier layer and partially covers two sides of the P-type polycrystalline silicon layer 1-3, and the second dielectric passivation layer 1-11 is located on the upper surface of the first dielectric passivation layer and covers the metal gate 1-2.
Further, the grid metal 1-2 extends towards two sides of the P-type polycrystalline silicon layer 1-3 to form a grid field plate, and the grid field plate is positioned on the upper surface of the first dielectric passivation layer 1-10; the source electrode metal 1-12 extends towards the side of the drain electrode metal 1-13 to form a source electrode field plate, and the source electrode field plate is positioned on the upper surface of the second dielectric passivation layer 1-11 and covers the junction type grid part; the drain metal 1-13 extends towards the source metal 1-12 side to form a drain field plate, and the drain field plate is positioned on the upper surface of the second dielectric passivation layer 1-11.
Further, the P-type polysilicon layer and the gate metal form a schottky contact or an ohmic contact.
Furthermore, the P-type polycrystalline silicon layer adopts a two-layer structure composed of a bottom lightly doped layer and a top heavily doped layer, the bottom lightly doped layer can prevent reverse-biased PP junctions from being broken down in advance or tunneling current from being overlarge, threshold voltage can be adjusted through different thickness settings, the top heavily doped layer is favorable for forming ohmic contact with gate metal, and the influence of carrier accumulation on the stability of the threshold voltage is avoided.
Furthermore, the P-type wide bandgap semiconductor layer is P-type GaN, alGaN or NiO, and the doping concentration of the P-type wide bandgap semiconductor layer is greater than 1e17cm -3 。
Further, the substrate is made of Si, siC, or sapphire; the buffer layer is made of C-doped or Fe-doped high-resistance GaN or AlGaN; the channel layer is made of unintentionally doped GaN or InGaN; the barrier layer is made of AlGaN, gaN/AlGaN, alGaN/AlN or InAlN.
A PP heterojunction-based junction-type gate-enhanced GaN device comprises: the device comprises a substrate 2-12, metal drain electrodes 2-13 arranged below the substrate, pressure-resistant layers 2-9 arranged on the substrate, two P-type electric field shielding regions 2-7 arranged on the pressure-resistant layers, an N-type current path region 2-8 arranged between the two P-type electric field shielding regions, an unintentional doping (UID) channel layer 2-5 arranged on the P-type electric field shielding regions and the current path region, barrier layers 2-4 arranged on the channel layer, junction type grid electrode parts arranged on the barrier layers, metal source electrodes 2-6, first dielectric passivation layers 2-10 and second dielectric passivation layers 2-11; it is characterized in that the preparation method is characterized in that,
the junction type grid electrode part is composed of a P type wide bandgap semiconductor layer 2-1, a P type polycrystalline silicon layer 2-3 and a metal grid electrode 2-2 which are sequentially stacked from bottom to top, namely: the P-type wide bandgap semiconductor layer is arranged on the barrier layers 2-4, the P-type polycrystalline silicon layer is arranged on the P-type wide bandgap semiconductor layer, and the metal grid is arranged on the P-type polycrystalline silicon layer; the first dielectric passivation layer 2-10 covers the upper surface of the barrier layer (the region for removing the junction type grid part) and partially covers two sides of the P-type polycrystalline silicon layer 2-3, and the second dielectric passivation layer 2-11 is positioned on the upper surface of the first dielectric passivation layer and covers the metal grid 2-2; the metal source electrode 2-6 covers the second medium passivation layer, and two sides of the metal source electrode are respectively contacted with the barrier layer 2-4, the channel layer 2-5 and the P-type electric field shielding region.
Further, the P-type polysilicon layer and the gate metal form a schottky contact or an ohmic contact.
Furthermore, the P-type polycrystalline silicon layer adopts a two-layer structure consisting of a bottom lightly doped layer and a top heavily doped layer, the bottom lightly doped P-type semiconductor layer can prevent a reverse biased PP (propene Polymer) junction from being broken down in advance or a tunneling current from being too large, the threshold voltage can be adjusted by changing the thickness, and the top heavily doped P-type semiconductor layer is favorable for forming ohmic contact and preventing carriers from being accumulated and is favorable for the stability of the threshold voltage.
Furthermore, the P-type wide bandgap semiconductor layer is P-type GaN, alGaN or NiO, and the doping concentration of the P-type wide bandgap semiconductor layer is greater than 1e17cm -3 。
Further, the substrate is made of N-type heavily doped GaN; the pressure-resistant layer is made of N-type lightly doped GaN, and the concentration of the pressure-resistant layer is between 1e14 and 1e 17; the current path region is made of N-type GaN and has a concentration higher than that of the voltage-resistant layer; the barrier layer is made of AlGaN, gaN/AlGaN, alGaN/AlN or InAlN; the P-type electric field shielding layer and the channel layer are made of GaN.
The invention has the effective effects that:
the invention provides a junction-type gate-enhanced GaN device based on a PP heterojunction, which comprises a transverse device and a longitudinal device, wherein a P-type wide bandgap semiconductor layer is used for exhausting high-concentration two-dimensional electron gas below the P-type wide bandgap semiconductor layer to obtain an enhanced device; meanwhile, a P-type polycrystalline silicon layer is arranged on the P-type wide bandgap semiconductor layer, a junction gate is formed by the P-type wide bandgap semiconductor layer, the P-type polycrystalline silicon layer and a grid metal together, because the PP heterojunction almost has no electron current, and the hole barrier of the PP heterojunction formed by the P-type wide bandgap semiconductor layer and the P-type polycrystalline silicon layer is very high, the hole in the P-type polycrystalline silicon can enter the P-type wide bandgap semiconductor only after crossing the very high barrier, when the P-type polycrystalline silicon opens a channel by applying positive voltage to the grid, the hole on the side of the P-type polycrystalline silicon almost cannot cross the hole barrier to form hole current, so that the grid current is extremely low, the grid voltage swing is extremely high, the drive loss can be reduced, and the difficulty and the complexity of the design of a drive circuit can be reduced; moreover, based on the novel junction type grid, the influence of interface charges or traps of the dielectric layer (I) and the semiconductor layer (S) in the MIS structure on the reliability and stability of the threshold voltage is avoided; in addition, the problem of serious electrothermal stability caused by overlarge grid leakage due to the use of an inverse bias P-type Schottky junction in the traditional P-GaN HEMT can be solved, the grid leakage current is recovered and no charge is stored after the electrothermal stress disappears in the PP heterojunction, so that the threshold voltage of a device and the reliability and stability of grid leakage are improved; in conclusion, the invention realizes the enhancement type device with extremely low grid driving current and extremely high grid voltage swing without adopting a received-gate structure and fluorine ion injection by introducing a novel junction type grid structure, and has the advantages of low specific on resistance, simple process, high consistency, low cost and high stability.
Drawings
Fig. 1 is a schematic diagram of a cell of a conventional p-GaN gate HEMT device.
FIG. 2 is a schematic diagram of a conventional received-gate HEMT device cell.
FIG. 3 is a schematic diagram of a conventional MIS grid CAVET structure cell.
FIG. 4 is a schematic diagram of a conventional p-GaN gate CAVET structure unit cell.
FIG. 5 is a schematic diagram of an enhanced lateral GaN device cell in example 1 of the invention;
the semiconductor structure comprises a substrate, a P-type wide bandgap semiconductor layer 1-1, a metal gate 1-2, a P-type polycrystalline silicon layer 1-3, a barrier layer 1-4, a channel layer 1-5, a source ohmic contact metal layer 1-6, a drain ohmic contact metal layer 1-7, a buffer layer 1-8, a substrate 1-9, a first dielectric passivation layer 1-10, a second dielectric passivation layer 1-11, a metal source 1-12 and a metal drain 1-13.
Fig. 6 is a graph showing transfer characteristics and gate current waveforms of the enhancement mode lateral GaN device in example 1 of the present invention.
Fig. 7 is a schematic energy band diagram of a junction gate portion in an enhancement mode lateral GaN device in embodiment 1 of the present invention.
FIG. 8 is a schematic view of an enhancement mode vertical GaN device cell in embodiment 2 of the invention;
the device comprises a substrate, a P-type wide bandgap semiconductor layer 2-1, a metal gate 2-2, a P-type polycrystalline silicon layer 2-3, a barrier layer 2-4, a UID channel layer 2-5, a metal source electrode 2-6, a P-type electric field shielding region 2-7, an N-type current circuit region 2-8, a voltage-withstanding layer 2-9, a first dielectric passivation layer 2-10, a second dielectric passivation layer 2-11, a substrate 2-12 and a metal drain electrode 2-13.
Detailed Description
In order to make the objects, technical solutions and technical effects of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some, but not all embodiments of the present invention.
Example 1
The present embodiment provides a junction-type gate-enhanced lateral GaN device, wherein a cell structure of the junction-type gate-enhanced lateral GaN device is shown in fig. 5, and specifically includes:
the semiconductor device comprises a substrate 1-9, buffer layers 1-8 arranged on the substrate, channel layers 1-5 arranged on the buffer layers, barrier layers 1-4 arranged on the channel layers, source ohmic contact metal layers 1-6 arranged on the barrier layers 1-4, drain ohmic contact metal layers 1-7 and junction type grid parts, and first dielectric passivation layers 1-10 and second dielectric passivation layers 1-11;
a metal source electrode 1-12 is arranged on the source electrode ohmic contact metal layer 1-6, a metal drain electrode 1-13 is arranged on the drain electrode ohmic contact metal layer 1-7, and the junction-type gate part is positioned between the source electrode ohmic contact metal layer 1-6 and the drain electrode ohmic contact metal layer 1-7 and is arranged adjacent to the source electrode ohmic contact metal layer 1-6; the junction type grid electrode part is composed of a P type wide bandgap semiconductor layer 1-1, a P type polycrystalline silicon layer 1-3 and a metal grid electrode 1-2 which are sequentially stacked from bottom to top, namely: the P-type wide bandgap semiconductor layer is arranged on the barrier layers 1-4, the P-type polycrystalline silicon layer is arranged on the P-type wide bandgap semiconductor layer, and the metal grid is arranged on the P-type polycrystalline silicon layer; the first dielectric passivation layer 1-10 is positioned on the upper surface of the barrier layer (the area of the source ohmic contact layer 1-6, the drain ohmic contact layer 1-7 and the junction type grid part are removed) and partially covers two sides of the P-type polycrystalline silicon layer 1-3, and the second dielectric passivation layer 1-11 is positioned on the upper surface of the first passivation layer and covers the metal grid 1-2.
Further, the grid metal 1-2 extends towards two sides of the P-type polycrystalline silicon layer 1-3 to form a grid field plate, and the grid field plate is positioned on the upper surface of the first dielectric passivation layer 1-10; the source electrode metal 1-12 extends towards the side of the drain electrode metal 1-13 to form a source electrode field plate, and the source electrode field plate is positioned on the upper surface of the second dielectric passivation layer 1-11 and covers the junction type grid part; the drain metal 1-13 extends towards the source metal 1-12 side to form a drain field plate, and the drain field plate is positioned on the upper surface of the second dielectric passivation layer 1-11.
Furthermore, in this embodiment, the substrate is P-type Si, the buffer layer is C-doped GaN, the channel layer is 400nm UID-GaN, the barrier layer is AlGaN with a molar composition of 0.2 and a thickness of 10nm, and the P-type wide bandgap semiconductor layer has an effective hole concentration of about 1 × 10 18 cm -3 The P-type polycrystalline silicon layer has a thickness of 50nm and a doping concentration of 5e17cm -3 The gate source interval and the gate drain interval are respectively 1.5um and 13.5um, the length of the gate electrode is 2um, the metal gate electrode and the P-type polycrystalline silicon layer are in Schottky contact, and the first passivation layer is 100nm of SiN and the second passivation layer is 50nm of SiO2.
Based on the above parameters, the transfer characteristic curve and the gate current waveform of the junction-type gate-enhanced lateral GaN device in this embodiment are shown in fig. 6, and it can be seen from the figure that, firstly, the device realizes the enhancement characteristic, and the threshold voltage is about 1.5V. More importantly, the device V GS The grid current density is only nA/mm magnitude when the voltage is 10V, and is compared with the conventional p-GaN HEMT (Jiang, huaxing, et al. "High-voltage p-GaN HEMTs with off-state blocking capability) after gate breakdown."IEEE Electron Device Letters,vol.40,no.4,2019,pp.530-533.)V GS The mA/mm magnitude is reduced by 10 when the voltage is not less than 6V 5 More than the order of magnitude. Because the grid current of the traditional p-GaN HEMT is too large, the grid voltage of the traditional p-GaN HEMT is generally limited below 6V, and the invention obviously can still maintain extremely low grid current when the grid voltage is increased to 10V or above. Therefore, the design difficulty of the driving circuit is reduced, the grid voltage overvoltage protection requirement is reduced, and the power consumption of the driving circuit is reduced.
In terms of working principle: as shown in fig. 7, which is a schematic energy band diagram of the junction-type gate portion in this embodiment, it can be seen from the figure that although the doping is P-type, since a very high hole barrier is formed at the P-type polysilicon/P-GaN heterojunction interface, holes in the P-type polysilicon are prevented from entering the P-GaN when the gate is forward biased, so that the current formed when the gate metal on the P-type polysilicon applies a positive voltage to open the gate channel is extremely low, the gate voltage swing is extremely high, and the above simulation test results also prove the principle. Meanwhile, when the P-GaN of the P type wide bandgap semiconductor layer 1-1 is changed into P-AlGaN or P-NiO, the device has similar effect. The first dielectric passivation layer is used for passivating the surface of a device, a trap between the first dielectric passivation layer and the barrier layer provides a two-dimensional electron gas source, and the first dielectric passivation layer and the barrier layer are used for forming a grid field plate with grid metal, so that the breakdown voltage is improved, and the current collapse is inhibited; the second dielectric passivation layer is used for passivating the surface of the device and forming a source-drain field plate with the source-drain metal, so that the breakdown voltage is improved, and the current collapse is inhibited.
In addition, it should be noted that: in all the above embodiments, the above similar effects are obtained when the substrate is replaced by SiC or sapphire, the buffer layer is replaced by high-resistance AlGaN, the channel layer is replaced by InGaN, and the barrier layer is replaced by GaN/AlGaN, alGaN/AlN or InAlN.
Example 2
The present embodiment provides a junction-type gate-enhanced vertical GaN device, whose structure is shown in fig. 8, which specifically includes:
the device comprises a substrate 2-12, metal drain electrodes 2-13 arranged below the substrate, pressure-resistant layers 2-9 arranged on the substrate, two P-type electric field shielding regions 2-7 arranged on the pressure-resistant layers, an N-type current path region 2-8 arranged between the two P-type electric field shielding regions, an unintentional doping (UID) channel layer 2-5 arranged on the P-type electric field shielding regions and the current path region, barrier layers 2-4 arranged on the channel layer, junction type grid electrode parts arranged on the barrier layers, metal source electrodes 2-6, first dielectric passivation layers 2-10 and second dielectric passivation layers 2-11;
the junction type grid electrode part is composed of a P type wide bandgap semiconductor layer 2-1, a P type polycrystalline silicon layer 2-3 and a metal grid electrode 2-2 which are sequentially stacked from bottom to top, namely: the P-type wide bandgap semiconductor layer is arranged on the barrier layers 2-4, the P-type polycrystalline silicon layer is arranged on the P-type wide bandgap semiconductor layer, and the metal grid is arranged on the P-type polycrystalline silicon layer; the first passivation layer 2-10 covers the upper surface of the barrier layer (the region for removing the junction type grid part) and partially covers two sides of the P-type polycrystalline silicon layer 2-3, and the second dielectric passivation layer 2-11 is positioned on the upper surface of the first dielectric passivation layer and covers the metal grid 2-2; the metal source electrode 2-6 covers the second medium passivation layer, and two sides of the metal source electrode are respectively contacted with the barrier layer 2-4, the channel layer 2-5 and the P-type electric field shielding region.
Furthermore, in this embodiment, the substrate is made of heavily doped N-type GaN, and the voltage-withstanding layer is made of lightly doped N-type GaN, usually with a concentration of 1e 14-1e17 cm -3 The current path region is made of N-type GaN and has a concentration higher than that of the voltage-resistant layer; the barrier layer is made of AlGaN, gaN/AlGaN, alGaN/AlN or InAlN, and the Al molar group of AlGaN or the In molar component of InAlN is adaptively designed according to the application requirement; the P-type wide bandgap semiconductor layer is P-type GaN, alGaN or NiO, and the concentration is more than 1e17cm -3 The molar composition of Al of the P-type AlGaN is generally between 0 and 0.35 according to different requirements, and the thickness of the P-type wide bandgap semiconductor layer is adaptively designed according to application requirements.
In terms of working principle: the patterned gate portion in this embodiment is the same as embodiment 1, the gate control principle is similar to embodiment 1, and the transfer characteristic curve, the gate current, and the band diagram are also similar to embodiment 1, and the same characteristics and advantageous effects are obtained.
Where mentioned above are merely embodiments of the invention, any feature disclosed in this specification may, unless stated otherwise, be replaced by alternative features serving equivalent or similar purposes; all of the disclosed features, or all of the method or process steps, may be combined in any combination, except mutually exclusive features and/or steps.
Claims (6)
1. A PP heterojunction-based junction-type gate-enhanced GaN device comprises: the semiconductor device comprises a substrate (1-9), buffer layers (1-8) arranged on the substrate, unintended doped channel layers (1-5) arranged on the buffer layers, barrier layers (1-4) arranged on the channel layers, source ohmic contact metal layers (1-6) and drain ohmic contact metal layers (1-7) and junction type grid parts arranged on the barrier layers, and first dielectric passivation layers (1-10) and second dielectric passivation layers (1-11); it is characterized in that the preparation method is characterized in that,
a metal source electrode is arranged on the source electrode ohmic contact metal layer, a metal drain electrode is arranged on the drain electrode ohmic contact metal layer, and the junction-type gate part is positioned between the source electrode ohmic contact metal layer and the drain electrode ohmic contact metal layer and is arranged adjacent to the source electrode ohmic contact metal layer; the junction type grid electrode part is formed by sequentially stacking a P type wide bandgap semiconductor layer (1-1), a P type polycrystalline silicon layer (1-3) and a metal grid electrode (1-2) from bottom to top; the first dielectric passivation layer is located on the upper surface of the barrier layer and partially covers two sides of the P-type polycrystalline silicon layer, and the second dielectric passivation layer is located on the upper surface of the first dielectric passivation layer and covers the metal gate.
2. The PP-heterojunction-based junction-type gate-enhanced GaN device of claim 1, wherein the gate metal extends towards two sides of the P-type polysilicon layer to form a gate field plate, and the gate field plate is positioned on the upper surface of the first dielectric passivation layer; the source electrode metal extends towards the side of the drain electrode metal to form a source electrode field plate, and the source electrode field plate is positioned on the upper surface of the second medium passivation layer and covers the junction type grid part; and the drain metal extends to the source metal side to form a drain field plate, and the drain field plate is positioned on the upper surface of the second dielectric passivation layer.
3. A PP heterojunction-based junction-type gate-enhanced GaN device comprises: the device comprises a substrate (2-12), metal drain electrodes (2-13) arranged below the substrate, pressure-resistant layers (2-9) arranged on the substrate, two P-type electric field shielding regions (2-7) arranged on the pressure-resistant layers, an N-type current path region (2-8) arranged between the two P-type electric field shielding regions, unintended doped channel layers (2-5) arranged on the P-type electric field shielding regions and the current path region, barrier layers (2-4) arranged on the channel layers, junction type grid electrode parts arranged on the barrier layers, metal source electrodes (2-6), first dielectric passivation layers (2-10) and second dielectric passivation layers (2-11); it is characterized in that the preparation method is characterized in that,
the junction type grid electrode part is formed by sequentially stacking a P type wide bandgap semiconductor layer (2-1), a P type polycrystalline silicon layer (2-3) and a metal grid electrode (2-2) from bottom to top; the first dielectric passivation layer covers the upper surface of the barrier layer and partially covers two sides of the P-type polycrystalline silicon layer, and the second dielectric passivation layer is positioned on the upper surface of the first dielectric passivation layer and covers the metal gate; the metal source electrode covers the second medium passivation layer, and two sides of the metal source electrode are respectively contacted with the barrier layer, the channel layer and the P-type electric field shielding region.
4. The PP-heterojunction-based junction-gated enhancement GaN device of claim 1 or 3, wherein the P-type polysilicon layer forms a Schottky contact or an ohmic contact with the gate metal.
5. The PP-heterojunction-based junction-gated enhancement GaN device of claim 1 or 3, wherein the P-type polysilicon layer has a two-layer structure consisting of a bottom lightly doped layer and a top heavily doped layer.
6. The PP-heterojunction-based junction-gate-enhanced GaN device of claim 1 or 3, wherein the P-type wide bandgap semiconductor layer is P-type GaN, alGaN or NiO, and has a doping concentration of more than 1e17cm -3 。
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