CN117690963A - GaN-HEMT device and preparation method thereof - Google Patents
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Abstract
The application provides a GaN-HEMT device and a preparation method thereof, wherein the GaN-HEMT device comprises a channel layer, a barrier layer, a first passivation layer and a grid electrode; the barrier layer is arranged on the channel layer and is used for forming two-dimensional electron gas at the interface between the channel layer and the barrier layer; the first passivation layer is arranged on one side of the barrier layer, which is away from the channel layer, and is a P-GaN layer; the grid electrode is arranged on one side of the first passivation layer, which is away from the barrier layer, and forms ohmic contact with the first passivation layer; by setting the P-GaN layer as the first passivation layer, the first passivation layer can shield surface traps so as to improve the current collapse resistance of the device.
Description
Technical Field
The application belongs to the technical field of HEMT devices, and particularly relates to a GaN-HEMT device and a preparation method thereof.
Background
The GaN-HEMT (High Electron Mobility Transistors, gallium nitride high electron mobility transistor) device is an electronic device based on gallium nitride (GaN) materials, and has the advantages of high speed, high efficiency, high power density and the like. In a GaN-HEMT device, the GaN material has high electron mobility and saturated electron velocity, enabling the device to achieve high-speed switching and high-efficiency conversion. GaN-HEMT devices can be classified into Depletion-Mode (D-Mode) and Enhancement-Mode (E-Mode).
In the related art, an enhanced GaN adds a P-type gallium nitride epitaxial layer on a gate to realize an E-Mode HEMT device. The GaN HEMT device is easy to generate current collapse during switching.
Therefore, how to improve the current collapse resistance of the GaN-HEMT device is a problem that the skilled person needs to solve.
Disclosure of Invention
The invention aims to provide a GaN-HEMT device and a preparation method thereof, and aims to solve the problem that the GaN-HEMT device in the traditional technology is easy to collapse in current.
A first aspect of an embodiment of the present application proposes a GaN-HEMT device, including:
a channel layer;
a barrier layer disposed on the channel layer, the barrier layer being configured to form a two-dimensional electron gas within the channel layer;
the first passivation layer is arranged on one side, away from the channel layer, of the barrier layer, and is a P-GaN layer;
and the grid electrode is arranged on one side of the first passivation layer, which is away from the barrier layer, and forms ohmic contact with the first passivation layer.
In some embodiments of the present application, the GaN-HEMT device further includes:
the buffer layer is arranged on one side of the channel layer, which is away from the barrier layer;
the second passivation layer is arranged on one side, away from the channel layer, of the buffer layer, and the second passivation layer is a P-GaN layer.
In some embodiments of the present application, the GaN-HEMT device further includes a source electrode, where the source electrode is disposed at one end of the channel layer and is electrically connected to the channel layer; one end of the source electrode extends to the second passivation layer and is connected with the second passivation layer, and the other end of the source electrode extends to the upper portion of the grid electrode.
In some embodiments of the present application, the GaN-HEMT device further includes a source field plate, where the source field plate is connected to an end of the source near the gate; wherein the source field plate extends along a direction parallel to the gate and covers the gate.
In some embodiments of the present application, the GaN-HEMT device further includes a drain electrode, where the drain electrode is disposed at an end of the channel layer facing away from the source electrode and is electrically connected to the channel layer; one end of the drain electrode is connected to the channel layer, and the other end extends to the upper portion of the grid electrode.
In some embodiments of the present application, the GaN-HEMT device further includes a drain field plate, where the drain field plate is connected to an end of the drain near the gate; wherein the drain field plate extends in a direction approaching the source field plate.
In some embodiments of the present application, an insulating layer is disposed between the source field plate and the drain field plate.
In some embodiments of the present application, the GaN-HEMT device further includes a current blocking layer, and the current blocking layer is enclosed around the channel layer.
In some embodiments of the present application, the channel layer is a GaN layer;
and/or, the barrier layer is an AlGaN layer;
and/or, the buffer layer is a GaN layer.
In a second aspect, the present application further provides a method for manufacturing a GaN-HEMT device, which is used for manufacturing a GaN-HEMT device as described above.
Compared with the prior art, the embodiment of the invention has the beneficial effects that: the GaN-HEMT device comprises a channel layer, a barrier layer, a first passivation layer and a grid electrode; the barrier layer is arranged on the channel layer and is used for forming two-dimensional electron gas at the interface between the channel layer and the barrier layer; the first passivation layer is arranged on one side of the barrier layer, which is away from the channel layer, and is a P-GaN layer; the grid electrode is arranged on one side of the first passivation layer, which is away from the barrier layer, and forms ohmic contact with the first passivation layer; according to the P-GaN semiconductor device, the P-GaN layer is arranged as the first passivation layer, the grid electrode is in ohmic contact with the first passivation layer, a path for free hole outflow and injection can be provided for the first passivation layer, and the first passivation layer can shield surface traps to improve the current collapse resistance of the device.
Drawings
Fig. 1 is a schematic structural diagram of a GaN-HEMT device according to an embodiment of the present application.
Specific element symbol description: 100-substrate, 200-AIN nucleation layer, 300-second passivation layer, 400-buffer layer, 500-channel layer, 600-drain, 610-drain field plate, 620-insulating layer, 700-source, 710-source field plate, 800-barrier layer, 900-first passivation layer, 910-current blocking layer, 1000-gate, 1100-protection layer.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved by the present application more clear, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
It will be understood that when an element is referred to as being "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It should be appreciated that the terms "length," "width," "upper," "lower," "inner," "outer," and the like indicate an orientation or positional relationship based on that shown in the drawings, merely to facilitate description of the present application and simplify the description, and do not indicate or imply that the apparatus or element in question must have a particular orientation, be configured and operated in a particular orientation, and therefore should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
It should be noted that the GaN-HEMT device is an electronic device based on gallium nitride material, and has advantages of high speed, high efficiency, high power density, and the like. In a GaN-HEMT device, the GaN material has high electron mobility and saturated electron velocity, enabling the device to achieve high-speed switching and high-efficiency conversion. The GaN-HEMT device comprises depletion type GaN and enhancement type GaN.
In the related art, an enhanced GaN adds a P-type gallium nitride epitaxial layer on a gate to realize an E-Mode HEMT device.
Therefore, the related GaN-HEMT device structure and the preparation method thereof are improved.
Referring to fig. 1 in combination, fig. 1 shows a schematic structural diagram of a GaN-HEMT device according to the present embodiment. The GaN-HEMT device of the embodiment comprises a channel layer 500, a barrier layer 800, a first passivation layer 900 and a gate 1000; the barrier layer 800 is disposed on the channel layer 500, the barrier layer 800 being for forming a two-dimensional electron gas at an interface between the channel layer 500 and the barrier layer 800; the first passivation layer 900 is disposed on a side of the barrier layer 800 facing away from the channel layer 500, the first passivation layer 900 being a P-GaN layer; the gate electrode 1000 is disposed on a side of the first passivation layer 900 facing away from the barrier layer 800, and the gate electrode 1000 forms an ohmic contact with the first passivation layer 900.
It should be noted that the channel layer 500 is a two-dimensional electron gas transport channel and is generally located above the buffer layer 400. The channel layer 500 is generally made of an intrinsic GaN material, mainly because the intrinsic GaN material contains no impurity, and has a relatively small scattering effect on the two-dimensional electron gas, thereby improving the mobility of the two-dimensional electron gas. In some embodiments, the thickness of the channel layer 500 is several hundred nanometers, and too thin may make it difficult for the buffer layer 400 to deplete the two-dimensional electron gas in the channel, and too thick may provide a large leakage path under high fields due to the n-type intrinsic GaN, thereby affecting the breakdown characteristics of the device. The Two-dimensional electron gas is a Two-dimensional electron gas system (Two-Dimensional Electron Gas,2 DEG). It is an electronic system in which electrons are confined in one direction and are free to move in the other two directions.
It should also be explained that in a semiconductor device, the barrier layer 800 is a very important structural layer that can control and regulate the flow of current and signals and improve the stability and reliability of the device.
Current gate and P-GaN layers are typically designed to be schottky contacts. However, the present application forms ohmic contact between the first passivation layer 900 and the gate electrode 1000 by providing the P-GaN layer as the first passivation layer 900. This design enables the gate 1000 to provide a path for free hole flow and injection for the first passivation layer 900.
In the off state, the surface trap can capture or release charges, and when the device is turned on, if electrons captured by the surface trap cannot be released in time, the output current can be influenced.
At 0 bias, the two-dimensional electron gas under the first passivation layer 900 has been depleted, and at the off-state drain voltage, the thin first passivation layer 900 may form a depletion region that extends from the drain to the gate 1000 (as opposed to conventional GaN HEMT devices).
In addition, the GaN HEMT device of the present embodiment is not affected by surface traps, because the first passivation layer 900 connected to the gate 1000 can actively supply/release charges through the gate 1000, which means that holes can be rapidly accumulated and released in the first passivation layer 900 during the turn-on and turn-off processes to shield the effect caused by the surface traps trapping charges.
In some embodiments, the thickness of the first passivation layer 900 is 20-100nm. If the thickness of the first passivation layer 900 is too thick, the two-dimensional electron gas of the channel layer 500 may not be exhausted, and an E-Mode device may not be formed. Illustratively, the first passivation layer 900 is partially located at the bottom of the gate electrode 1000, which has a thickness of 100nm. Another portion of the first passivation layer 900 extends beyond the bottom of the gate electrode 1000, and has a thickness of 20-50nm.
In particular embodiments, the thickness of the first passivation layer 900 may be controlled by the step of ion implantation.
In some embodiments, the thickness of the channel layer 500 is 400nm. The thickness of the barrier layer 800 is 15nm.
In some embodiments of the present application, please continue to refer to fig. 1, the GaN-HEMT device of the present embodiment further includes a buffer layer 400 and a second passivation layer 300; the buffer layer 400 is disposed on a side of the channel layer 500 facing away from the barrier layer 800; the second passivation layer 300 is disposed on a side of the buffer layer 400 facing away from the channel layer 500, and the second passivation layer 300 is a P-GaN layer.
It should be noted that the buffer layer 400 of the vertical GaN HEMT device can be used as a material layer for bearing high voltage. And the buffer layer 400 can reduce the electric field intensity inside the transistor, thereby improving the reliability and performance of the transistor. The buffer layer 400 may also act as an isolation layer to prevent interdiffusion of the GaN material with the Si substrate 100.
In some embodiments, the buffer layer has a thickness of 1.5-1.9 μm. The thickness of the second passivation layer is 0.1-0.5 μm.
In some embodiments of the present application, please continue to refer to fig. 1, the GaN-HEMT device of the present embodiment further includes a source 700, where the source 700 is disposed at one end of the channel layer 500 and is electrically connected to the channel layer 500; one end of the source electrode 700 extends to the second passivation layer 300 and is connected to the second passivation layer 300, and the other end of the source electrode 700 extends above the gate electrode 1000.
Specifically, the GaN-HEMT device further comprises a source electrode field plate, wherein the source electrode field plate is connected with one end of the source electrode, which is close to the grid electrode; the source electrode field plate extends along the direction parallel to the grid electrode and covers the grid electrode.
It should be explained that, in the GaN-HEMT, the source electrode 700 and the drain electrode 600 can be connected to the GaN layer through a Field Plate. The source field plate 710 (S-FP) and the drain field plate 610 (D-FP) may provide a uniform channel electric field, improving withstand voltage.
The second passivation layer 300 and the source electrode 700 are connected together by the source field plate 710 in this embodiment, so that a dynamic charge storage layer can be formed in the second passivation layer 300 to facilitate improvement of the GaN-HEMT device. In particular, a P-N junction can be formed between the dynamic charge storage layer and the channel layer 500. The P-N junction diode thus antiparallel is in a reverse biased state when a voltage bias is applied between the device drain 600 and source 700. During turn-off, a higher drain voltage bias results in a higher potential difference between the P-doped dynamic charge storage layer and the drain 600, which increases the reverse bias voltage across the anti-parallel P-N junction diode and enhances depletion of free holes in the P-doped dynamic charge storage layer. As the energy band of the P-doped dynamic charge storage layer on the drain 600 side decreases, a large number of holes are depleted. Holes flow from the P-doped dynamic charge storage layer to the source, leaving ionized acceptors to be considered as net negative charges stored in the P-doped dynamic charge storage layer. The net negative charge left behind reduces the charge density of the two-dimensional electron gas, which is also negatively charged, and the two-dimensional electron gas is accelerated to be depleted, thereby reducing the turn-off time of the device and thus the turn-off loss.
In some embodiments of the present application, please continue to refer to fig. 1, the GaN-HEMT device of the present embodiment further includes a drain electrode 600, where the drain electrode 600 is disposed at an end of the channel layer 500 facing away from the source electrode 700 and is electrically connected to the channel layer 500; one end of the drain electrode 600 is connected to the channel layer 500, and the other end extends above the gate electrode 1000.
Specifically, the GaN-HEMT device further comprises a drain electrode field plate, wherein the drain electrode field plate is connected with one end of the drain electrode, which is close to the grid electrode; wherein the drain field plate extends in a direction approaching the source field plate.
In some embodiments of the present application, referring to fig. 1, an insulating layer 620 is disposed between the source field plate 710 and the drain field plate 610 in this embodiment.
In some embodiments of the present application, referring to fig. 1, the GaN-HEMT device of the present embodiment further includes a current blocking layer 910 (HR-GaN, high-resistance gallium nitride), where the current blocking layer 910 is surrounded around the channel layer 500. The role of the current blocking layer 910 in the GaN-HEMT device is to improve the withstand voltage and reliability of the device.
In some embodiments, the gate 1000 is covered with a protective layer 1100. The source field plate 700 and the drain field plate 600 are covered on the protective layer 1100.
Illustratively, the protective layer 1100 may be a layer of SiNx, which is a silicon nitride material, where x represents the atomic ratio of nitrogen to silicon. SiNx is generally used as the insulating layer 620 and the protective layer 1100 in electronic devices because it has advantages of high hardness, low dielectric constant, high chemical stability, high thermal stability, and the like. In the GaN-HEMT device, siNx can be used as a passivation layer to protect the surface of the device from oxidation and corrosion, and stability and reliability of the device are improved.
In some embodiments of the present application, the channel layer 500 is a GaN layer; and/or the barrier layer 800 is an AlGaN layer; and/or the buffer layer 400 is a GaN layer.
In some embodiments, barrier layer 800 is Al 0.3 Ga 0.7 And N layers.
In some embodiments, the GaN-HEMT device further comprises a substrate 100, the AIN nucleation layer 200 is disposed on the substrate 100, and the second passivation layer 300 is disposed on the AIN nucleation layer 200. Illustratively, the substrate 100 is a Si substrate 100.
Further, in order to better implement the GaN-HEMT device in any embodiment, on the basis of the GaN-HEMT device structure, the present application further provides a preparation method of the GaN-HEMT device, which is used for preparing the GaN-HEMT device in any embodiment.
Specifically, the preparation method of the GaN-HEMT device comprises the following steps:
s100: growing a nucleation layer AlN on a substrate; specifically, the thickness of the nucleation layer AlN is 10nm;
s200: growing a first buffer layer GaN on the nucleation layer AlN; specifically, the thickness of the first buffer layer GaN is 1 μm;
s300: growing a second passivation layer P-GaN on the first buffer layer GaN;
s400: growing a second buffer layer GaN on the second passivation layer P-GaN;
s500: growing a channel layer GaN on the second buffer layer GaN;
s600: growth of barrier layer Al on channel layer GaN x Ga y N; specifically, x∈ [ 0.2,0.3 ];
s700: growing a first passivation layer P-GaN on the barrier layer;
s800: ion implantation is carried out on the first passivation layer P-GaN to form a current blocking layer HR-GaN; specifically, the ion implantation is performed twice, the first time around the first passivation layer P-GaN, and the second time on the first passivation layer P-GaN, and toward the first passivation layer P-GaN.
S900: depositing a protective layer SiNx on the first passivation layer P-GaN;
s1000: etching part of the protective layer SiNx to prepare a grid electrode, and connecting the grid electrode with the first passivation layer P-GaN;
s1100: depositing a protective layer SiNx on the grid electrode;
s1200: preparing a source electrode field plate, a drain electrode field plate, a source electrode and a drain electrode;
s1300: an insulating layer SiO2 is deposited between the source field plate and the drain field plate.
It should be noted that the design of the present application is illustrated by using the P-GaN HEMT device structure as an example, but the present application is also applicable to other E-Mode GaN HEMT device structures, for example, the E-Mode GaN HEMT device with trench gate design, and other D-Mode GaN HEMT device structures are also applicable for supporting the protection scope of the claims.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
While the basic concepts have been described above, it will be apparent to those skilled in the art that the foregoing detailed disclosure is by way of example only and is not intended to be limiting. Although not explicitly described herein, various modifications, improvements, and adaptations of the present application may occur to one skilled in the art. Such modifications, improvements, and modifications are intended to be suggested within this application, and are therefore within the spirit and scope of the exemplary embodiments of this application.
Meanwhile, the present application uses specific words to describe embodiments of the present application. Reference to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic is associated with at least one embodiment of the present application. Thus, it should be emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various positions in this specification are not necessarily referring to the same embodiment. Furthermore, certain features, structures, or characteristics of one or more embodiments of the present application may be combined as suitable.
Likewise, it should be noted that in order to simplify the presentation disclosed herein and thereby aid in understanding one or more inventive embodiments, various features are sometimes grouped together in a single embodiment, figure, or description thereof. This method of disclosure, however, is not intended to imply that more features than are presented in the claims are required for the subject application. Indeed, less than all of the features of a single embodiment disclosed above.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (10)
1. A GaN-HEMT device, the GaN-HEMT device comprising:
a channel layer;
a barrier layer disposed on the channel layer, the barrier layer being configured to form a two-dimensional electron gas at an interface between the channel layer and the barrier layer;
the first passivation layer is arranged on one side, away from the channel layer, of the barrier layer, and is a P-GaN layer;
and the grid electrode is arranged on one side of the first passivation layer, which is away from the barrier layer, and forms ohmic contact with the first passivation layer.
2. The GaN-HEMT device of claim 1, further comprising:
the buffer layer is arranged on one side of the channel layer, which is away from the barrier layer;
the second passivation layer is arranged on one side, away from the channel layer, of the buffer layer, and the second passivation layer is a P-GaN layer.
3. The GaN-HEMT device of claim 2, further comprising a source electrode disposed at one end of the channel layer and electrically connected to the channel layer; one end of the source electrode extends to the second passivation layer and is connected with the second passivation layer, and the other end of the source electrode extends to the upper portion of the grid electrode.
4. The GaN-HEMT device of claim 3, further comprising a source field plate connecting an end of the source adjacent to the gate; wherein the source field plate extends along a direction parallel to the gate and covers the gate.
5. The GaN-HEMT device of claim 3, further comprising a drain electrode disposed at an end of the channel layer facing away from the source electrode and electrically connected to the channel layer; one end of the drain electrode is connected to the channel layer, and the other end extends to the upper portion of the grid electrode.
6. The GaN-HEMT device of claim 5, further comprising a drain field plate connecting an end of the drain adjacent the gate; wherein the drain field plate extends in a direction approaching the source field plate.
7. The GaN-HEMT device of claim 6, wherein an insulating layer is disposed between the source field plate and the drain field plate.
8. The GaN-HEMT device of claim 1, further comprising a current blocking layer surrounding the channel layer.
9. The GaN-HEMT device of any one of claims 2 to 7, wherein the channel layer is a GaN layer;
and/or, the barrier layer is an AlGaN layer;
and/or, the buffer layer is a GaN layer.
10. A method of manufacturing a GaN-HEMT device, characterized by being used to manufacture a GaN-HEMT device as claimed in any one of claims 1 to 9.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013062442A (en) * | 2011-09-14 | 2013-04-04 | Sumitomo Electric Ind Ltd | Nitride semiconductor electronic device and nitride semiconductor electronic device manufacturing method |
| CN108054208A (en) * | 2017-12-19 | 2018-05-18 | 中国电子产品可靠性与环境试验研究所 | Lateral type gallium nitride-based field effect transistor and preparation method thereof |
| CN115172451A (en) * | 2022-06-20 | 2022-10-11 | 电子科技大学 | Junction type grid enhanced GaN device based on PP heterojunction |
| CN115332334A (en) * | 2022-08-26 | 2022-11-11 | 电子科技大学 | GaN HEMT longitudinal device with integrated diode having reverse freewheeling capability |
| CN115548106A (en) * | 2022-10-12 | 2022-12-30 | 电子科技大学 | Enhancement mode GaN device with P type grid |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013062442A (en) * | 2011-09-14 | 2013-04-04 | Sumitomo Electric Ind Ltd | Nitride semiconductor electronic device and nitride semiconductor electronic device manufacturing method |
| CN108054208A (en) * | 2017-12-19 | 2018-05-18 | 中国电子产品可靠性与环境试验研究所 | Lateral type gallium nitride-based field effect transistor and preparation method thereof |
| CN115172451A (en) * | 2022-06-20 | 2022-10-11 | 电子科技大学 | Junction type grid enhanced GaN device based on PP heterojunction |
| CN115332334A (en) * | 2022-08-26 | 2022-11-11 | 电子科技大学 | GaN HEMT longitudinal device with integrated diode having reverse freewheeling capability |
| CN115548106A (en) * | 2022-10-12 | 2022-12-30 | 电子科技大学 | Enhancement mode GaN device with P type grid |
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