CN114664943A - Planar high electron mobility transistor - Google Patents

Planar high electron mobility transistor Download PDF

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Publication number
CN114664943A
CN114664943A CN202011536169.0A CN202011536169A CN114664943A CN 114664943 A CN114664943 A CN 114664943A CN 202011536169 A CN202011536169 A CN 202011536169A CN 114664943 A CN114664943 A CN 114664943A
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semiconductor epitaxial
epitaxial layer
layer
planar
gate
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周翔
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Nantong Shangyangtong Integrated Circuit Co ltd
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Nantong Shangyangtong Integrated Circuit Co ltd
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Priority to CN202011536169.0A priority Critical patent/CN114664943A/en
Priority to US17/517,425 priority patent/US20220199814A1/en
Publication of CN114664943A publication Critical patent/CN114664943A/en
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Abstract

The invention discloses a planar high electron mobility transistor, comprising: the heterojunction is composed of a first semiconductor epitaxial layer and a second semiconductor epitaxial layer, and two-dimensional electron gas is positioned at the interface of the heterojunction; the surface of the bottom of the grid electrode groove of the groove grid is positioned at the bottom of the two-dimensional electron gas to cut off the two-dimensional electron gas; when the grid-source voltage is larger than or equal to the threshold voltage, an inversion layer is formed on the surface of the first semiconductor epitaxial layer covered by the side surface and the bottom surface of the grid conductive material layer, and the two-dimensional electron gas conduction of the source and drain ends enables the device to be conducted; and when the grid-source voltage is less than the threshold voltage, the two-dimensional electron gas at the source-drain end is disconnected and the device is closed. The invention can realize the control of the conduction channel of HEMTs by adopting the trench gate of the MOSFET, thereby facilitating the independent adjustment of the threshold voltage and conveniently realizing the normally-off planar high electron mobility transistor; the drift region electric field can be conveniently adjusted, so that the electric field distribution of the drift region is uniform, the breakdown voltage of the device can be improved, and the specific on-resistance and the size can be reduced.

Description

Planar high electron mobility transistor
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly to planar High Electron Mobility Transistors (HEMTs).
Background
Gallium nitride, as a typical wide bandgap semiconductor material, is often used in various studies as a power semiconductor device fabrication. Particularly, in the application of the high-temperature and high-pressure field, the gallium nitride material has more obvious advantages because the gallium nitride material has a larger forbidden band width of 3.4eV, a high breakdown electric field intensity of 3MV/cm, high electron mobility and high thermal conductivity. The mainstream gallium nitride devices have been studied so far with a focus on planar HEMTs, and the fabrication processes for such devices have matured and are already in the market stage. However, there is no uniform way to implement normally-off gan HEMTs.
The specific on-resistance (Ron, sp) of the conventional power device is related to the Breakdown Voltage (Breakdown Voltage), and the higher the Breakdown Voltage is, the higher the specific on-resistance is, the higher the Breakdown Voltage is. For conventional power semiconductor devices, there is a physical limit of Ron, sp vs. bv, also known as the one-dimensional physical limit (1-D limit).
Disclosure of Invention
The technical problem to be solved by the invention is to provide a planar high electron mobility transistor, which can cut off two-dimensional electron gas, thereby facilitating independent adjustment of threshold voltage and facilitating realization of a normally-off planar high electron mobility transistor; the electric field of the drift region can be conveniently adjusted, so that the electric field of the drift region is uniformly distributed, the breakdown voltage of the device can be improved, or the specific on-resistance of the device and the size of the device can be reduced under the condition of keeping the breakdown voltage, so that the energy loss of the device during the turning-on process can be greatly reduced; the method is suitable for the gallium nitride material, fully exerts the advantages of the gallium nitride material, reduces the manufacturing cost of the gallium nitride device and simplifies the process flow.
In order to solve the above technical problem, the present invention provides a device unit of a planar high electron mobility transistor, including:
the semiconductor device comprises a first semiconductor epitaxial layer and a second semiconductor epitaxial layer formed on the surface of the first semiconductor epitaxial layer, wherein the first semiconductor epitaxial layer and the second semiconductor epitaxial layer form a first heterojunction and form two-dimensional electron gas at the interface of the first heterojunction.
The groove gate comprises a gate groove, a gate dielectric layer formed on the inner side surface of the gate groove and a gate conductive material layer filling the gate groove.
The grid groove penetrates through the second semiconductor epitaxial layer, so that the bottom surface of the grid groove is positioned in the first semiconductor epitaxial layer at the bottom of the two-dimensional electron gas, and the two-dimensional electron gas is cut into source-end two-dimensional electron gas and drain-end two-dimensional electron gas by the groove grid.
The source metal layer and the first side face of the grid groove have a distance and form ohmic contact with the source end two-dimensional electron gas.
And the drain metal layer and the second side surface of the grid groove have intervals and form ohmic contact with the drain two-dimensional electron gas.
The gate conductive material layer is connected to the gate metal layer.
When the gate-source voltage between the gate metal layer and the source metal layer is greater than or equal to the threshold voltage, an inversion layer is formed on the surface of the first semiconductor epitaxial layer covered by the side surface and the bottom surface of the gate conductive material layer, and the inversion layer enables the source two-dimensional electron gas and the drain two-dimensional electron gas to be conducted and to form a conductive channel which enables the source metal layer and the drain metal layer to be conducted together, so that the device is conducted.
And when the grid-source voltage between the grid metal layer and the source metal layer is less than the threshold voltage, disconnecting the source two-dimensional electron gas and the drain two-dimensional electron gas and closing the device.
In a further improvement, the planar high electron mobility transistor is an enhancement mode device, and the threshold voltage is greater than 0V.
In a further improvement, the first semiconductor epitaxial layer is made of a wide bandgap semiconductor material, and the second semiconductor epitaxial layer is made of a wide bandgap semiconductor material.
In a further improvement, the material of the first semiconductor epitaxial layer comprises gallium nitride, and the material of the second semiconductor epitaxial layer comprises aluminum gallium nitride.
In a further improvement, the first semiconductor epitaxial layer is formed on a buffer layer formed on a substrate.
In a further refinement, the material of the substrate comprises silicon or sapphire.
In a further improvement, the drift region is located between the drain metal layer and the second side surface of the gate trench, a charge balance structure is arranged in the drift region, and when the drift region is reversely biased, the charge balance structure enables the electric field distribution of the drift region to be uniform.
In a further refinement, the charge balance structure comprises:
and a third semiconductor epitaxial layer is arranged on the surface of the second semiconductor epitaxial layer of the drift region, and the material of the third semiconductor epitaxial layer comprises gallium nitride.
Bound charges are formed at the interface of a second heterojunction formed by the third semiconductor epitaxial layer and the second semiconductor epitaxial layer, and the electric field distribution of the drift region is adjusted and made uniform through the bound charges at the interface of the second heterojunction.
In a further improvement, the third semiconductor epitaxial layer continuously covers the surface of the second semiconductor epitaxial layer of the drift region.
In a further improvement, the third semiconductor epitaxial layer is divided into more than one third semiconductor epitaxial layer subsegment and more than one third semiconductor epitaxial layer spacer region on the surface of the second semiconductor epitaxial layer of the drift region, and the third semiconductor epitaxial layer subsegment and the third semiconductor epitaxial layer spacer regions are alternately arranged on the surface of the second semiconductor epitaxial layer of the drift region.
In a further improvement, the number of the third semiconductor epitaxial layer subsections is 1, and the number of the third semiconductor epitaxial layer spacers is 1.
The third semiconductor epitaxial layer subsegment and the third semiconductor epitaxial layer interval area are sequentially arranged in the direction from the second side face of the grid electrode groove to the drain electrode metal layer; or, the third semiconductor epitaxial layer spacer and the third semiconductor epitaxial layer subsegment are sequentially arranged in a direction from the second side surface of the gate trench to the drain metal layer.
In a further improvement, the number of the third semiconductor epitaxial layer subsections is more than 1, and the number of the third semiconductor epitaxial layer spacers is one less than the number of the third semiconductor epitaxial layer subsections.
And the third semiconductor epitaxial layer subsegments and the third semiconductor epitaxial layer spacers are sequentially arranged in the direction from the second side face of the grid groove to the drain metal layer.
In a further improvement, the third semiconductor epitaxial layer subsegment is formed by forming the third semiconductor epitaxial layer by epitaxial growth and then selectively etching the third semiconductor epitaxial layer.
In a further improvement, the thickness of the third semiconductor epitaxial layer is 5nm or less.
In a further refinement, the charge balance structure comprises:
the thickness of the second semiconductor epitaxial layer in a direction from the second side of the gate trench to the drain metal layer has a varying structure, and the bound charge density at the interface of the first heterojunction is adjusted by adjusting the thickness of the second semiconductor epitaxial layer and thus the drift region electric field distribution is adjusted and made uniform.
In a further improvement, the second semiconductor epitaxial layer is divided into more than two second semiconductor epitaxial layer subsections according to different thicknesses in a direction from the second side surface of the gate trench to the drain metal layer.
In a further improvement, in a direction from the second side surface of the gate trench to the drain metal layer, the thicknesses of the second semiconductor epitaxial layer subsections are sequentially increased or sequentially decreased or sequentially increased first and then sequentially decreased after increasing to a maximum value or sequentially decreased first and then sequentially increased after decreasing to a minimum value.
The further improvement is that each second semiconductor epitaxial layer subsection is formed once after the second semiconductor epitaxial layer is formed, and then the thickness of the corresponding second semiconductor epitaxial layer subsection is obtained through an etching process.
Or, each second semiconductor epitaxial layer subsection is formed through multiple times of epitaxial and etching processes.
In a further improvement, the lengths of the second semiconductor epitaxial layer subsections are the same or different.
In a further improvement, in a direction from the second side of the gate trench to the drain metal layer, the thickness of the second semiconductor epitaxial layer gradually increases or gradually decreases as a function of one time, or gradually increases as a function of one time and gradually decreases as a function of one time after increasing to a maximum value, or gradually decreases as a function of one time and gradually increases as a function of one time after decreasing to a minimum value.
In a further improvement, the material of the gate dielectric layer comprises silicon oxide or aluminum oxide;
the gate conductive material layer comprises a polysilicon gate or a metal gate.
In a further refinement, the first semiconductor epitaxial layer has a first conductivity type doping or has a second conductivity type doping or is undoped.
The invention can realize the cut-off of the two-dimensional electron gas by forming the trench gate and penetrating the bottom of the gate trench of the trench gate under the two-dimensional electron gas, so that the formation of a conduction channel between a source and a drain is not controlled by the two-dimensional electron gas, but is controlled by the trench gate, and the conduction and the cut-off of the conduction channel are controlled by an inversion layer formed by inverting the epitaxial layer of the first semiconductor through the trench gate, namely the invention can realize the control of the conduction channel of HEMTs by adopting the trench gate of the MOSFET, so that the conduction and the cut-off of the conduction channel are controlled by the trench gate in the same way as the MOSFET, the threshold voltage of the planar high electron mobility transistor can be conveniently and independently adjusted, for example, the threshold voltage of a device can be adjusted by adjusting the work function of the gate conductive material layer of the trench gate, the thickness of the gate dielectric layer and the doping type and the doping concentration of the epitaxial layer of the first semiconductor, and conveniently realize the normally-off planar high electron mobility transistor; the two-dimensional electron gas of the conventional planar high electron mobility transistor is conducted and is a normally-open device, and the normally-closed planar high electron mobility transistor is conveniently realized by the method.
In addition, the invention can form a charge balance structure in the drift region between the trench gate and the drain metal layer and adjust the electric field distribution of the drift region through the charge balance structure, thereby being convenient to obtain the electric field of the uniformly distributed drift region, improving the breakdown voltage of the device or reducing the specific on-resistance of the device and the size of the device under the condition of keeping the breakdown voltage, and greatly reducing the energy loss of the device when the device is switched on; the invention can be applied to gallium nitride materials, fully exerts the advantages of the gallium nitride materials, reduces the manufacturing cost of gallium nitride devices and simplifies the process flow.
The gallium nitride power device structure can conveniently regulate and control the threshold voltage, thereby manufacturing an enhancement transistor and enabling the application scene of the enhancement transistor to be wider; compared with the traditional high electron mobility transistor, under the same breakdown voltage, the on-resistance of the transistor is greatly reduced compared with that of the existing power device, so that the power loss of the power semiconductor device can be greatly reduced, and the energy conservation and emission reduction are realized; meanwhile, the advantages of the gallium nitride device are fully exerted, the process flow is simplified, and the manufacturing cost is reduced.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a schematic structural diagram of a planar HEMT according to a first embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a planar HEMT according to a second embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a planar HEMT according to a third embodiment of the present invention;
fig. 3A is a schematic view of a first structure when the number of the third semiconductor epitaxial-layer sub-segments corresponding to fig. 3 is 1 and the number of the third semiconductor epitaxial-layer spacers is 1;
fig. 3B is a schematic diagram of a second structure when the number of the third semiconductor epitaxial-layer sub-segments corresponding to fig. 3 is 1 and the number of the third semiconductor epitaxial-layer spacers is 1;
fig. 3C is a schematic structural diagram of the third semiconductor epitaxial layer sub-segments corresponding to fig. 3, the number of which is 2, and the number of the third semiconductor epitaxial layer spacers is 1;
FIG. 4 is a schematic structural diagram of a planar HEMT according to a fourth embodiment of the present invention;
fig. 4A is a schematic structural diagram of fig. 4 when the number of the second semiconductor epitaxial layer sub-segments is 2;
FIG. 5 is a schematic structural diagram of a planar HEMT according to a fifth embodiment of the present invention;
fig. 5A is a schematic structural diagram of fig. 5 when the number of the second semiconductor epitaxial layer sub-segments is 2;
FIG. 6 is a schematic structural diagram of a planar HEMT according to a sixth embodiment of the present invention;
FIG. 7 is a schematic structural diagram of a planar HEMT according to a seventh embodiment of the present invention;
fig. 8 is a schematic structural diagram of a planar hemt according to an eighth embodiment of the present invention;
fig. 9 is a schematic structural diagram of a planar hemt according to a ninth embodiment of the present invention;
fig. 10 is a schematic structural diagram of a planar hemt according to a tenth embodiment of the present invention;
fig. 11 is a schematic structural diagram of a planar hemt according to an eleventh embodiment of the present invention.
Detailed Description
The first embodiment of the present invention is a planar high electron mobility transistor:
fig. 1 is a schematic structural diagram of a planar hemt according to a first embodiment of the present invention; the device unit of the planar high electron mobility transistor of the first embodiment of the present invention includes:
the semiconductor device comprises a first semiconductor epitaxial layer 3 and a second semiconductor epitaxial layer 4 formed on the surface of the first semiconductor epitaxial layer 3, wherein the first semiconductor epitaxial layer 3 and the second semiconductor epitaxial layer 4 form a first heterojunction and form two-dimensional electron gas at the interface of the first heterojunction.
The trench gate comprises a gate trench, a gate dielectric layer 7 formed on the inner side surface of the gate trench, and a gate conductive material layer 8 filling the gate trench.
The grid groove penetrates through the second semiconductor epitaxial layer 4, so that the bottom surface of the grid groove is positioned in the first semiconductor epitaxial layer at the bottom of the two-dimensional electron gas, and the two-dimensional electron gas is cut into source-end two-dimensional electron gas and drain-end two-dimensional electron gas by the groove grid.
The source metal layer 5 has a distance with the first side of the gate trench and forms ohmic contact with the source two-dimensional electron gas.
The drain metal layer 6 has a distance from the second side of the gate trench and forms ohmic contact with the drain two-dimensional electron gas.
The gate conductive material layer 8 is connected to the gate metal layer.
When the gate-source voltage between the gate metal layer and the source metal layer 5 is greater than or equal to the threshold voltage, an inversion layer is formed on the surface of the first semiconductor epitaxial layer 3 covered by the side surface and the bottom surface of the gate conductive material layer 8, and the inversion layer enables the source end two-dimensional electron gas and the drain end two-dimensional electron gas to be conducted and to form a conductive channel which enables the source metal layer 5 and the drain metal layer 6 to be conducted together, so that the device is conducted.
And when the grid-source voltage between the grid metal layer and the source metal layer 5 is less than the threshold voltage, disconnecting the source two-dimensional electron gas and the drain two-dimensional electron gas and closing the device.
In the first embodiment of the present invention, the planar hemt is an enhancement mode device, and the threshold voltage is greater than 0V.
The first semiconductor epitaxial layer 3 is made of a wide bandgap semiconductor material, and the second semiconductor epitaxial layer 4 is made of a wide bandgap semiconductor material.
The material of the first semiconductor epitaxial layer 3 comprises gallium nitride, and the material of the second semiconductor epitaxial layer 4 comprises aluminum gallium nitride.
The first semiconductor epitaxial layer 3 is formed on a buffer layer 2, and the buffer layer 2 is formed on a substrate 1. The material of the substrate 1 comprises silicon or sapphire.
The material of the gate dielectric layer 7 comprises silicon oxide or aluminum oxide.
The gate conductive material layer 8 includes a polysilicon gate or a metal gate.
The first semiconductor epitaxial layer 3 has a first conductivity type doping or has a second conductivity type doping or is undoped.
In the first embodiment of the present invention, the threshold voltage can be set by the doping structure of the first semiconductor epitaxial layer 3, the thickness of the gate dielectric layer 7, and the work function of the gate conductive material layer 8.
The buffer layer 2 is mainly used for releasing stress and reducing defects of the gallium nitride epitaxial layer. Since the lattice constants of the gallium nitride epitaxial layer, i.e. the first semiconductor epitaxial layer 3, and the substrate 1 are often different, the buffer layer 2 is required to eliminate the defects caused by lattice mismatch, which is a common type of superlattice or graded doping.
AlGaN (Al)xGa1-xN) the thickness of the epitaxial layer, i.e. the second semiconductor epitaxial layer 4, and the molar composition of the aluminum atoms determine the concentration of the two-dimensional electron gas at the interface, the thickness of the second semiconductor epitaxial layer 4 being designed as required.
The position of the gate dielectric layer 7 is deeper than that of the two-dimensional electron gas, so that the two-dimensional electron gas is dug and broken; during the manufacturing process, an etching process is required to realize that the bottom of the gate trench is deeper than the bottom of the second semiconductor epitaxial layer 4. The gate dielectric layer 7 is an insulator thin film formed by a deposition process, and the thickness of the gate dielectric layer determines the threshold voltage of the device and needs to be well controlled; meanwhile, the bottom of the groove is well filled in the deposition process, and the thickness is uniform.
In addition, the top of the gate conductive material layer 8 is also connected to a gate metal layer composed of a metal layer. It is also generally necessary to form an interlayer film or passivation layer to achieve isolation between the source metal layer 5, the drain metal layer 6 and the gate metal layer.
In the first embodiment of the present invention, the two-dimensional electron gas can be cut off by forming the trench gate and penetrating the bottom of the gate trench of the trench gate under the two-dimensional electron gas, so that the formation of the conduction channel between the source and the drain is not controlled by the two-dimensional electron gas, but controlled by the trench gate, and the conduction and the turn-off of the conduction channel are controlled by the inversion layer formed by inverting the first semiconductor epitaxial layer 3 by the trench gate, so that the conduction and the turn-off of the conduction channel can be controlled by the trench gate, as in the case of the planar high electron mobility transistor and the MOSFET, and the threshold voltage of the planar high electron mobility transistor can be independently adjusted, for example, the threshold voltage of the device can be adjusted by adjusting the work function of the gate conductive material layer 8 of the trench gate, the thickness of the gate dielectric layer 7, and the doping type and doping concentration of the first semiconductor epitaxial layer 3, and the normally-off planar high electron mobility transistor is conveniently realized; the two-dimensional electron gas of the conventional planar high electron mobility transistor is conducted and is a normally-on device, but the first embodiment of the present invention facilitates the realization of a normally-off planar high electron mobility transistor.
The second embodiment of the present invention is a planar high electron mobility transistor:
the planar hemt according to the second embodiment of the present invention is different from the planar hemt according to the first embodiment of the present invention in that the planar hemt according to the second embodiment of the present invention further includes the following features:
fig. 2 is a schematic structural diagram of a planar hemt according to a second embodiment of the present invention; the drift region is located between the drain metal layer 6 and the second side surface of the gate trench, a charge balance structure is arranged in the drift region, and when the drift region is reversely biased, the charge balance structure enables the electric field distribution of the drift region to be uniform. In fig. 2, the lateral regions corresponding to the drift regions are shown in parenthesis with reference 201.
In a second embodiment of the present invention, the charge balance structure comprises:
a third semiconductor epitaxial layer 101 is arranged on the surface of the second semiconductor epitaxial layer 4 of the drift region, and the material of the third semiconductor epitaxial layer 101 comprises gallium nitride.
Bound charges are formed at the interface of a second heterojunction formed by the third semiconductor epitaxial layer 101 and the second semiconductor epitaxial layer 4, and the electric field distribution of the drift region is adjusted and made uniform by the bound charges at the interface of the second heterojunction.
The third semiconductor epitaxial layer 101 continuously covers the surface of the second semiconductor epitaxial layer 4 of the drift region.
The thickness of the third semiconductor epitaxial layer 101 is 5nm or less.
In addition, the second embodiment of the present invention can form a charge balance structure in the drift region between the trench gate and the drain metal layer 6 and adjust the electric field distribution in the drift region through the charge balance structure, so as to conveniently obtain the electric field in the uniformly distributed drift region, thereby improving the breakdown voltage of the device or reducing the specific on-resistance of the device and reducing the size of the device while maintaining the adjustment of the breakdown voltage, thereby greatly reducing the energy loss of the device when the device is turned on; the second embodiment of the invention can be applied to gallium nitride materials, fully exerts the advantages of the gallium nitride materials, reduces the manufacturing cost of gallium nitride devices and simplifies the process flow.
The gallium nitride power device structure of the second embodiment of the invention can conveniently regulate and control the threshold voltage, thereby manufacturing an enhanced transistor and enabling the application scene of the enhanced transistor to be wider; compared with the traditional high electron mobility transistor, under the same breakdown voltage, the on-resistance of the transistor is greatly reduced compared with that of the existing power device, so that the power loss of the power semiconductor device can be greatly reduced, and the energy conservation and emission reduction are realized; meanwhile, the advantages of the gallium nitride device are fully exerted, the process flow is simplified, and the manufacturing cost is reduced.
The third embodiment of the present invention is a planar high electron mobility transistor:
the planar hemt according to the third embodiment of the present invention is different from the planar hemt according to the second embodiment of the present invention in that the planar hemt according to the third embodiment of the present invention further includes the following features:
fig. 3 is a schematic structural diagram of a planar hemt according to a third embodiment of the present invention; the third semiconductor epitaxial layer 101 is divided into more than one third semiconductor epitaxial layer subsegment 101a and more than one third semiconductor epitaxial layer spacer 101b on the surface of the second semiconductor epitaxial layer 4 of the drift region, and the third semiconductor epitaxial layer subsegment 101a and the third semiconductor epitaxial layer spacer 101b are alternately arranged on the surface of the second semiconductor epitaxial layer 4 of the drift region.
In the third embodiment of the present invention, the number of the third semiconductor epitaxial layers 101 can be limited, and can also be extended to be infinite, i.e., having infinite elements.
As shown in fig. 3A, it is a first structural schematic diagram when the number of the third semiconductor epitaxial-layer subsections corresponding to fig. 3 is 1 and the number of the third semiconductor epitaxial-layer spacers is 1; the number of the third semiconductor epitaxial layer subsections 101a is 1, and the number of the third semiconductor epitaxial layer spacers 101b is 1. The third semiconductor epitaxial layer subsegment 101a and the third semiconductor epitaxial layer spacer 101b are sequentially arranged in a direction from the second side of the gate trench to the drain metal layer 6.
As shown in fig. 3B, the first structure diagram is shown when the number of the third semiconductor epitaxial-layer sub-segments corresponding to fig. 3 is 1 and the number of the third semiconductor epitaxial-layer spacers is 1; the number of the third semiconductor epitaxial layer subsections 101a is 1, and the number of the third semiconductor epitaxial layer spacers 101b is 1. The third semiconductor epitaxial layer spacer 101b and the third semiconductor epitaxial layer sub-segment 101a are sequentially arranged in a direction from the second side of the gate trench to the drain metal layer 6.
Or, the number of the third semiconductor epitaxial layer subsections 101a is greater than 1, and the number of the third semiconductor epitaxial layer spacers 101b is one less than the number of the third semiconductor epitaxial layer subsections 101 a. The third semiconductor epitaxial layer subsegment 101a and the third semiconductor epitaxial layer spacer 101b are sequentially arranged in a direction from the second side of the gate trench to the drain metal layer 6. As shown in fig. 3C, the structure is schematically illustrated when the number of the third semiconductor epitaxial-layer sub-segments corresponding to fig. 3 is 2 and the number of the third semiconductor epitaxial-layer spacers is 1; it can be seen that the third semiconductor epitaxial-layer subsegment 101a and the third semiconductor epitaxial-layer spacer 101b are sequentially aligned in a direction from the second side of the gate trench to the drain metal layer 6.
The fourth embodiment of the present invention is a planar high electron mobility transistor:
the difference between the planar hemt of the fourth embodiment of the present invention and the planar hemt of the first embodiment of the present invention is that the planar hemt of the fourth embodiment of the present invention further comprises the following features:
fig. 4 is a schematic structural diagram of a planar hemt according to a fourth embodiment of the present invention; the drift region is located between the drain metal layer 6 and the second side surface of the gate trench, a charge balance structure is arranged in the drift region, and when the drift region is reversely biased, the charge balance structure enables the electric field distribution of the drift region to be uniform. In fig. 4, the lateral regions corresponding to the drift regions are shown in parenthesis with reference 201.
The charge balance structure includes:
the thickness of the second semiconductor epitaxial layer 4 in the direction from the second side of the gate trench to the drain metal layer 6 has a varying structure, and the bound charge density at the interface of the first heterojunction and thus the drift region electric field distribution are adjusted and made uniform by adjusting the thickness of the second semiconductor epitaxial layer 4.
And the second semiconductor epitaxial layer 4 is divided into more than two second semiconductor epitaxial layer subsections 4a from the second side surface of the gate trench to the drain metal layer 6 according to different thicknesses.
In the fourth embodiment of the present invention, the thickness of each of the second semiconductor epitaxial layer subsections 4a decreases in sequence from the second side of the gate trench to the drain metal layer 6.
Each second semiconductor epitaxial layer subsection 4a is formed once after the second semiconductor epitaxial layer 4 is formed, and then the thickness of the corresponding second semiconductor epitaxial layer subsection 4a is obtained through an etching process. Alternatively, each of the second semiconductor epitaxial layer subsegments 4a is formed by multiple epitaxial and etching processes.
The lengths of the second semiconductor epitaxial layer subsections 4a are the same or different.
As shown in fig. 4A, it is a schematic structural diagram when the number of the second semiconductor epitaxial layer sub-segments corresponding to fig. 4 is 2; it can be seen that there are two of said second semiconductor epitaxial layer subsections 4a which decrease in thickness in the direction from the second side of said gate trench to said drain metal layer 6.
The number of said second semiconductor epitaxial-layer subsections 4a can extend from a limited number to an unlimited number.
The fifth embodiment of the present invention is a planar high electron mobility transistor:
the difference between the planar hemt of the fifth embodiment of the present invention and the planar hemt of the fourth embodiment of the present invention is that the planar hemt of the fifth embodiment of the present invention further comprises the following features:
fig. 5 is a schematic structural diagram of a planar hemt according to a fifth embodiment of the present invention; the thickness of each second semiconductor epitaxial layer subsection 4a increases in sequence from the second side of the gate trench to the drain metal layer 6.
As shown in fig. 5A, it is a schematic structural diagram when the number of the second semiconductor epitaxial layer sub-segments corresponding to fig. 5 is 2; it can be seen that there are two of the second semiconductor epitaxial layer subsections 4a that increase in thickness in a direction from the second side of the gate trench to the drain metal layer 6.
The sixth embodiment of the present invention is a planar high electron mobility transistor:
the difference between the planar hemt of the sixth embodiment of the present invention and the planar hemt of the fourth embodiment of the present invention is that the planar hemt of the sixth embodiment of the present invention further comprises the following features:
fig. 6 is a schematic structural diagram of a planar hemt according to a sixth embodiment of the present invention; in the direction from the second side surface of the gate trench to the drain metal layer 6, the thickness of each second semiconductor epitaxial layer subsection 4a increases sequentially and then decreases sequentially after increasing to the maximum value.
The seventh embodiment of the present invention is a planar high electron mobility transistor:
the difference between the planar hemt of the seventh embodiment of the present invention and the planar hemt of the fourth embodiment of the present invention is that the planar hemt of the seventh embodiment of the present invention further comprises the following features:
fig. 7 is a schematic structural diagram of a planar hemt according to a seventh embodiment of the present invention; in the direction from the second side surface of the gate trench to the drain metal layer 6, the thickness of each second semiconductor epitaxial layer subsection 4a is sequentially reduced and then sequentially increased after being reduced to the minimum value.
The eighth embodiment of the present invention is a planar high electron mobility transistor:
the planar hemt according to the eighth embodiment of the present invention is different from the planar hemt according to the fourth embodiment of the present invention in that the planar hemt according to the eighth embodiment of the present invention further includes the following features:
fig. 8 is a schematic structural diagram of a planar hemt according to an eighth embodiment of the present invention; the charge balance structure includes:
the thickness of the second semiconductor epitaxial layer 4 in the direction from the second side of the gate trench to the drain metal layer 6 has a varying structure, and the bound charge density at the interface of the first heterojunction and thus the drift region electric field distribution are adjusted and made uniform by adjusting the thickness of the second semiconductor epitaxial layer 4. In fig. 8, the second semiconductor epitaxial layer in region 201 is separately identified by reference numeral 4 b.
In the eighth embodiment of the present invention, the thickness of the second semiconductor epitaxial layer 4b is gradually reduced as a linear function in a direction from the second side of the gate trench to the drain metal layer 6. The first order function is also a linear function.
The ninth embodiment of the present invention is a planar high electron mobility transistor:
the planar high electron mobility transistor according to the ninth embodiment of the present invention is different from the planar high electron mobility transistor according to the eighth embodiment of the present invention in that the planar high electron mobility transistor according to the ninth embodiment of the present invention further includes the following features:
fig. 9 is a schematic structural diagram of a planar hemt according to a ninth embodiment of the present invention; the thickness of the second semiconductor epitaxial layer 4 gradually increases as a linear function in a direction from the second side of the gate trench to the drain metal layer 6.
Tenth embodiment of the invention a planar high electron mobility transistor:
the difference between the planar hemt of the tenth embodiment of the present invention and the planar hemt of the eighth embodiment of the present invention is that the planar hemt of the tenth embodiment of the present invention further comprises the following features:
fig. 10 is a schematic structural diagram of a planar hemt according to a tenth embodiment of the present invention; in the direction from the second side of the gate trench to the drain metal layer 6, the thickness of the second semiconductor epitaxial layer 4 gradually increases as a linear function and then gradually decreases as a linear function after increasing to a maximum value.
Eleventh embodiment of the invention a planar high electron mobility transistor:
the planar high electron mobility transistor according to the eleventh embodiment of the present invention is different from the planar high electron mobility transistor according to the eighth embodiment of the present invention in that the planar high electron mobility transistor according to the eleventh embodiment of the present invention further includes the following features:
fig. 11 is a schematic structural diagram of a planar hemt according to an eleventh embodiment of the present invention; in the direction from the second side of the gate trench to the drain metal layer 6, the thickness of the second semiconductor epitaxial layer 4 gradually decreases as a linear function and then gradually increases as a linear function after decreasing to a minimum value.
The device structure of the embodiment of the invention has important value in the power semiconductor device taking gallium nitride as a base material. However, the device structure according to the embodiment of the present invention is not limited to the gan material, and any material used for manufacturing the power semiconductor device may be applicable.
The embodiment of the invention is based on some innovative structures provided on the basis of a typical gallium nitride high electron mobility transistor, and the core of the embodiment of the invention comprises the design of a drift region of a planar device by utilizing a charge balance concept, and the structure can optimize the electric field distribution to make the electric field distribution more uniform, thereby achieving the purpose of optimizing the breakdown voltage and the reliability of the device.
The device structure of the embodiment of the invention is an innovative structure based on a gallium nitride high electron mobility transistor, and the device mainly relies on a heterostructure of aluminum gallium nitride (AlGaN) and gallium nitride (GaN), and two-dimensional electron gas (2DEG) at the device is used as a conducting channel. However, the structure of the device provided by the embodiment of the invention is not limited to be used for the gallium nitride heterostructure, and can also be used for other heterostructures;
the device of the embodiment of the invention firstly utilizes the MOS structure as the channel to realize the normally-off device, combines the traditional MOSFETs and HEMTs and fully exerts the advantages of the two device structures.
Secondly, the embodiment of the invention applies the concept of charge balance to the high electron mobility device, and a thin GaN layer is grown on the surface of the AlGaN epitaxial layer, that is, charges with opposite polarity can be introduced into the third semiconductor epitaxial layer 101, so that the effect of charge balance can be achieved. The structure can be expanded, for example, the top GaN layer is locally removed, so that the local electric field distribution is changed, the design freedom of the device is higher, and a plurality of variable structures can be added.
Thirdly, besides introducing the top GaN layer, the interface charge engineering can also be achieved by locally etching the AlGaN, namely the second semiconductor epitaxial layer 4, and since the density of the interface charge can be changed by the thickness of the AlGaN, the distribution of the charge density in the whole drift region can be changed by locally removing the AlGaN layer. The following expansion can be made: if the drift region is divided into a limited number of small cells and the AlGaN layer of each small cell is specifically processed, the charge distribution of the entire drift region can be designed according to the design requirement, so that the electric field distribution is further improved. The following extension can be further made: the drift region is divided into infinite small units, the AlGaN thickness of each unit can achieve the effect of gradual change, and the electric charge distribution of the drift region is continuously functionalized by utilizing the concept of calculus, so that the electric field distribution is optimized.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (22)

1. A planar hemt, wherein the device cell comprises:
the two-dimensional electron gas generation device comprises a first semiconductor epitaxial layer and a second semiconductor epitaxial layer formed on the surface of the first semiconductor epitaxial layer, wherein the first semiconductor epitaxial layer and the second semiconductor epitaxial layer form a first heterojunction and form two-dimensional electron gas at the interface of the first heterojunction;
the trench gate comprises a gate trench, a gate dielectric layer formed on the inner side surface of the gate trench and a gate conductive material layer filling the gate trench;
the grid groove penetrates through the second semiconductor epitaxial layer, so that the bottom surface of the grid groove is positioned in the first semiconductor epitaxial layer at the bottom of the two-dimensional electron gas, and the two-dimensional electron gas is cut into source-end two-dimensional electron gas and drain-end two-dimensional electron gas by the groove grid;
the source metal layer and the first side face of the grid groove have a distance and form ohmic contact with the source end two-dimensional electron gas;
the drain metal layer and the second side surface of the grid groove have intervals and form ohmic contact with the drain two-dimensional electron gas;
the gate conductive material layer is connected to the gate metal layer;
when the gate-source voltage between the gate metal layer and the source metal layer is greater than or equal to the threshold voltage, an inversion layer is formed on the surface of the first semiconductor epitaxial layer covered by the side surface and the bottom surface of the gate conductive material layer, and the inversion layer enables the source two-dimensional electron gas and the drain two-dimensional electron gas to be conducted and to form a conductive channel which enables the source metal layer and the drain metal layer to be conducted together, so that the device is conducted;
and when the grid-source voltage between the grid metal layer and the source metal layer is less than the threshold voltage, the source two-dimensional electron gas and the drain two-dimensional electron gas are disconnected, and the device is closed.
2. The planar hemt of claim 1, wherein: the planar high electron mobility transistor is an enhancement mode device, and the threshold voltage is greater than 0V.
3. The planar hemt of claim 2, wherein: the first semiconductor epitaxial layer is made of a wide bandgap semiconductor material, and the second semiconductor epitaxial layer is made of a wide bandgap semiconductor material.
4. The planar hemt of claim 3, wherein: the material of the first semiconductor epitaxial layer comprises gallium nitride, and the material of the second semiconductor epitaxial layer comprises aluminum gallium nitride.
5. The planar hemt of claim 4, wherein: the first semiconductor epitaxial layer is formed on a buffer layer formed on a substrate.
6. The planar hemt of claim 5, wherein: the material of the substrate comprises silicon or sapphire.
7. The planar hemt of claim 4, wherein: the drift region is located between the drain metal layer and the second side face of the grid groove, a charge balance structure is arranged in the drift region, and when the drift region is reversely biased, the charge balance structure enables the electric field of the drift region to be uniformly distributed.
8. The planar hemt of claim 7, wherein: the charge balance structure includes:
a third semiconductor epitaxial layer is arranged on the surface of the second semiconductor epitaxial layer of the drift region, and the material of the third semiconductor epitaxial layer comprises gallium nitride;
bound charges are formed at the interface of a second heterojunction formed by the third semiconductor epitaxial layer and the second semiconductor epitaxial layer, and the electric field distribution of the drift region is adjusted and made uniform through the bound charges at the interface of the second heterojunction.
9. The planar hemt of claim 8, wherein: the third semiconductor epitaxial layer continuously covers the surface of the second semiconductor epitaxial layer of the drift region.
10. The planar hemt of claim 8, wherein: the third semiconductor epitaxial layer on the surface of the second semiconductor epitaxial layer of the drift region is divided into more than one third semiconductor epitaxial layer subsegment and more than one third semiconductor epitaxial layer spacer, and the third semiconductor epitaxial layer subsegment and the third semiconductor epitaxial layer spacer are alternately arranged on the surface of the second semiconductor epitaxial layer of the drift region.
11. The planar hemt of claim 10, wherein: the number of the third semiconductor epitaxial layer subsegments is 1, and the number of the third semiconductor epitaxial layer spacers is 1;
the third semiconductor epitaxial layer subsegment and the third semiconductor epitaxial layer interval area are sequentially arranged in the direction from the second side face of the grid electrode groove to the drain electrode metal layer; or, the third semiconductor epitaxial layer spacer and the third semiconductor epitaxial layer subsegment are sequentially arranged in a direction from the second side surface of the gate trench to the drain metal layer.
12. The planar hemt of claim 10, wherein: the number of the third semiconductor epitaxial layer subsections is more than 1, and the number of the third semiconductor epitaxial layer interval regions is one less than that of the third semiconductor epitaxial layer subsections;
and the third semiconductor epitaxial layer subsegment and the third semiconductor epitaxial layer interval area are sequentially arranged in the direction from the second side surface of the gate trench to the drain metal layer.
13. The planar hemt of claim 10, wherein: and the third semiconductor epitaxial layer subsegment is formed by selectively etching the third semiconductor epitaxial layer after the third semiconductor epitaxial layer is formed by epitaxial growth.
14. The planar hemt of any one of claims 8-13, wherein: the thickness of the third semiconductor epitaxial layer is 5nm or less.
15. The planar hemt of claim 7, wherein: the charge balance structure includes:
the thickness of the second semiconductor epitaxial layer in the direction from the second side of the gate trench to the drain metal layer has a varying structure, and bound charge density at the interface of the first heterojunction is adjusted by adjusting the thickness of the second semiconductor epitaxial layer and thus the drift region electric field distribution is adjusted and made uniform.
16. The planar hemt of claim 15, wherein: and the second semiconductor epitaxial layer is divided into more than two second semiconductor epitaxial layer subsections according to different thicknesses in the direction from the second side surface of the gate trench to the drain metal layer.
17. The planar hemt of claim 16, wherein: in the direction from the second side surface of the gate trench to the drain metal layer, the thicknesses of the second semiconductor epitaxial layer subsections are sequentially increased or sequentially decreased or sequentially increased first and then sequentially decreased after being increased to the maximum value or sequentially decreased first and then sequentially increased after being decreased to the minimum value.
18. The planar hemt of claim 16, wherein: each second semiconductor epitaxial layer subsection is formed once after the second semiconductor epitaxial layer is formed, and then the thickness of the corresponding second semiconductor epitaxial layer subsection is obtained through an etching process;
or, each second semiconductor epitaxial layer subsection is formed through multiple times of epitaxial and etching processes.
19. The planar hemt of claim 16 or 17, wherein: the lengths of the second semiconductor epitaxial layer subsections are the same or different.
20. The planar hemt of claim 15, wherein: in the direction from the second side face of the gate trench to the drain metal layer, the thickness of the second semiconductor epitaxial layer gradually increases according to a linear function or gradually decreases according to a linear function or gradually increases according to a linear function first and then gradually decreases according to a linear function after increasing to a maximum value or gradually decreases according to a linear function first and then gradually increases according to a linear function after decreasing to a minimum value.
21. The planar hemt of claim 4, wherein: the gate dielectric layer is made of silicon oxide or aluminum oxide;
the gate conductive material layer comprises a polysilicon gate or a metal gate.
22. The planar hemt of claim 4, wherein: the first semiconductor epitaxial layer has a first conductivity type doping or has a second conductivity type doping or is undoped.
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