CN113707708B - Junction accumulation layer enhanced AlGaN/GaN high electron mobility transistor and manufacturing method thereof - Google Patents
Junction accumulation layer enhanced AlGaN/GaN high electron mobility transistor and manufacturing method thereof Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
Abstract
The invention discloses a junction accumulation layer enhanced AlGaN/GaN high electron mobility transistor, which grows accumulation dielectric layers on the surfaces of an AlGaN layer and a GaN layer and is correspondingly connected with an ohmic source electrode and an ohmic drain electrode respectively; growing an epitaxial layer on the accumulated dielectric layer in the gate source region, and forming a P + region and an N + region at the left end and the right end of the epitaxial layer through ion implantation; an epitaxial grid electrode is formed above the N + region at the left end of the epitaxial layer through ohmic contact, and an epitaxial drain electrode is formed above the P + region at the right end of the epitaxial layer; the ohmic drain electrode is connected with the epitaxial drain electrode through a lead and is used as the drain electrode of the device; the Schottky gate is connected with the epitaxial gate through a lead and is used as a gate of the device; when a positive voltage is applied to the grid electrode, the accumulated dielectric layer generates a large number of electrons in the GaN layer to be connected with two-dimensional electrons to form a conduction channel, so that the enhancement of the device is realized; when the device is reversely biased, the inner electric field can be optimized through the AlGaN epitaxial layer, so that the electric field distribution is more uniform, and the breakdown voltage of the device can be greatly improved.
Description
Technical Field
The invention relates to the field of semiconductor devices, in particular to an enhanced AlGaN/GaN high electron mobility transistor.
Background
Compared with the performance of silicon power devices, the performance of GaN (gallium nitride) power devices has obvious advantages. Among them, alGaN/GaN HEMT devices represented by AlGaN/GaN High Electron Mobility transistors HEMTs (High Electron Mobility transistors) have characteristics of High output power density, high temperature resistance, radiation resistance, and the like.
It is known that due to strong spontaneous polarization and piezoelectric polarization effects, a high concentration of two-Dimensional Electron Gas (2deg. In the application of low-power-consumption digital integrated circuits, the integration of enhancement type and depletion type devices on a single wafer is necessary, and the realization of a novel high-voltage-resistance enhancement type AlGaN/GaN HEMTs device is one of key technologies to be solved when a GaN-based power electronic device is applied to the field of power semiconductors.
As shown in fig. 1, a current trench gate enhancement HEMT device with a field plate structure mainly includes: the GaN-based semiconductor device comprises a substrate 01, a GaN layer 02 which is positioned on a semi-insulating substrate and epitaxially grows, an ohmic source electrode 03 and an ohmic drain electrode 08 which are connected with the GaN layer, and an AlGaN layer 04 which is positioned on the GaN layer and epitaxially grows heterologously; a groove grid 05, a grid field plate 06 and a dielectric passivation layer 07 which are positioned on the AlGaN layer.
In the manufacturing process of the groove gate enhanced HEMT device, the thickness of the AlGaN layer 4 and the etching depth of the groove gate 5 are difficult to control accurately, so that the process repeatability is poor, and the controllability of the threshold voltage is poor; in addition, through a common termination optimization technology (such as a field plate, resurf, and the like), the breakdown voltage is increased while the on-resistance is inevitably increased, so that designers often need compromise processing to obtain optimal device performance.
Disclosure of Invention
In order to solve the problem that the existing enhanced AlGaN/GaN HEMTs can not meet the requirements of both on-resistance and breakdown voltage, the invention provides a junction accumulation layer enhanced AlGaN/GaN high electron mobility transistor.
Meanwhile, a manufacturing method of the high electron mobility transistor is also provided.
The technical scheme of the invention is as follows:
provided is a junction accumulation layer enhanced AlGaN/GaN high electron mobility transistor comprising:
the ohmic source electrode is positioned at the left end of the GaN layer;
the ohmic drain electrode is positioned at the right end of the GaN layer;
growing an AlGaN layer on the surface of the GaN layer, and forming an AlGaN/GaN heterojunction through heteroepitaxy, wherein the AlGaN layer is divided into two parts, the left half part is connected with an ohmic source electrode, and the right half part is connected with an ohmic drain electrode;
a Schottky gate on the upper surface of the right side of the left half AlGaN layer;
the accumulation dielectric layer covers the right side of the left half AlGaN layer, the left side of the right half AlGaN layer, the area between the upper surfaces of the GaN layers, and the upper surfaces of the left half AlGaN layer and the right half AlGaN layer;
epitaxial layer provided with accumulation mediumA region on the upper surface of the layer and between the Schottky gate and the ohmic drain; the left side end and the right side end of the epitaxial layer are respectively formed with P by ion implantation + Region and N + A zone;
the epitaxial grid is in ohmic contact with the upper surface of the left side end of the epitaxial layer;
the epitaxial drain electrode is in ohmic contact with the upper surface of the right side end of the epitaxial layer, and the left boundary of the epitaxial drain electrode is spaced from the N + region of the epitaxial layer;
the ohmic drain electrode is connected with the epitaxial drain electrode through a lead and is integrally used as the drain electrode of the device;
the Schottky gate is connected with the epitaxial gate through a lead, and the whole Schottky gate is used as a gate of the device.
Optionally, the substrate is made of a semiconductor material and can be Si, sapphire or SiC.
Optionally, the doping concentration of the GaN layer is 1 × 10 15 cm -3 ～1×10 17 cm -3 。
Optionally, the AlGaN layer has a thickness of 15 to 25nm.
Optionally, the material of the accumulation dielectric layer is an insulating material, and the thickness of the accumulation dielectric layer is 0.03-0.1 μm.
Optionally, the doping concentration of the epitaxial layer is 1 × 10 15 cm -3 ～1×10 17 cm -3 The thickness is 0.1-2 μm.
Optionally, the epitaxial layer P + The doping concentration of the region is 1 × 10 18 cm -3 ～1×10 20 cm -3 The length is 0.5-2 μm.
Optionally, the epitaxial layer N + The doping concentration of the region is 1 × 10 18 cm -3 ～1×10 20 cm -3 The length is 0.2-0.6 μm.
Optionally, the epitaxial layer N + The distance between the region and the epitaxial drain is 0.2-1 μm.
The manufacturing method of the junction accumulation layer enhanced AlGaN/GaN high electron mobility transistor comprises the following steps of:
step 1: preparing a substrate from a semiconductor material;
step 2: growing a GaN layer on a substrate;
and 3, step 3: forming an AlGaN layer on the GaN layer through heteroepitaxy;
and 4, step 4: the optimal breakdown voltage of the device is obtained through simulation, the length of the right half AlGaN layer (4) is calculated, and then a partial AlGaN layer in the middle area is etched through a plasma etching method, so that a left half AlGaN layer and a right half AlGaN layer are formed;
and 5: forming a Schottky gate on the upper surface of the right side of the left AlGaN layer;
and 6: growing accumulation dielectric layers on the right side of the AlGaN layer of the left half part, the left side of the AlGaN layer of the right half part, the region between the upper surfaces of the GaN layers, and the upper surfaces of the AlGaN layer of the left half part and the AlGaN layer of the right half part;
and 7: further growing an epitaxial layer on the accumulation medium layer, etching off the epitaxial layer above the AlGaN layer at the left half part and the epitaxial layer above the rightmost side of the GaN layer, and forming P at the left side end and the right side end of the epitaxial layer by ion implantation + Region and N + A zone;
and step 8: on the upper surface of the epitaxial layer corresponding to P + Depositing metal at the position of the region to form an epitaxial grid electrode, simultaneously depositing metal on the upper surface of the rightmost end of the epitaxial layer to form an epitaxial drain electrode, and depositing metal above the leftmost end and the rightmost end of the upper surface of the GaN layer to form an ohmic source electrode and an ohmic drain electrode;
and step 9: connecting the ohmic drain electrode with the epitaxial drain electrode to form a drain electrode of the whole device; the Schottky gate is connected with the epitaxial gate through a lead to form a gate of the whole device;
step 10: and forming a passivation layer on the surface of the device.
The technical scheme of the invention has the following beneficial effects:
1. when the grid voltage is zero, the GaN layer below the epitaxial grid electrode does not have a complete conduction channel, the device is in a cut-off state, the accumulation dielectric layer is used above the transistor, the grid electrode applies forward voltage, a large number of accumulated electrons of the GaN layer are connected with the AlGaN/GaN polarized 2DEG through the accumulation dielectric layer to form a conductive channel, and under the action of drain-source voltageThe enhancement mode device that achieves device turn-on, and thus gate-controlled normally-off, is achieved. And as the gate voltage increases, the partially accumulated electron concentration gradually approaches and exceeds the 2DEG concentration, further reducing the HEMT on-resistance. When the device works in the forward direction, the accumulation dielectric layer accumulates a large number of electrons on the GaN layer, and the bottom of the epitaxial layer can accumulate equivalent holes, and N is arranged on the epitaxial layer + The epitaxial layer is utilized to shield the high electric field at the edge of the grid electrode, and the thickness and the length of the right half AlGaN layer are determined in advance, so that the electric field distribution is optimized, and the breakdown voltage of the device is improved.
2. According to the invention, an enhancement device is realized by controlling the accumulation layer electron through the epitaxial grid, the withstand voltage is greatly improved under the condition of keeping the advantage of low on-resistance of HEMT, the on-state and withstand voltage modes of the device are changed, the contradiction between withstand voltage and on-resistance in the design of the traditional HEMT device is broken, and a high-performance device is obtained.
3. Compared with the traditional depletion type AlGaN/GaN HEMT, the invention realizes enhancement by controlling the generation of GaN layer accumulation electrons through the epitaxial grid, and simultaneously, the method of forming the device grid by using the Schottky grid (5) and the epitaxial grid (7) not only can realize the enhancement type AlGaN/GaN HEMT, but also is beneficial to reducing the problem of large leakage current caused by the traditional enhancement type grid process, and can effectively improve the reliability of the device.
Drawings
Fig. 1 is a schematic structural diagram of a conventional field plate trench gate AlGaN/GaN hemt device.
The reference numerals of fig. 1 are as follows:
01-a substrate; 02-GaN layer; 03-ohmic drain electrode; 04-AlGaN layer; 05-a recessed gate; 06-gate field plate; 07-dielectric passivation layer, 08-ohmic drain.
Fig. 2 is a schematic diagram of a junction accumulation layer enhanced AlGaN/GaN HEMTs device according to an embodiment of the present invention.
The reference numbers of fig. 2 are as follows:
1-a substrate; 2-a GaN layer; a 3-ohm drain electrode; a 4-AlGaN layer; 5-a schottky gate; a 6-P + region; 7-epitaxial gate; 8-a dielectric accumulation layer; 9-an epitaxial layer; a 10-N + region; 11-epitaxial drain; 12-ohm drain.
Fig. 3 is a comparison graph of output characteristics of field plate trench gate AlGaN/GaN HEMTs according to the embodiments of the present invention.
Fig. 4 is a schematic diagram showing the comparison of the breakdown voltages of the field plate trench gate AlGaN/GaN HEMTs according to the embodiment of the present invention.
Detailed Description
The present invention will be further described in detail by way of examples with reference to the accompanying drawings.
The present embodiment provides a specific structure of a junction accumulation layer enhanced AlGaN/GaN high electron mobility transistor, as shown in fig. 1, including:
the substrate 1 is made of semiconductor materials, and can be Si, sapphire or SiC;
a GaN layer 2 having a doping concentration of 1 × 10 in this embodiment is formed on a substrate 1 15 cm -3 ～1×10 17 cm -3 ；
An AlGaN layer 4 grows on the surface of the GaN layer 2, an AlGaN/GaN heterojunction is formed through heteroepitaxy, and the AlGaN/GaN heterojunction is divided into a left part and a right part, wherein the left side of the AlGaN layer 4 in the left half part is connected with an ohmic source electrode 3, and the right side of the AlGaN layer 4 in the right half part is connected with an ohmic drain electrode 12; in this embodiment, the AlGaN layer has a thickness of 15 to 25nm;
accumulation dielectric layers 8 are arranged in the regions between the right side of the AlGaN layer 4 in the left half part, the left side of the AlGaN layer 4 in the right half part and the upper surface of the GaN layer 2, and the upper surfaces of the AlGaN layer 4 in the left half part and the AlGaN layer 4 in the right half part; the material of the accumulation medium layer 8 is an insulating material, silicon dioxide or aluminum oxide can be selected, and the typical value of the thickness of the accumulation medium layer is 0.03-0.1 mu m;
accumulating the upper surface of the dielectric layer 8, and growing an epitaxial layer 9 in a region between the Schottky gate 5 and the ohmic drain (12); the thickness of the epitaxial layer 9 is 0.1-2 μm; the N-type doping concentration is 1 x 10 15 cm -3 ～1×10 17 cm -3 (in some cases, the dopant may be P-type, lightly doped or undoped, or lightly doped to a concentration lower than N + Doping concentration of the region);
p is formed at the left side end and the right side end of the epitaxial layer 9 by ion implantation + Region 6 and N + A region 10; in this example, P + The doping concentration of the region is 1 × 10 18 cm -3 ～1×10 20 cm -3 The length is 0.5-2 mu m; n is a radical of + The doping concentration of the region is 1 × 10 18 cm -3 ～1×10 20 cm -3 The length is 0.2-0.6 μm;
the epitaxial layer 9 has a left side end surface formed with the epitaxial gate 7 by ohmic contact, a right side end surface formed with the epitaxial drain 11 by ohmic contact, and a left boundary of the epitaxial drain 11 and the epitaxial layer N + The interval exists in the area 10, and the value of the interval is 0.2-1 mu m;
the ohmic source electrode 3 is positioned at the left end of the GaN layer 2;
the ohmic drain electrode 12 is positioned at the right end of the GaN layer 2;
the epitaxial drain 11 and the ohmic drain 12 are connected through a wire and are integrally used as the drain of the device;
the Schottky gate 5 is connected with the epitaxial gate 7 to form the gate of the whole device, enhancement is realized by controlling the generation of GaN layer accumulation electrons through the epitaxial gate, and meanwhile, the method of forming the device gate by the Schottky gate (5) and the epitaxial gate (7) not only can realize enhancement type AlGaN/GaN HEMT, but also is beneficial to reducing the problem of large leakage current caused by the traditional enhancement type gate process, and can effectively improve the reliability of the device.
The device can be prepared by the following steps:
step 1: preparing a substrate 1 from a semiconductor material;
step 2: growing a GaN layer 2 on a substrate 1;
and step 3: forming an AlGaN layer 4 on the GaN layer 2 by heteroepitaxy;
and 4, step 4: the optimal breakdown voltage of the device obtained through simulation is 863V, the length of the right half AlGaN layer (4) is calculated to be 3 mu m, and then a part of the AlGaN layer 4 in the middle area is etched away through a plasma etching method, so that the left half AlGaN layer 4 and the right half AlGaN layer 4 are formed;
and 5: a Schottky gate 5 is formed on the upper surface of the right side of the AlGaN layer 4 on the left half part;
step 6: an accumulation dielectric layer 8 is grown on the right side of the AlGaN layer 4 in the left half, the left side of the AlGaN layer 4 in the right half, the region between the upper surfaces of the GaN layers 2, and the upper surfaces of the AlGaN layer 4 in the left half and the AlGaN layer 4 in the right half;
and 7: further growing an epitaxial layer 9 on the accumulation medium layer 8, etching off the epitaxial layer 9 above the AlGaN layer 4 in the left half part and above the rightmost side of the GaN layer 2, and then forming P at the left side end and the right side end of the epitaxial layer 9 by ion implantation + Region 6 and N + A region 10;
and 8: on the upper surface of the epitaxial layer 8 corresponding to P + Depositing metal at the position of the region 6 to form an epitaxial grid 7, depositing metal on the upper surface of the rightmost end of the epitaxial layer to form an epitaxial drain 11, and depositing metal above the leftmost end and the rightmost end of the upper surface of the GaN layer 2 to form an ohmic source 3 and an ohmic drain 12;
and step 9: connecting the ohmic drain electrode 12 with the epitaxial drain electrode 11 to form a drain electrode of the whole device; the Schottky gate 5 is connected with the epitaxial gate 7 through a lead to form a gate of the whole device;
step 10: and forming a passivation layer on the surface of the device.
Through simulation experiments, as shown in fig. 3, when the spacing length between the gate and the drain is 6 μm, the on-resistance of the AlGaN/GaN HEMTs with field plate trench gate enhancement mode is substantially similar to the on-resistance of the embodiment by 9.96 Ω. As shown in fig. 4, the breakdown voltage of the AlGaN/GaN HEMTs with the field plate trench gate is only about 352V, but the breakdown voltage of the device can be increased to 863V by 145% in this embodiment; it is required to point out that the trench gate enhanced AlGaN/GaN HEMTs used for comparison adopt a field plate technology to optimize the withstand voltage of the device, and the length of the field plate is about 2 μm;
the above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, many modifications and substitutions can be made without departing from the technical principle of the present invention, and these modifications and substitutions also fall into the protection scope of the present invention.
Claims (8)
1. A junction accumulation layer enhanced AlGaN/GaN high electron mobility transistor comprises a substrate (1) made of semiconductor materials, a GaN layer (2), an ohmic source electrode (3), an AlGaN layer (4), a grid electrode, an accumulation dielectric layer (8) and an ohmic drain electrode (12);
the method is characterized in that:
the AlGaN layer (4) is arranged on the upper surface of the GaN layer (2) and is divided into a left part and a right part, the left side of the AlGaN layer (4) on the left half part is connected with the ohmic source electrode (3), and the right side of the AlGaN layer (4) on the right half part is connected with the ohmic drain electrode (12);
accumulation dielectric layers (8) are arranged on the right side of the left half AlGaN layer (4), the left side of the right half AlGaN layer (4), a region between the upper surfaces of the GaN layers (2), the upper surface of the left side of the left half AlGaN layer (4) and the upper surface of the right half AlGaN layer (4);
a Schottky gate (5) is arranged on the upper surface of the right side of the AlGaN layer (4) in the left half part;
an epitaxial layer (9) is arranged on the upper surface of the accumulation dielectric layer (8) and in a region between the Schottky gate electrode (5) and the ohmic drain electrode (12);
the left side end and the right side end of the epitaxial layer (9) are respectively formed with P by ion implantation + Region (6) and N + A zone (10);
an epitaxial gate (7) is arranged on the upper surface of the left side of the epitaxial layer (9), and the epitaxial gate (7) is positioned at P + An epitaxial drain (11) is arranged on the upper surface of the right side of the epitaxial layer (9) above the region (6), and the left boundary of the epitaxial drain (11) and the epitaxial layer N + The zones (10) being spaced apart;
the Schottky gate (5) is connected with the epitaxial gate (7) through a lead, and the whole Schottky gate is used as a gate of the device;
the ohmic drain (12) is connected with the epitaxial drain (11) through a lead and is integrally used as the drain of the device;
the length of the AlGaN layer (4) on the right half part is 1/3-2/3 of the distance between the grid electrode and the drain electrode of the transistor, and the thickness of the AlGaN layer is 15-25 nm.
2. The junction accumulation layer enhanced AlGaN/GaN high electron mobility transistor according to claim 1, wherein: the substrate (1) of semiconductor material is silicon, sapphire or silicon carbide.
3. The junction accumulation layer enhanced AlGaN/GaN high electron mobility transistor according to claim 1, wherein: the doping concentration of the GaN layer (2) is 1 x 10 15 cm -3 ～1×10 17 cm -3 。
4. The junction accumulation layer enhanced AlGaN/GaN high electron mobility transistor according to claim 1, wherein: the accumulation dielectric layer (8) is made of insulating materials and has the thickness of 0.03-0.1 mu m.
5. The junction accumulation layer enhanced AlGaN/GaN high electron mobility transistor according to claim 1, wherein: the epitaxial layer (9) is made of semiconductor material and has a doping concentration of 1 × 10 15 cm -3 ～1×10 17 cm -3 The thickness is 0.1-2 μm.
6. The junction accumulation layer enhanced AlGaN/GaN high electron mobility transistor according to claim 1, wherein: the left end P of the epitaxial layer + The doping concentration of the region (6) is 1 x 10 18 cm -3 ～1×10 20 cm -3 The length is 0.5-2 μm.
7. The junction accumulation layer enhanced AlGaN/GaN high electron mobility transistor according to claim 1, wherein: the right end N of the epitaxial layer + The doping concentration of the region (10) is 1 x 10 18 cm -3 ～1×10 20 cm -3 The length is 0.2-0.6 μm, and the distance from the epitaxial drain (11) is 0.2-0.5 μm.
8. A method of fabricating the junction accumulation layer enhanced AlGaN/GaN high electron mobility transistor according to claim 1, comprising the steps of:
step 1: preparing a substrate (1) from a semiconductor material;
step 2: growing a GaN layer (2) on a substrate (1);
and 3, step 3: forming an AlGaN layer (4) on the GaN layer (2) by heteroepitaxy;
and 4, step 4: calculating the length of the right half AlGaN layer (4) according to the optimal breakdown voltage of the device obtained through simulation, and then etching off part of the AlGaN layer (4) in the middle area through a plasma etching method, thereby forming a left half AlGaN layer (4) and a right half AlGaN layer (4);
and 5: a Schottky gate (5) is formed on the upper surface of the right side of the left half AlGaN layer (4);
step 6: growing accumulation dielectric layers (8) on the right side of the AlGaN layer (4) of the left half part, the left side of the AlGaN layer (4) of the right half part and the region between the upper surfaces of the GaN layers (2), and the upper surfaces of the AlGaN layer (4) of the left half part and the AlGaN layer (4) of the right half part;
and 7: further growing an epitaxial layer (9) on the accumulation medium layer (8), etching the epitaxial layer (9) above the AlGaN layer (4) in the left half part and above the rightmost side of the GaN layer (2), and forming P at the left side end and the right side end of the epitaxial layer (9) by ion implantation + Region (6) and N + A zone (10);
and 8: on the upper surface of the epitaxial layer (9) corresponding to P + Depositing metal at the position of the region (6) to form an epitaxial gate (7), depositing metal on the upper surface of the rightmost end of the epitaxial layer to form an epitaxial drain (11), and depositing metal above the leftmost end and the rightmost end of the upper surface of the GaN layer (2) to form an ohmic source (3) and an ohmic drain (12);
and step 9: connecting the ohmic drain (12) with the epitaxial drain (11) to form the drain of the whole device; the Schottky gate (5) is connected with the epitaxial gate (7) through a lead to form a gate of the whole device;
step 10: and forming a passivation layer on the surface of the device.
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| GB2482308A (en) * | 2010-07-28 | 2012-02-01 | Univ Sheffield | Super junction silicon devices |
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| JPH07130996A (en) * | 1993-06-30 | 1995-05-19 | Toshiba Corp | High-breakdown-strength semiconductor element |
| CN102082176A (en) * | 2010-12-03 | 2011-06-01 | 中山大学 | Gallium nitride (GaN) enhancement type metal insulator semiconductor field effect transistor (MISFET) device and manufacturing method thereof |
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