JPH07130996A - High-breakdown-strength semiconductor element - Google Patents

High-breakdown-strength semiconductor element

Info

Publication number
JPH07130996A
JPH07130996A JP5188855A JP18885593A JPH07130996A JP H07130996 A JPH07130996 A JP H07130996A JP 5188855 A JP5188855 A JP 5188855A JP 18885593 A JP18885593 A JP 18885593A JP H07130996 A JPH07130996 A JP H07130996A
Authority
JP
Japan
Prior art keywords
semiconductor layer
type
layer
gate
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5188855A
Other languages
Japanese (ja)
Other versions
JP3400025B2 (en
Inventor
Ichiro Omura
一郎 大村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
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Filing date
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Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP18885593A priority Critical patent/JP3400025B2/en
Publication of JPH07130996A publication Critical patent/JPH07130996A/en
Application granted granted Critical
Publication of JP3400025B2 publication Critical patent/JP3400025B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
    • H01L29/7821—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To obtain a high-breakdown-strength semiconductor element whose ON-voltage is low by installing a gate-semiconductor-layer control means which electrically isolates a gate semiconductor layer from a drain electrode in an ON-operation on the basis of the potential difference between a gate electrode coming into contact with the gate semiconductor layer and the drain electrode. CONSTITUTION:A heavily doped p-type semiconductor layer 10 which does not come into contact with a source electrode 6 is formed on a gate insulating film 8 at the upper part of a P-type well layer 3 in a region which is sandwiched between an n-type source layer 4 and an n-type high-resistance semiconductor layer 2. In addition, a gate electrode 13 is formed. On the end part of the gate insulating film 8 on the drain side, a Zener diode which is composed of an n-type semiconductor layer 11 and a p-type semiconductor layer 12 as a gate semiconductor control means is formed. Then, the p-type semiconductor layer 12 comes into contact with a drain electrode 7. In addition, a low-concentration i-type polysilicon layer 9 is formed on the insulating film 8 between the p-type semiconductor layer 10.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、高耐圧半導体素子に係
り、特にＭＯＳ構造を有する高耐圧半導体素子に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage semiconductor element, and more particularly to a high breakdown voltage semiconductor element having a MOS structure.

【０００２】[0002]

【従来の技術】近年、コンピュータや通信機器の重要部
分には、多数のトランジスタや抵抗等を電気回路を達成
するようにむすびつけ、１チップ上に集積化して形成し
た集積回路（ＩＣ）が多用されている。このようなＩＣ
中で、高耐圧素子を含むものはパワーＩＣと呼ばれてい
る。2. Description of the Related Art In recent years, an integrated circuit (IC) formed by integrating a large number of transistors, resistors and the like so as to achieve an electric circuit and forming them on one chip has been widely used in important parts of computers and communication equipment. ing. IC like this
Among them, a device including a high breakdown voltage element is called a power IC.

【０００３】図２６は、高耐圧素子の一つである横型Ｍ
ＯＳＦＥＴの素子断面図である。図中、１０１はｐ型シ
リコン基板を示し、このｐ型シリコン基板１０１上には
ｎ型高抵抗半導体層１０２が設けられ、その表面にはチ
ャネル形成用のｐ型ウェル層１０３が形成されている。
ｐ型ウェル層１０３の表面にはｎ型ソース層１０４が選
択的に形成されている。ｎ型ソース層１０４からｐ型ウ
ェル層１０３にまたがる領域にはソース電極１０６が設
けられている。FIG. 26 shows a horizontal type M which is one of high breakdown voltage elements.
It is an element sectional view of OSFET. In the figure, 101 indicates a p-type silicon substrate, an n-type high resistance semiconductor layer 102 is provided on the p-type silicon substrate 101, and a p-type well layer 103 for forming a channel is formed on the surface thereof. .
An n-type source layer 104 is selectively formed on the surface of the p-type well layer 103. A source electrode 106 is provided in a region extending from the n-type source layer 104 to the p-type well layer 103.

【０００４】ｎ型高抵抗半導体層１０２の表面にはｎ型
ドレイン層１０５が選択的に形成され、このｎ型ドレイ
ン層１０５にはドレイン電極１０７が設けられている。
ｎ型高抵抗半導体層１０２とｎ型ソース層１０４とで挟
まれた領域のｐ型ウェル層１０３上には、シリコン酸化
膜からなるゲート絶縁膜１０８を介してゲート電極１０
９が設けられている。An n-type drain layer 105 is selectively formed on the surface of the n-type high resistance semiconductor layer 102, and a drain electrode 107 is provided on the n-type drain layer 105.
On the p-type well layer 103 in the region sandwiched between the n-type high resistance semiconductor layer 102 and the n-type source layer 104, the gate electrode 10 is formed with a gate insulating film 108 made of a silicon oxide film interposed therebetween.
9 is provided.

【０００５】横型ＭＯＳＦＥＴは、各電極間の容量を小
さくできるので、特に高速なスイッチングが可能という
利点がある。しかし、従来の横型ＭＯＳＦＥＴには次の
ような問題があった。すなわち、オン状態では、ゲート
電極１０９の下部にしかチャネルｃｈが形成されず、ｎ
型高抵抗半導体層１０２の抵抗によって、オン電圧が高
くなるという問題があった。特に高耐圧素子ではオン電
圧が著しく高いため、ＭＯＳＦＥＴは用いられない。Since the lateral MOSFET can reduce the capacitance between the electrodes, it has an advantage that particularly high-speed switching is possible. However, the conventional lateral MOSFET has the following problems. That is, in the ON state, the channel ch is formed only under the gate electrode 109, and n
There is a problem that the on-voltage is increased due to the resistance of the high-resistance semiconductor layer 102. In particular, MOSFETs are not used in high breakdown voltage devices because the on-voltage is extremely high.

【０００６】図２７は、上記問題を解決するために提案
された横型ＭＯＳＦＥＴの構造を示す素子断面図であ
る。この横型ＭＯＳＦＥＴが図２６のそれと異なる点
は、ゲート電極１０９ａがｎ型ドレイン層１０５上まで
延在していることにある。このため、オン状態では、ｎ
型ソース層１０４からｎ型ドレイン層１０５までの表面
にチャネルが形成され、オン電圧は低くなる。FIG. 27 is a cross-sectional view of an element showing the structure of a lateral MOSFET proposed to solve the above problem. This lateral MOSFET differs from that of FIG. 26 in that the gate electrode 109 a extends up to the n-type drain layer 105. Therefore, in the ON state, n
A channel is formed on the surface from the type source layer 104 to the n-type drain layer 105, and the on-voltage becomes low.

【０００７】しかしながら、オフ状態でゲート・ドレイ
ン間の電圧が高くなると、ゲート電極１０９ａのドレイ
ン端部１１０に電界が集中し、その部分の耐圧が低下す
るという問題があった。However, when the voltage between the gate and the drain is increased in the off state, the electric field is concentrated on the drain end portion 110 of the gate electrode 109a, and the breakdown voltage of that portion is lowered.

【０００８】[0008]

【発明が解決しようとする課題】上述の如く、従来の横
型ＭＯＳＦＥＴの場合、ゲート電極が（チャネル方向
に）短いと、オン電圧が高くなるという問題があった。
また、オン電圧を下げるためにゲート電極を長くする
と、オフ状態で、ゲート電極のドレイン端部に電界が集
中し、耐圧が低下するという問題があった。本発明は、
上記事情を考慮してなされたもので、その目的とすると
ころは、オン電圧が低く、耐圧が高い高耐圧半導体素子
を提供することにある。As described above, the conventional lateral MOSFET has a problem that the ON voltage becomes high when the gate electrode is short (in the channel direction).
Further, if the gate electrode is lengthened in order to lower the on-voltage, there is a problem that the electric field is concentrated at the drain end of the gate electrode in the off state, and the breakdown voltage is lowered. The present invention is
The present invention has been made in view of the above circumstances, and an object thereof is to provide a high breakdown voltage semiconductor element having a low on-voltage and a high breakdown voltage.

【０００９】[0009]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明の高耐圧半導体素子は、第１導電型半導体
基板上に設けられた第２導電型高抵抗半導体層と、この
第２導電型高抵抗半導体層の表面に選択的に形成された
第１導電型半導体層と、この第１導電型半導体層の表面
に選択的に形成された第２導電型ソース層と、前記第２
導電型高抵抗半導体層の表面に選択的に形成された第２
導電型ドレイン層と、前記第２導電型ドレイン層に接す
るドレイン電極と、前記第１導電型半導体層及び前記第
２導電型ソース層に接するソース電極と、前記第２導電
型ソース層と前記第２導電型ドレイン層とで挟まれた前
記第１導電型半導体層と前記第２導電型高抵抗半導体層
との上に、ゲート絶縁膜を介して設けられ、前記ソース
電極と接しないゲート半導体層と、前記第２導電型ソー
ス層と前記第２導電型高抵抗半導体層とで挟まれた前記
第１導電型半導体層上の前記ゲート半導体層に接するゲ
ート電極と、前記ドレイン電極と前記ゲート電極との電
位差に基づいて、オン時に前記ゲート半導体層と前記ド
レイン電極とを電気的に分離するゲート半導体層制御手
段とを備えたことを特徴とする。In order to achieve the above object, a high breakdown voltage semiconductor device of the present invention comprises a second conductivity type high resistance semiconductor layer provided on a first conductivity type semiconductor substrate and a second conductivity type high resistance semiconductor layer. A first conductive type semiconductor layer selectively formed on the surface of the second conductive type high resistance semiconductor layer; a second conductive type source layer selectively formed on the surface of the first conductive type semiconductor layer; Two
The second selectively formed on the surface of the conductive type high resistance semiconductor layer
A conductive type drain layer, a drain electrode in contact with the second conductive type drain layer, a source electrode in contact with the first conductive type semiconductor layer and the second conductive type source layer, the second conductive type source layer and the second conductive type drain layer. A gate semiconductor layer provided on the first conductive type semiconductor layer and the second conductive type high resistance semiconductor layer sandwiched by a two conductive type drain layer with a gate insulating film interposed therebetween and not in contact with the source electrode. A gate electrode in contact with the gate semiconductor layer on the first conductivity type semiconductor layer sandwiched between the second conductivity type source layer and the second conductivity type high resistance semiconductor layer, the drain electrode and the gate electrode And a gate semiconductor layer control means for electrically separating the gate semiconductor layer and the drain electrode from each other based on a potential difference between the gate semiconductor layer and the drain electrode.

【００１０】[0010]

【作用】本発明によれば、オン時に、ゲート絶縁膜側の
ゲート半導体層の表面にチャネルが形成され、ゲート半
導体層の抵抗が著しく低下し、ゲート半導体層の電位は
ゲート印加電圧と同じになる。このため、第１導電型半
導体層から第２導電型高抵抗半導体層の表面にわたって
チャネルが形成される。According to the present invention, when turned on, a channel is formed on the surface of the gate semiconductor layer on the side of the gate insulating film, the resistance of the gate semiconductor layer is significantly reduced, and the potential of the gate semiconductor layer becomes equal to the gate applied voltage. Become. Therefore, a channel is formed from the first conductivity type semiconductor layer to the surface of the second conductivity type high resistance semiconductor layer.

【００１１】すなわち、第２導電型ソース層から第２導
電型ドレイン層に向かって、従来よりも長いチャネルが
形成され、実効的に長いゲート電極が形成された場合と
同じ状態になる。したがって、オン電圧が低下する。ま
た、ゲート半導体層制御手段によって、オン状態のとき
のドレイン電極からゲート半導体層への電流の流れ込み
は生じない。That is, a channel longer than the conventional one is formed from the second-conductivity-type source layer toward the second-conductivity-type drain layer, which is the same state as when an effectively longer gate electrode is formed. Therefore, the on-voltage decreases. Further, the gate semiconductor layer control means does not cause a current to flow from the drain electrode to the gate semiconductor layer in the ON state.

【００１２】一方、オフ時には、ゲート半導体層の表面
のチャネルが消滅し、上記実効的に長いゲート電極が消
滅することになる。また、ゲート半導体層が空乏化する
ことにより、ゲート電極のドレイン端部の耐圧低下は生
じない。On the other hand, when turned off, the channel on the surface of the gate semiconductor layer disappears, and the effectively long gate electrode disappears. In addition, since the gate semiconductor layer is depleted, the breakdown voltage at the drain end of the gate electrode does not decrease.

【００１３】[0013]

【実施例】以下、図面を参照しながら実施例を説明す
る。図１は、本発明の第１の実施例に係る横型ＭＯＳＦ
ＥＴのオン状態の様子を示す素子断面図である。また、
図２は、オフ状態の様子を示す素子断面図である。図
中、１はｐ型シリコン基板を示し、このｐ型シリコン基
板１上にはｎ型高抵抗半導体層２が設けられ、その表面
にはチャネル形成用のｐ型ウェル層３が形成されてい
る。Embodiments will be described below with reference to the drawings. FIG. 1 shows a lateral MOSF according to a first embodiment of the present invention.
It is an element cross-sectional view showing a state of an ET on state. Also,
FIG. 2 is a cross-sectional view of an element showing a state of the off state. In the figure, 1 indicates a p-type silicon substrate, an n-type high resistance semiconductor layer 2 is provided on the p-type silicon substrate 1, and a p-type well layer 3 for forming a channel is formed on the surface thereof. .

【００１４】ｐ型ウェル層３の表面にはｎ型ソース層４
が選択的に形成され、このｎ型ソース層４からｐ型ウェ
ル層３にまたがる領域にはソース電極６が設けられてい
る。ｎ型高抵抗半導体層２の表面にはｎ型ドレイン層５
が選択的に形成され、このｎ型ドレイン層５にはドレイ
ン電極７が設けられている。ソース電極６とドレイン電
極７との間の領域上には、シリコン酸化膜からなるゲー
ト絶縁膜８が設けられている。ｎ型ソース層４とｎ型高
抵抗半導体層２とで挟まれた領域のｐ型ウェル層３の上
方に当たるゲート絶縁膜８上には、ソース電極６と接し
ない高濃度のｐ型半導体層１０が設けられ、このｐ型半
導体層１０にはゲート電極１３が設けられている。An n-type source layer 4 is formed on the surface of the p-type well layer 3.
Are selectively formed, and a source electrode 6 is provided in a region extending from the n-type source layer 4 to the p-type well layer 3. An n-type drain layer 5 is formed on the surface of the n-type high resistance semiconductor layer 2.
Are selectively formed, and a drain electrode 7 is provided on the n-type drain layer 5. A gate insulating film 8 made of a silicon oxide film is provided on the region between the source electrode 6 and the drain electrode 7. A high-concentration p-type semiconductor layer 10 that is not in contact with the source electrode 6 is formed on the gate insulating film 8 above the p-type well layer 3 in a region sandwiched between the n-type source layer 4 and the n-type high resistance semiconductor layer 2. The gate electrode 13 is provided on the p-type semiconductor layer 10.

【００１５】ドレイン側のゲート絶縁膜８の端部上には
ｎ型半導体層１１とｐ型半導体層１２とからなるツェナ
ーダイオードが設けられている。ｐ型半導体層１２はド
レイン電極７に接している。ｐ型半導体層１０とｎ型半
導体層１１との間のゲート絶縁膜８上には、不純物濃度
の低いｉ型ポリシリコン層９が設けられている。なお、
ポリシリコンの代わりにシリコンを用いても良い。A Zener diode composed of an n-type semiconductor layer 11 and a p-type semiconductor layer 12 is provided on the end of the gate insulating film 8 on the drain side. The p-type semiconductor layer 12 is in contact with the drain electrode 7. An i-type polysilicon layer 9 having a low impurity concentration is provided on the gate insulating film 8 between the p-type semiconductor layer 10 and the n-type semiconductor layer 11. In addition,
Silicon may be used instead of polysilicon.

【００１６】このように構成された横型ＭＯＳＦＥＴに
よれば、ゲート電極１３にソース電極６に対して正の電
圧を印加すると、ｐ型半導体層１０の下部のｐ型ウェル
層３の表面にチャネルｃｈ１が形成されると同時にｉ型
ポリシリコン層９の表面にチャネルｃｈ２が誘起され
る。この結果、ｉ型ポリシリコン層９の抵抗が著しく低
下し、ｉ型ポリシリコン層９の電位はゲート印加電圧と
同じになる。このため、ｎ型高抵抗半導体層２の表面に
チャネルｃｈ３が形成される。According to the lateral MOSFET thus configured, when a positive voltage is applied to the gate electrode 13 with respect to the source electrode 6, the channel ch1 is formed on the surface of the p-type well layer 3 below the p-type semiconductor layer 10. The channel ch2 is induced on the surface of the i-type polysilicon layer 9 at the same time that the channel is formed. As a result, the resistance of the i-type polysilicon layer 9 is significantly reduced, and the potential of the i-type polysilicon layer 9 becomes the same as the gate applied voltage. Therefore, the channel ch3 is formed on the surface of the n-type high resistance semiconductor layer 2.

【００１７】したがって、ｎ型ソース層４とｎ型ドレイ
ン層５とは一つのチャネルで繋がるようになる。すなわ
ち、図２７に示した横型ＭＯＳＦＥＴのように、実効的
に長いゲート電極１０９ａが形成された場合と同じよう
に、長いチャネルが形成される。したがって、ｎ型ソー
ス層４、ｎ型ドレイン層５がｎ型高抵抗半導体層２の表
面に形成されていても、オン電圧を低くできる。また、
このとき、ｎ型半導体層１１とｐ型半導体層１２とで形
成されるダイオードは逆バイアスされるので、ドレイン
電極７からｉ型ポリシリコン層９に電流が流れる込むと
いう不都合は生じない。Therefore, the n-type source layer 4 and the n-type drain layer 5 are connected by one channel. That is, like the lateral MOSFET shown in FIG. 27, a long channel is formed as in the case where the effectively long gate electrode 109a is formed. Therefore, even if the n-type source layer 4 and the n-type drain layer 5 are formed on the surface of the n-type high resistance semiconductor layer 2, the on-voltage can be lowered. Also,
At this time, the diode formed by the n-type semiconductor layer 11 and the p-type semiconductor layer 12 is reverse-biased, so that there is no inconvenience that a current flows from the drain electrode 7 to the i-type polysilicon layer 9.

【００１８】一方、オフ時には、ゲート電極１３には電
圧は印加されず、ドレイン電極７には高電圧が印加され
るため、図２に示すように、ｐ型ウェル層３の表面にチ
ャネルｃｈ１は形成されない。この結果、チャネルｃｈ
２，ｃｈ３は誘起されず、ｉ型ポリシリコン層９は空乏
化する。すなわち、図２７に示した横型ＭＯＳＦＥＴの
ような、実効的に長いゲート電極１０９ａは消滅する。
したがって、ドレイン電極７の近傍の電界集中が回避さ
れ、ｎ型ドレイン電極７の近傍の耐圧低下は生じない。On the other hand, when turned off, no voltage is applied to the gate electrode 13 and a high voltage is applied to the drain electrode 7, so that the channel ch1 is formed on the surface of the p-type well layer 3 as shown in FIG. Not formed. As a result, channel ch
2 and ch3 are not induced and the i-type polysilicon layer 9 is depleted. That is, the effectively long gate electrode 109a like the lateral MOSFET shown in FIG. 27 disappears.
Therefore, the electric field concentration near the drain electrode 7 is avoided, and the breakdown voltage does not decrease near the n-type drain electrode 7.

【００１９】したがって、本実施例によれば、オン電圧
が低く、耐圧が高い横型ＭＯＳＦＥＴが得られる。図３
は、本発明の第２の実施例に係る横型ＭＯＳＦＥＴのオ
ン状態の様子を示す素子断面図である。なお、以下の図
３〜図９において、前出した図と同一符号（添字が異な
るものを含む）は同一部分または相当部分を示す。Therefore, according to this embodiment, a lateral MOSFET having a low on-voltage and a high breakdown voltage can be obtained. Figure 3
FIG. 6 is an element cross-sectional view showing an on-state of a lateral MOSFET according to a second example of the present invention. In FIGS. 3 to 9 below, the same reference numerals (including those with different subscripts) as in the above-mentioned drawings indicate the same or corresponding portions.

【００２０】本実施例の横型ＭＯＳＦＥＴは、先の実施
例のそれをＳＯＩ構造としたものである。シリコン基板
１ａ上には埋め込みシリコン酸化膜１０が形成され、シ
リコン酸化膜１０が上には薄いｎ型高抵抗半導体層２ａ
が形成されている。また、ｎ型高抵抗半導体層２ａには
シリコン酸化膜１０に達するｐ型ウェル層３ａが形成さ
れている。その他の構造は先の実施例と同じである。The lateral MOSFET of this embodiment has the SOI structure of that of the previous embodiment. A buried silicon oxide film 10 is formed on a silicon substrate 1a, and a thin n-type high resistance semiconductor layer 2a is formed on the silicon oxide film 10.
Are formed. A p-type well layer 3a reaching the silicon oxide film 10 is formed in the n-type high resistance semiconductor layer 2a. The other structure is the same as that of the previous embodiment.

【００２１】このように構成された横型ＭＯＳＦＥＴで
も、先の実施例と同様な効果が得られるのは勿論のこ
と、更に、オン電圧が低く、ＳＯＩ構造により素子の接
合容量が小さくなるので、高速なスイッチングが行なえ
るようになる。図４は、本発明の第３の実施例に係るＭ
ＯＳＦＥＴの構造を示す素子断面図である。In the lateral MOSFET thus constructed, the same effect as in the previous embodiment can be obtained, and further, since the on-state voltage is low and the SOI structure reduces the junction capacitance of the element, the high speed is achieved. It becomes possible to perform the switching. FIG. 4 shows the M according to the third embodiment of the present invention.
It is an element sectional view showing a structure of OSFET.

【００２２】これは本発明をトレンチ溝を用いたＭＯＳ
ＦＥＴに適用した例である。通常、トレンチ溝内にゲー
ト電極を設けた素子の場合、トレンチ溝の下端部分で電
界集中が生じ、その部分の耐圧が劣化するという問題が
ある。しかし、本実施例によれば、ｉ型ポリシリコン層
９が空乏化し、トレンチ溝の下端部分での電界集中が緩
和するので、耐圧が改善される。This is because the present invention is a MOS using a trench groove.
This is an example applied to a FET. Usually, in the case of an element in which a gate electrode is provided in the trench groove, there is a problem that electric field concentration occurs at the lower end portion of the trench groove and the breakdown voltage of that portion deteriorates. However, according to this embodiment, the i-type polysilicon layer 9 is depleted and the electric field concentration at the lower end portion of the trench groove is relaxed, so that the breakdown voltage is improved.

【００２３】図５は、本発明の第４の実施例に係る横型
ＭＯＳＦＥＴの構造を示す素子断面図である。本実施例
の横型ＭＯＳＦＥＴが第２の実施例のそれと異なる点
は、ゲート電極１０とドレイン電極７との間の半導体層
９，１０，１１，１２の表面がポリシリコン高抵抗膜
（ＳＩＰＯＳ）１５で被覆されていることにある。FIG. 5 is an element cross-sectional view showing the structure of a lateral MOSFET according to the fourth embodiment of the present invention. The lateral MOSFET of this embodiment is different from that of the second embodiment in that the surface of the semiconductor layers 9, 10, 11, 12 between the gate electrode 10 and the drain electrode 7 is a polysilicon high resistance film (SIPOS) 15. It is covered with.

【００２４】このように構成された横型ＭＯＳＦＥＴに
よれば、ポリシリコン高抵抗膜１５によって、オフ時に
ｉ型ポリシリコン層９内を流れる微小電流によるｎ型高
抵抗半導体層２ａ内の電界の変動を抑制でき、更に耐圧
が向上する。図６は、本発明の第５の実施例に係る横型
ＭＯＳＦＥＴの構造を示す素子断面図である。According to the lateral MOSFET having the above structure, the polysilicon high resistance film 15 prevents the electric field in the n type high resistance semiconductor layer 2a from varying due to a minute current flowing in the i type polysilicon layer 9 when it is turned off. It can be suppressed and the breakdown voltage is further improved. FIG. 6 is an element sectional view showing the structure of the lateral MOSFET according to the fifth embodiment of the present invention.

【００２５】本実施例の横型ＭＯＳＦＥＴが第２の実施
例のそれと異なる点は、低不純物濃度のｉ型ポリシリコ
ン層９の代わりに、ｐ型ポリシリコン層９ａ（他の半導
体材料でも良い）を用いたことにある。通常、ｎ型高抵
抗半導体層２ａが薄い（２μｍ以下）場合には、ｎ型高
抵抗半導体層２ａの不純物濃度は、耐圧の関係上、ある
程度の値（ドーズ量１．５×１０12／ｃｍ2 ）以上にで
きない。The lateral MOSFET of this embodiment is different from that of the second embodiment in that a p-type polysilicon layer 9a (other semiconductor material may be used) instead of the i-type polysilicon layer 9 having a low impurity concentration. I used it. Usually, when the n-type high-resistance semiconductor layer 2a is thin (2 μm or less), the impurity concentration of the n-type high-resistance semiconductor layer 2a has a certain value (dose amount 1.5 × 10 12 / cm 3) due to the breakdown voltage. 2 ) You can't do more.

【００２６】しかし、本実施例によれば、オフ時の空乏
化によって生じるｐ型ポリシリコン層９ａ内の負電荷と
ｎ型高抵抗半導体層２ａ内の正電荷とが互いに打ち消し
合うため、ｎ型高抵抗半導体層２ａの不純物濃度を高く
できる。したがって、オン電圧が更に低くなる。図７
は、本発明の第６の実施例に係る横型ＭＯＳＦＥＴの構
造を示す素子断面図である。However, according to this embodiment, the negative charges in the p-type polysilicon layer 9a and the positive charges in the n-type high-resistance semiconductor layer 2a, which are generated by depletion at the time of turning off, cancel each other out, so that the n-type The impurity concentration of the high resistance semiconductor layer 2a can be increased. Therefore, the on-voltage becomes even lower. Figure 7
[FIG. 11A] is an element cross-sectional view showing the structure of a lateral MOSFET according to a sixth embodiment of the present invention.

【００２７】本実施例の横型ＭＯＳＦＥＴが第２の実施
例のそれと異なる点は、低不純物濃度のｉ型ポリシリコ
ン層９の代わりに、ｎ型ポリシリコン層９ｂ（他の半導
体材料でも良い）を用いたことにある。本実施例によれ
ば、オフ時に、ソース側からドレイン側に向かって、ｎ
型ポリシリコン層９ｂおよびｎ型高抵抗半導体層２ａ内
に空乏層が広がる。このため、ｎ型高抵抗半導体層２ａ
が厚く、縦方向（膜厚方向）の電界が大きくても、ゲー
ト絶縁膜８に高電圧が印加されないので、耐圧を改善で
きる。なお、ｎ型半導体層１１の不純物濃度を高く（１
×１０17〜１０18ｃｍ-3程度以上）し、ゲート絶縁膜８
側のｎ型半導体層１１の表面にチャネルが誘起されるの
を防止することが好ましい。The lateral MOSFET of this embodiment is different from that of the second embodiment in that an n-type polysilicon layer 9b (other semiconductor material may be used) instead of the i-type polysilicon layer 9 having a low impurity concentration. I used it. According to the present embodiment, when off, n from the source side toward the drain side
A depletion layer spreads in the type polysilicon layer 9b and the n-type high resistance semiconductor layer 2a. Therefore, the n-type high resistance semiconductor layer 2a
Since the gate insulating film 8 is thick and the electric field in the vertical direction (the film thickness direction) is large, the high voltage is not applied to the gate insulating film 8, so that the breakdown voltage can be improved. In addition, the impurity concentration of the n-type semiconductor layer 11 is increased (1
X 10 17 to 10 18 cm −3 or more), and the gate insulating film 8
It is preferable to prevent a channel from being induced on the surface of the n-type semiconductor layer 11 on the side.

【００２８】図８は、本発明の第７の実施例に係る横型
ＭＯＳＦＥＴの構造を示す素子断面図である。本実施例
の横型ＭＯＳＦＥＴが第６の実施例のそれと異なる点
は、ｐ型半導体層１２がｎ型ポリシリコン層９ｂの上部
表面に形成されていることにある。図中、１４はドレイ
ン電極７に繋がった電極を示している。FIG. 8 is an element cross-sectional view showing the structure of a lateral MOSFET according to the seventh embodiment of the present invention. The lateral MOSFET of this embodiment differs from that of the sixth embodiment in that the p-type semiconductor layer 12 is formed on the upper surface of the n-type polysilicon layer 9b. In the figure, 14 indicates an electrode connected to the drain electrode 7.

【００２９】本実施例によれば、ゲート絶縁膜８側のｎ
型ポリシリコン層９ｂの表面にチャネルが誘起されて
も、ｐ型半導体層１２は上記チャネルと繋がらないの
で、チャネルストッパ層が不要になる。図９は、本発明
の第８の実施例に係る横型ＭＯＳＦＥＴの構造を示す素
子断面図である。According to this embodiment, n on the gate insulating film 8 side is
Even if a channel is induced on the surface of the type polysilicon layer 9b, the p-type semiconductor layer 12 is not connected to the channel, so that the channel stopper layer becomes unnecessary. FIG. 9 is an element cross-sectional view showing the structure of the lateral MOSFET according to the eighth embodiment of the present invention.

【００３０】本実施例の横型ＭＯＳＦＥＴが第７の実施
例のそれと異なる点は、ｐ型半導体層１２を無くし、電
極１４が直接ｎ型ポリシリコン層９ｂの上部表面に接す
るようになっていることにある。本実施例によれば、電
極１４とｎ型ポリシリコン層９ｂとによりショットキー
接合が形成され、これによりダイオードが形成されるの
で、ｐ型半導体層１２が無くても先の実施例と同様な効
果が得られる。The lateral MOSFET of this embodiment is different from that of the seventh embodiment in that the p-type semiconductor layer 12 is eliminated and the electrode 14 is in direct contact with the upper surface of the n-type polysilicon layer 9b. It is in. According to the present embodiment, since the Schottky junction is formed by the electrode 14 and the n-type polysilicon layer 9b and the diode is formed by this, the same as in the previous embodiment without the p-type semiconductor layer 12. The effect is obtained.

【００３１】以上の実施例は、横型ＩＧＢＴにも適用で
き、その横型ＩＧＢＴの構造は、図１，図３，図５，図
６，図７，図８，図９に対応して、それぞれ、図２８，
図２９，図３０，図３１，図３２，図３３，図３４の如
きになり、上記実施例と同様な効果が得られる。なお、
各図中の１６はＩＧＢＴを構成するｐ型半導体層を示し
ている。The above embodiment can be applied to a lateral IGBT, and the structure of the lateral IGBT corresponds to FIG. 1, FIG. 3, FIG. 5, FIG. 6, FIG. 7, FIG. 8 and FIG. 28,
29, FIG. 30, FIG. 31, FIG. 32, FIG. 33, and FIG. 34, the same effects as those of the above embodiment can be obtained. In addition,
Reference numeral 16 in each figure denotes a p-type semiconductor layer that constitutes the IGBT.

【００３２】図１０は、本発明の第９の実施例に係る横
型ＭＯＳＦＥＴの平面図である。また、図１１、図１２
は、それぞれ、図１０の横型ＭＯＳＦＥＴのＡ−Ａ´断
面図、Ｂ−Ｂ´断面図である。なお、以下の図１０〜図
２４において、前出した図と同一符号（添字が異なるも
のを含む）は同一部分または相当部分を示す。これを製
造工程に従い説明すると、まず、シリコン基板２１にシ
リコン酸化膜２２を埋め込み形成する。次いでシリコン
酸化膜２２上にｎ型半導体層３１を形成し、このｎ型半
導体層３１にシリコン酸化膜２２に達するｐ型ウェル層
２４を選択的に形成する。このとき、ｐ型ウェル層２４
とチャネル形成部分４２とソース電極２７とのコンタク
ト部４１を残しておく。FIG. 10 is a plan view of a lateral MOSFET according to the ninth embodiment of the present invention. Also, FIG. 11 and FIG.
11A and 11B are respectively an AA ′ sectional view and a BB ′ sectional view of the lateral MOSFET of FIG. 10. Note that, in FIGS. 10 to 24 below, the same reference numerals (including those with different subscripts) as in the above-mentioned drawings indicate the same or corresponding portions. This will be described according to the manufacturing process. First, the silicon oxide film 22 is embedded and formed in the silicon substrate 21. Next, the n-type semiconductor layer 31 is formed on the silicon oxide film 22, and the p-type well layer 24 reaching the silicon oxide film 22 is selectively formed on the n-type semiconductor layer 31. At this time, the p-type well layer 24
The contact portion 41 between the channel forming portion 42 and the source electrode 27 is left.

【００３３】次にｐ型ウェル層２４内にシリコン酸化膜
２２に達するストライプ状のｎ型ソース層２５を形成す
るとともに、ｎ型半導体層３１内にシリコン酸化膜２２
に達するストライプ状のｎ型ドレイン層２６を形成す
る。次にｎ型ソース層２５とｎ型ドレイン層２６とで挟
まれた領域にシリコン酸化膜２２に達するストライプ状
のｐ型半導体層３２を形成する。このストライプの方向
はｎ型ソース層２５（ｎ型ドレイン層２６）のそれと直
角である。Next, a stripe-shaped n-type source layer 25 reaching the silicon oxide film 22 is formed in the p-type well layer 24, and the silicon oxide film 22 is formed in the n-type semiconductor layer 31.
To form a stripe-shaped n-type drain layer 26. Next, a stripe-shaped p-type semiconductor layer 32 reaching the silicon oxide film 22 is formed in a region sandwiched by the n-type source layer 25 and the n-type drain layer 26. The direction of this stripe is perpendicular to that of the n-type source layer 25 (n-type drain layer 26).

【００３４】次にｐ型ウェル層２４上にゲート絶縁膜２
９を形成した後、このゲート絶縁膜２９上にゲート電極
３０を形成する。最後に、ｎ型ソース層２５に接するソ
ース電極２７、ｎ型ドレイン層２６に接するドレイン電
極２８を形成する。なお、製造工程の順序は上記のもの
に限定されるものではない。Next, the gate insulating film 2 is formed on the p-type well layer 24.
After forming 9, the gate electrode 30 is formed on the gate insulating film 29. Finally, a source electrode 27 in contact with the n-type source layer 25 and a drain electrode 28 in contact with the n-type drain layer 26 are formed. The order of manufacturing steps is not limited to the above.

【００３５】以上述べた方法により得られる横型ＭＯＳ
ＦＥＴによれば、ｎ型半導体層３１の濃度を上げても、
オフ時の空乏化によってｎ型半導体層３１内に生じる正
電荷は、ｐ型半導体層３２内に生じる負電荷によって打
ち消されるので、耐圧は改善される。一方、図２４に示
す従来の横型ＭＯＳＦＥＴの場合には、図２５に示すよ
うに、ｎ型半導体層２３の単位面積当り不純物濃度が１
×１０12ｃｍ-2を越えると、耐圧は急激に低下する。Lateral MOS obtained by the method described above
According to the FET, even if the concentration of the n-type semiconductor layer 31 is increased,
The positive charge generated in the n-type semiconductor layer 31 due to depletion at the time of off is canceled by the negative charge generated in the p-type semiconductor layer 32, so that the breakdown voltage is improved. On the other hand, in the case of the conventional lateral MOSFET shown in FIG. 24, the impurity concentration per unit area of the n-type semiconductor layer 23 is 1 as shown in FIG.
When it exceeds × 10 12 cm -2 , the breakdown voltage drops sharply.

【００３６】したがって、本実施例によれば、耐圧の低
下を招くこと無く、ｎ型半導体層３１の濃度を上げるこ
とができるので、オン抵抗を低くできる。図１３、図１
４は、本発明の第１０の実施例に係る横型ＭＯＳＦＥＴ
の素子断面図で、それぞれ、図１１、図１２に対応する
ものである。本実施例の横型ＭＯＳＦＥＴが先の実施例
のそれと異なる点は、厚いｎ型半導体層３１に素子を形
成したことにある。このため、ｐ型ウェル層２４、ｎ型
ソース層２５、ｎ型ドレイン層２６、ｎ型半導体層３
１、ｐ型半導体層３２をシリコン酸化膜２２に達しない
ように形成できる。Therefore, according to this embodiment, since the concentration of the n-type semiconductor layer 31 can be increased without lowering the breakdown voltage, the on-resistance can be lowered. 13 and 1
4 is a lateral MOSFET according to the tenth embodiment of the present invention
11 are sectional views of the element corresponding to FIG. 11 and FIG. 12, respectively. The lateral MOSFET of this embodiment is different from that of the previous embodiment in that an element is formed on the thick n-type semiconductor layer 31. Therefore, the p-type well layer 24, the n-type source layer 25, the n-type drain layer 26, and the n-type semiconductor layer 3 are formed.
1. The p-type semiconductor layer 32 can be formed so as not to reach the silicon oxide film 22.

【００３７】図１５〜図２０は、ｎ型半導体層３１、ｐ
型半導体層３２の他の配置パターンを示す図で、いずれ
の配置パターンも、ｎ型半導体層３１の不純物濃度がソ
ース側で低く、ドレイン側で高くなるようになってい
る。このような条件を満たす配置パターンを選んだの
は、上記の如きの濃度勾配があると、ソース・ドレイン
間の耐圧が高くなるという研究報告に基づく（ＩＳＰＳ
Ｄ´９１，ｐ３１，Marchant et al. ）。15 to 20 show n-type semiconductor layers 31, p.
It is a figure which shows the other arrangement | positioning pattern of the type | mold semiconductor layer 32. In each arrangement | positioning pattern, the impurity concentration of the n-type semiconductor layer 31 is low in the source side, and becomes high in the drain side. The reason why the layout pattern satisfying such a condition is selected is based on a research report that the breakdown voltage between the source and the drain becomes high when the above concentration gradient is present (ISPS).
D'91, p31, Marchant et al.).

【００３８】しかし、従来の技術では濃度勾配を形成す
るのに、多数の拡散工程を要し、プロセス上の問題が多
かったが、上記配置パターンのようなものであれば、従
来の問題を回避できる。図１５に示す配置パターンは、
ｐ型半導体層３２の幅をドレインに向かって徐々に細く
することにより、平均的に直線的な濃度勾配が得られ
る。However, in the conventional technique, a large number of diffusion steps were required to form the concentration gradient, and there were many process problems. However, in the case of the above arrangement pattern, the conventional problem can be avoided. it can. The arrangement pattern shown in FIG. 15 is
By gradually narrowing the width of the p-type semiconductor layer 32 toward the drain, an average linear concentration gradient can be obtained.

【００３９】図１６に示す配置パターンは、ｐ型半導体
層３２がｎ型ドレイン層２６に達しないもので、平均的
にソース側とドレイン側とに濃度差を設けている。図１
７に示す配置パターンは、各ｐ型半導体層３２の長さを
変えることにより、図１５に示した配置パターンと同じ
効果を実現するものである。図１５〜図１７の配置パタ
ーンの場合、ｐ型半導体層３２がｐ型ウェル層２４に接
しているため、その接している部分ではチャネルが形成
されず、チャネル幅が短なり、オン電圧が高くなる。The arrangement pattern shown in FIG. 16 is one in which the p-type semiconductor layer 32 does not reach the n-type drain layer 26, and there is an average concentration difference between the source side and the drain side. Figure 1
The arrangement pattern shown in FIG. 7 realizes the same effect as the arrangement pattern shown in FIG. 15 by changing the length of each p-type semiconductor layer 32. In the arrangement patterns of FIGS. 15 to 17, since the p-type semiconductor layer 32 is in contact with the p-type well layer 24, a channel is not formed in the contact portion, the channel width is short, and the on-voltage is high. Become.

【００４０】図１８、図１９に示す配置パターンは、こ
のようなオン電圧の問題を解決できるものである。すな
わち、図１８に示す配置パターンは、ｐ型半導体層３２
とｐ型ウェル層２４とが接しないもので、ｐ型半導体層
３２をいわゆるガードリングのようにフローティングと
することにより、オン電圧を小さくしている。The arrangement patterns shown in FIGS. 18 and 19 can solve such a problem of ON voltage. That is, the arrangement pattern shown in FIG. 18 has the p-type semiconductor layer 32.
And the p-type well layer 24 are not in contact with each other, and the p-type semiconductor layer 32 is floated like a so-called guard ring to reduce the on-voltage.

【００４１】図１９に示す配置パターンは、図１８にお
いて、一本のストライプをより短い複数のストライプに
したものである。図２０に示す配置パターンは、ｐ型半
導体層３２のストライプ方向をｎ型ソース層２５（ｎ型
ドレイン層２６）のそれと同じにし、ｐ型半導体層３２
をガードリング配置としたものである。図２１は、図２
０のＡ−Ａ´断面図である。この配置パターンの場合、
図２０に示すゲート電極３０の下部３３、ドレイン電極
２８の下部３４の電位集中が、従来に比べて十分緩和さ
れ、耐圧が改善される。The arrangement pattern shown in FIG. 19 is obtained by forming one stripe into a plurality of shorter stripes in FIG. In the arrangement pattern shown in FIG. 20, the stripe direction of the p-type semiconductor layer 32 is the same as that of the n-type source layer 25 (n-type drain layer 26), and the p-type semiconductor layer 32 is formed.
Is a guard ring arrangement. FIG. 21 corresponds to FIG.
It is AA 'sectional drawing of 0. For this placement pattern,
The potential concentration in the lower portion 33 of the gate electrode 30 and the lower portion 34 of the drain electrode 28 shown in FIG. 20 is sufficiently relaxed as compared with the conventional case, and the breakdown voltage is improved.

【００４２】図２２、図２３は、図２０の配置パターン
をＩＧＢＴに適用した場合の素子断面図を示し、図２２
はｎ型半導体層２３が厚いＩＧＢＴ、図２３は半導体層
２３が薄いＩＧＢＴの例を示している。なお、図中、３
５は高濃度ｎ型半導体層を示し、３６はｐ型エミッタ層
を示している。22 and 23 are sectional views of elements when the arrangement pattern of FIG. 20 is applied to an IGBT.
Shows an example of an IGBT in which the n-type semiconductor layer 23 is thick, and FIG. 23 shows an example of an IGBT in which the semiconductor layer 23 is thin. In the figure, 3
Reference numeral 5 indicates a high-concentration n-type semiconductor layer, and 36 indicates a p-type emitter layer.

【００４３】[0043]

【発明の効果】以上詳述したように本発明によれば、オ
ン電圧が低く、耐圧が高い高耐圧半導体素子が得られ
る。As described in detail above, according to the present invention, a high breakdown voltage semiconductor element having a low on-voltage and a high breakdown voltage can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の実施例に係る横型ＭＯＳＦＥＴ
のオン状態の様子を示す素子断面図。FIG. 1 is a lateral MOSFET according to a first embodiment of the present invention.
6 is a cross-sectional view of an element showing a state of ON state of FIG.

【図２】図１の横型ＭＯＳＦＥＴのオフ状態の様子を示
す素子断面図。2 is an element cross-sectional view showing a state of the lateral MOSFET of FIG. 1 in an off state.

【図３】本発明の第２の実施例に係る横型ＭＯＳＦＥＴ
のオン状態の様子を示す素子断面図。FIG. 3 is a lateral MOSFET according to a second embodiment of the present invention.
6 is a cross-sectional view of an element showing a state of ON state of FIG.

【図４】本発明の第３の実施例に係るＭＯＳＦＥＴの構
造を示す素子断面図。FIG. 4 is an element sectional view showing a structure of a MOSFET according to a third embodiment of the present invention.

【図５】本発明の第４の実施例に係る横型ＭＯＳＦＥＴ
の構造を示す素子断面図。FIG. 5 is a lateral MOSFET according to a fourth embodiment of the present invention.
3 is a cross-sectional view of an element showing the structure of FIG.

【図６】本発明の第５の実施例に係る横型ＭＯＳＦＥＴ
の構造を示す素子断面図。FIG. 6 is a lateral MOSFET according to a fifth embodiment of the present invention.
3 is a cross-sectional view of an element showing the structure of FIG.

【図７】本発明の第６の実施例に係る横型ＭＯＳＦＥＴ
の構造を示す素子断面図。FIG. 7 is a lateral MOSFET according to a sixth embodiment of the present invention.
3 is a cross-sectional view of an element showing the structure of FIG.

【図８】本発明の第７の実施例に係る横型ＭＯＳＦＥＴ
の構造を示す素子断面図。FIG. 8 is a lateral MOSFET according to a seventh embodiment of the present invention.
3 is a cross-sectional view of an element showing the structure of FIG.

【図９】本発明の第８の実施例に係る横型ＭＯＳＦＥＴ
の構造を示す素子断面図。FIG. 9 is a lateral MOSFET according to an eighth embodiment of the present invention.
3 is a cross-sectional view of an element showing the structure of FIG.

【図１０】本発明の第９の実施例に係る横型ＭＯＳＦＥ
Ｔの平面図。FIG. 10 is a lateral MOSFE according to a ninth embodiment of the present invention.
The top view of T.

【図１１】図１０の横型ＭＯＳＦＥＴのＡ−Ａ´断面
図。11 is a cross-sectional view taken along the line AA ′ of the lateral MOSFET of FIG.

【図１２】図１０の横型ＭＯＳＦＥＴのＢ−Ｂ´断面
図。12 is a cross-sectional view taken along the line BB ′ of the lateral MOSFET of FIG.

【図１３】本発明の第１０の実施例に係る横型ＭＯＳＦ
ＥＴの素子断面図。FIG. 13 is a lateral MOSF according to a tenth embodiment of the present invention.
The element sectional view of ET.

【図１４】本発明の第１０の実施例に係る横型ＭＯＳＦ
ＥＴの素子断面図。FIG. 14 is a lateral MOSF according to a tenth embodiment of the present invention.
The element sectional view of ET.

【図１５】ｎ型半導体層、ｐ型半導体層の配置パターン
を示す図。FIG. 15 is a diagram showing an arrangement pattern of an n-type semiconductor layer and a p-type semiconductor layer.

【図１６】ｎ型半導体層、ｐ型半導体層の他の配置パタ
ーンを示す図。FIG. 16 is a diagram showing another arrangement pattern of an n-type semiconductor layer and a p-type semiconductor layer.

【図１７】ｎ型半導体層、ｐ型半導体層の他の配置パタ
ーンを示す図。FIG. 17 is a diagram showing another arrangement pattern of an n-type semiconductor layer and a p-type semiconductor layer.

【図１８】ｎ型半導体層、ｐ型半導体層の他の配置パタ
ーンを示す図。FIG. 18 is a diagram showing another arrangement pattern of an n-type semiconductor layer and a p-type semiconductor layer.

【図１９】ｎ型半導体層、ｐ型半導体層の他の配置パタ
ーンを示す図。FIG. 19 is a diagram showing another arrangement pattern of an n-type semiconductor layer and a p-type semiconductor layer.

【図２０】ｎ型半導体層、ｐ型半導体層の他の配置パタ
ーンを示す図。FIG. 20 is a diagram showing another arrangement pattern of an n-type semiconductor layer and a p-type semiconductor layer.

【図２１】図２０のＡ−Ａ´断面図。21 is a cross-sectional view taken along the line AA ′ of FIG.

【図２２】図２０の配置パターンをＩＧＢＴに適用した
例を示す図。22 is a diagram showing an example in which the arrangement pattern of FIG. 20 is applied to an IGBT.

【図２３】図２０の配置パターンをＩＧＢＴに適用した
例を示す図。23 is a diagram showing an example in which the arrangement pattern of FIG. 20 is applied to an IGBT.

【図２４】従来の横型ＭＯＳＦＥＴの素子断面図。FIG. 24 is a device cross-sectional view of a conventional lateral MOSFET.

【図２５】従来の横型ＭＯＳＦＥＴの問題点を説明する
ための特性図。FIG. 25 is a characteristic diagram for explaining problems of the conventional lateral MOSFET.

【図２６】従来の他の横型ＭＯＳＦＥＴの素子断面図。FIG. 26 is a cross-sectional view of another conventional lateral MOSFET device.

【図２７】従来の他の横型ＭＯＳＦＥＴの素子断面図。FIG. 27 is an element cross-sectional view of another conventional lateral MOSFET.

【図２８】図１の横型ＭＯＳＦＥＴの特徴を適用した横
型ＩＧＢＴの素子断面図。28 is an element cross-sectional view of a lateral IGBT to which the characteristics of the lateral MOSFET of FIG. 1 are applied.

【図２９】図３の横型ＭＯＳＦＥＴの特徴を適用した横
型ＩＧＢＴの素子断面図。29 is an element cross-sectional view of a lateral IGBT to which the characteristics of the lateral MOSFET of FIG. 3 are applied.

【図３０】図５の横型ＭＯＳＦＥＴの特徴を適用した横
型ＩＧＢＴの素子断面図。30 is a cross-sectional view of a lateral IGBT device to which the features of the lateral MOSFET of FIG. 5 are applied.

【図３１】図６の横型ＭＯＳＦＥＴの特徴を適用した横
型ＩＧＢＴの素子断面図。31 is an element cross-sectional view of a lateral IGBT to which the characteristics of the lateral MOSFET of FIG. 6 are applied.

【図３２】図７の横型ＭＯＳＦＥＴの特徴を適用した横
型ＩＧＢＴの素子断面図。32 is an element cross-sectional view of a lateral IGBT in which the characteristics of the lateral MOSFET of FIG. 7 are applied.

【図３３】図８の横型ＭＯＳＦＥＴの特徴を適用した横
型ＩＧＢＴの素子断面図。33 is an element cross-sectional view of a lateral IGBT to which the characteristics of the lateral MOSFET of FIG. 8 are applied.

【図３４】図９の横型ＭＯＳＦＥＴの特徴を適用した横
型ＩＧＢＴの素子断面図。34 is an element cross-sectional view of a lateral IGBT in which the characteristics of the lateral MOSFET in FIG. 9 are applied.

【符号の説明】[Explanation of symbols]

１…ｐ型シリコン基板（第１導電型半導体基板）、１ａ
…シリコン基板、２、２ａ…ｎ型高抵抗半導体層（第２
導電型高抵抗半導体層）、３…ｐ型ウェル層（第１導電
型半導体層）、４…ｎ型ソース層（第２導電型ソース
層）、５…ｎ型ドレイン層（第２導電型ドレイン層）、
６…ソース電極、７…ドレイン電極、８…ゲート絶縁
膜、９…ｉ型ポリシリコン層（ゲート半導体層）、９ａ
…ｐ型ポリシリコン層（ゲート半導体層）、９ｂ…ｎ型
ポリシリコン層（ゲート半導体層）、１０…シリコン酸
化膜、１１…ｎ型半導体層（ゲート半導体層制御手
段）、１２…ｐ型半導体層（ゲート半導体層制御手
段）、１３…ゲート電極、１４…電極、１５…ポリシリ
コン高抵抗膜、１６…ｐ型半導体層。２１…シリコン基
板、２２…シリコン酸化膜、２３…ｎ型半導体層、２４
…ｐ型ウェル層、２５…ｎ型ソース層、２６…ｎ型ドレ
イン層、２７…ソース電極、２８…ドレイン電極、２９
…ゲート絶縁膜、３０…ゲート電極、３１…ｎ型半導体
層、３２…ｐ型半導体層、３３…ゲート電極の下部、３
４…ドレイン電極の下部、３５…高濃度ｎ型半導体層、
３６…、３７…、３８…、３９…、４０…、４１…コン
タクト部、４２…チャネル形成部分。1 ... P-type silicon substrate (first conductivity type semiconductor substrate) 1a
... Silicon substrate, 2, 2a ... n-type high resistance semiconductor layer (second
Conductive type high resistance semiconductor layer), 3 ... p type well layer (first conductive type semiconductor layer), 4 ... n type source layer (second conductive type source layer), 5 ... n type drain layer (second conductive type drain) layer),
6 ... Source electrode, 7 ... Drain electrode, 8 ... Gate insulating film, 9 ... i-type polysilicon layer (gate semiconductor layer), 9a
... p-type polysilicon layer (gate semiconductor layer), 9b ... n-type polysilicon layer (gate semiconductor layer), 10 ... silicon oxide film, 11 ... n-type semiconductor layer (gate semiconductor layer control means), 12 ... p-type semiconductor Layer (gate semiconductor layer control means), 13 ... Gate electrode, 14 ... Electrode, 15 ... Polysilicon high resistance film, 16 ... P-type semiconductor layer. 21 ... Silicon substrate, 22 ... Silicon oxide film, 23 ... N-type semiconductor layer, 24
... p-type well layer, 25 ... n-type source layer, 26 ... n-type drain layer, 27 ... source electrode, 28 ... drain electrode, 29
... gate insulating film, 30 ... gate electrode, 31 ... n-type semiconductor layer, 32 ... p-type semiconductor layer, 33 ... lower part of gate electrode, 3
4 ... Lower part of drain electrode, 35 ... High concentration n-type semiconductor layer,
36 ..., 37 ..., 38 ..., 39 ..., 40 ..., 41 ... Contact portion, 42 ... Channel forming portion.

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】第１導電型半導体基板上に設けられた第２
導電型高抵抗半導体層と、 この第２導電型高抵抗半導体層の表面に選択的に形成さ
れた第１導電型半導体層と、 この第１導電型半導体層の表面に選択的に形成された第
２導電型ソース層と、 前記第２導電型高抵抗半導体層の表面に選択的に形成さ
れた第２導電型ドレイン層と、 前記第１導電型半導体層及び前記第２導電型ソース層に
接するソース電極と、 前記第２導電型ドレイン層に接するドレイン電極と、 前記第２導電型ソース層と前記第２導電型ドレイン層と
で挟まれた前記第１導電型半導体層と前記第２導電型高
抵抗半導体層との上に、ゲート絶縁膜を介して設けら
れ、前記ソース電極と接しないゲート半導体層と、 前記第２導電型ソース層と前記第２導電型高抵抗半導体
層とで挟まれた前記第１導電型半導体層上の前記ゲート
半導体層に接するゲート電極と、 前記ドレイン電極と前記ゲート電極との電位差に基づい
て、オン時に前記ゲート半導体層と前記ドレイン電極と
を電気的に分離するゲート半導体層制御手段とを具備し
てなることを特徴とする高耐圧半導体素子。1. A second device provided on a first conductivity type semiconductor substrate.
A conductive type high resistance semiconductor layer, a first conductive type semiconductor layer selectively formed on the surface of the second conductive type high resistance semiconductor layer, and a selectively formed on the surface of the first conductive type semiconductor layer. A second conductive type source layer, a second conductive type drain layer selectively formed on the surface of the second conductive type high resistance semiconductor layer, a first conductive type semiconductor layer and the second conductive type source layer. A source electrode in contact with the second conductive type drain layer; a drain electrode in contact with the second conductive type drain layer; the first conductive type semiconductor layer and the second conductive layer sandwiched between the second conductive type source layer and the second conductive type drain layer; And a high-conductivity-type high-resistance semiconductor layer and a gate semiconductor layer that is provided via a gate insulating film and is not in contact with the source electrode, and the second-conductivity-type source layer and the second-conductivity-type high-resistance semiconductor layer. The gate half on the first conductive type semiconductor layer It comprises a gate electrode in contact with the conductor layer, and a gate semiconductor layer control means for electrically separating the gate semiconductor layer and the drain electrode when turned on, based on a potential difference between the drain electrode and the gate electrode. A high breakdown voltage semiconductor device characterized by the above.
JP18885593A 1993-06-30 1993-06-30 High voltage semiconductor device Expired - Fee Related JP3400025B2 (en)

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US5826221A (en) * 1995-11-30 1998-10-20 Oki Electric Industry Co., Ltd. Vocal tract prediction coefficient coding and decoding circuitry capable of adaptively selecting quantized values and interpolation values
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US5826221A (en) * 1995-11-30 1998-10-20 Oki Electric Industry Co., Ltd. Vocal tract prediction coefficient coding and decoding circuitry capable of adaptively selecting quantized values and interpolation values
JP2006279064A (en) * 1996-01-22 2006-10-12 Fuji Electric Device Technology Co Ltd Method of manufacturing semiconductor device
JP2001156288A (en) * 1999-11-25 2001-06-08 Toyota Motor Corp Semiconductor device
US6878998B1 (en) 2000-04-13 2005-04-12 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with region that changes depth across the direction of current flow
JP2005531153A (en) * 2002-06-26 2005-10-13 ケンブリッジ　セミコンダクター　リミテッド Lateral semiconductor devices
JP2006303111A (en) * 2005-04-19 2006-11-02 Sanken Electric Co Ltd Semiconductor device
JP2012175029A (en) * 2011-02-24 2012-09-10 Sanken Electric Co Ltd Semiconductor device
CN110010469A (en) * 2012-03-16 2019-07-12 ams有限公司 The method for manufacturing high-voltage transistor device
JP2018098221A (en) * 2016-12-07 2018-06-21 トヨタ自動車株式会社 Semiconductor device
JP2019145716A (en) * 2018-02-22 2019-08-29 株式会社豊田中央研究所 Semiconductor device
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CN111725320A (en) * 2020-07-20 2020-09-29 西安电子科技大学 Junction accumulation layer silicon carbide transverse field effect transistor and manufacturing method thereof
CN111725071B (en) * 2020-07-20 2021-06-18 西安电子科技大学 Silicon-based junction accumulation layer and buffer layer lateral double-diffusion field effect transistor and manufacturing method thereof
CN113707708A (en) * 2021-07-26 2021-11-26 西安电子科技大学 Junction accumulation layer enhanced AlGaN/GaN high electron mobility transistor and manufacturing method thereof
CN113707709A (en) * 2021-07-26 2021-11-26 西安电子科技大学 AlGaN/GaN high electron mobility transistor with accumulation layer epitaxial grid MIS structure and manufacturing method thereof
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