CN117558762A - Groove type MOSFET and preparation method - Google Patents
Groove type MOSFET and preparation method Download PDFInfo
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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Abstract
The invention discloses a groove type MOSFET and a preparation method thereof, wherein the MOSFET comprises the following components: a groove; the length of the groove along the first direction is greater than a first threshold value; the trench includes: a filling layer; the filling layer fills the inside of the groove; and the filling layer and the substrate form a PN junction. According to the invention, a novel grid structure is designed to replace a traditional trench grid to form a channel, the length of the channel is changed from the original fixed length to the length of the whole drift layer, and the channel is formed along the drift layer, so that the resistance of the drift layer is reduced, and the on-resistance of the MOSFET is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a trench MOSFET and a manufacturing method thereof.
Background
The trench MOSFET device is a novel MOSFET device with a vertical structure, and is optimized and developed on the basis of the traditional planar MOSFET structure. Compared with a planar MOSFET device, the trench MOSFET device has the advantages that a channel formed by constructing a trench structure penetrating through the bottommost end of the body region is positioned between the source region and the drift region, the JFET region is eliminated, and the JFET resistance is also eliminated; meanwhile, the groove grid structure of the groove type MOSFET device enables the interval of cells to be smaller than that of the plane type MOSFET device, more cells can be connected in parallel in design, and the total resistance is further reduced, so that the groove type MOSFET device can obtain smaller on-resistance.
The on-resistance of a MOSFET affects the operation of the MOSFET, and the on-resistance of a conventional MOSFET is divided into 8 parts, namely, a source contact resistance, a source region resistance, a channel resistance, an accumulation resistance, a JFET resistance, a drift region resistance, a substrate resistance, and a drain contact resistance. The trench gate junction of the trench MOSFET passes through the lowermost end of the P-well layer, eliminating the JFET region and also eliminating the JFET resistance, and therefore, the on-resistance of the trench MOSFET becomes 7 parts in total of source contact resistance, source region resistance, channel resistance, accumulation resistance, drift region resistance, substrate resistance, and drain contact resistance, wherein the ratio occupied by the drift region resistance and the substrate resistance is large.
The bottom of the trench of the conventional trench MOSFET is positioned on the upper layer of the drift layer, an opened conductive channel is positioned between the N+ region and the drift layer, a current path flows from the drain electrode to the drift layer through the substrate, then flows into the N+ region through the conductive channel and finally reaches the source electrode, and the current path needs to pass through the drift layer with high resistance value, so that the on-resistance of the MOSFET device is larger. Direct adjustment of the MOSFET drift layer to reduce the drift region resistance can result in insufficient withstand voltage of the MOSFET device.
Disclosure of Invention
In order to solve at least one technical problem set forth above, an object of the present invention is to provide a trench MOSFET and a method for manufacturing the same.
The aim of the invention is realized by adopting the following technical modes:
in a first aspect, the present invention provides a trench MOSFET comprising: a groove;
the length of the groove along the first direction is greater than a first threshold value;
the trench includes: a filling layer;
the filling layer fills the inside of the groove;
and the filling layer and the substrate form a PN junction.
Preferably, the filling layer includes: a first p+ layer and a first P-layer;
the first P+ layer is positioned below the grid electrode and is adjacent to the grid electrode;
the first P-layer is located below the first P+ layer and is adjacent to the first P+ layer.
Preferably, the filling layer further comprises: an n+ layer, a second P-layer, and a second p+ layer;
the N+ layer is positioned below the first P-layer and is adjacent to the first P-layer;
the second P-layer is positioned below the N+ layer and is adjacent to the N+ layer;
the second p+ layer is located between the second P-layer and the substrate and is adjacent to the second P-layer and the substrate.
Preferably, the width of the trench is 0.6um.
Preferably, the thickness of the first p+ layer is 1um;
the thickness of the first P-layer is 7um.
Preferably, the doping concentration of the first P+ layer is 1×10 19 cm -3 ；
The doping concentration of the first P-layer is 8×10 17 cm -3 。
Preferably, the thickness of the n+ layer is 1um;
the thickness of the second P-layer is 0.5um;
the thickness of the second P+ layer is 0.5um.
Preferably, the doping concentration of the N+ layer is 1×10 19 cm -3 ；
The doping concentration of the second P-layer is 8×10 17 cm -3 ；
The doping concentration of the second P+ layer is 1×10 19 cm -3 。
Preferably, the semiconductor device further comprises a substrate, a drift layer, a P-well layer, an N+ region, a P+ region, a source electrode, a gate electrode and a drain electrode;
the substrate is positioned above the drain electrode and is adjacent to the drain electrode;
the drift layer is positioned above the substrate and is adjacent to the substrate;
the P-well layer is positioned above the drift layer and is adjacent to the drift layer;
the N+ region and the P+ region are positioned above the P-well layer, and the N+ region is adjacent to the P-well layer and the P+ region;
the source is located above the N+ region and the P+ region and is adjacent to the N+ region and the P+ region.
In a second aspect, the present invention provides a method for manufacturing a trench MOSFET, including:
epitaxially forming a drift layer over the substrate;
etching the drift layer to form a groove;
forming a gate oxide layer on the side wall of the groove;
filling the groove to form a filling layer;
forming a P-well layer, an N+ region and a P+ region by ion implantation above the drift layer;
a source and a gate are deposited.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, a novel grid structure is designed to replace a traditional trench grid to form a channel, the length of the channel is changed from the original fixed length to the length of the whole drift layer, and the channel is formed along the drift layer, so that the resistance of the drift layer is reduced, and the on-resistance of the MOSFET is reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
In order to more clearly describe the technical solutions in the embodiments or the background of the present application, the following description will describe the drawings that are required to be used in the embodiments or the background of the present application.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the technical aspects of the disclosure.
Fig. 1 is a schematic structural diagram of a trench MOSFET according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of a method for manufacturing a trench MOSFET according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a method for manufacturing a trench MOSFET according to an embodiment of the present invention.
Detailed Description
In order to make the present application solution better understood by those skilled in the art, the following description will clearly and completely describe the technical solution in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better illustration of the invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some embodiments, methods, means, elements and circuits well known to those skilled in the art have not been described in detail so as not to obscure the present invention.
The on-resistance of a MOSFET affects the operation of the MOSFET, and the on-resistance of a conventional MOSFET is divided into 8 parts, namely, a source contact resistance, a source region resistance, a channel resistance, an accumulation resistance, a JFET resistance, a drift region resistance, a substrate resistance, and a drain contact resistance. The trench gate junction of the trench MOSFET passes through the lowermost end of the P-well layer, eliminating the JFET region and also eliminating the JFET resistance, and therefore, the on-resistance of the trench MOSFET becomes 7 parts in total of source contact resistance, source region resistance, channel resistance, accumulation resistance, drift region resistance, substrate resistance, and drain contact resistance, wherein the ratio occupied by the drift region resistance and the substrate resistance is large.
The bottom of the trench of the conventional trench MOSFET is positioned on the upper layer of the drift layer, an opened conductive channel is positioned between the N+ region and the drift layer, a current path flows from the drain electrode to the drift layer through the substrate, then flows into the N+ region through the conductive channel and finally reaches the source electrode, and the current path needs to pass through the drift layer with high resistance value, so that the on-resistance of the MOSFET device is larger. Direct adjustment of the MOSFET drift layer to reduce the drift region resistance can result in insufficient withstand voltage of the MOSFET device. According to the invention, a novel grid structure is designed to replace a traditional trench grid to form a channel, the length of the channel is changed from the original fixed length to the length of the whole drift layer, and the channel is formed along the drift layer, so that the resistance of the drift layer is reduced, and the on-resistance of the MOSFET is reduced.
Example 1
There is provided a trench MOSFET, as shown in fig. 1, comprising: a groove;
the length of the groove along the first direction is greater than a first threshold value;
the trench includes: a filling layer;
the filling layer fills the inside of the trench;
the filling layer and the substrate form a PN junction.
Trench MOSFETs are a common type of field effect transistor. The basic structure of a trench MOSFET includes a source, a drain, a gate, and a channel. Wherein the channel between the source and the drain is a channel through which current flows, and the gate is a switch that controls the current in the channel. The source electrode metal and the gate electrode metal of the groove type MOSFET are positioned above the silicon wafer, the lower part of the silicon wafer is a substrate, and the drain electrode is positioned below the silicon wafer and contacted with the substrate. Trench MOSFETs, also known as surface effect transistors, have gates buried in the body to form vertical channels, although their process is complex and cell uniformity is inferior to planar structures. However, the trench structure can increase the cell density, has no JFET effect, has smaller parasitic capacitance, has high switching speed and has very low switching loss; in addition, by selecting a proper channel crystal face and an optimally designed structure, the optimal channel mobility can be realized, and the on-resistance is obviously reduced.
The trench refers to a channel region, and the trench type MOSFET can change the performance and characteristics of the transistor by adjusting the size of the trench. In order to form a vertical channel structure, a trench is formed in the drift layer of the trench type MOSFET, and after an oxide layer is manufactured on the surface of the trench, polysilicon is filled in the trench to form a gate. This structure embeds the gate in the body, forming a vertical channel, the current path flowing vertically from the lower substrate drain through the drift layer, channel and source region, the channel and current direction being parallel.
In this embodiment, the novel gate structure is designed to replace the conventional trench gate to form the channel, so that the length of the channel is changed from the original fixed length to the length of the whole drift layer, and the channel is formed along the drift layer, so that the resistance of the drift layer is reduced, and the on-resistance of the MOSFET is reduced. Specifically, the trench is embedded in the drift layer, and a length in the first direction is greater than a first threshold. It should be noted that, the first direction is a direction describing a depth of the trench, and for a vertically arranged trench, the first direction is a direction perpendicular to a placement direction of the drift layer, and the first direction may be a direction in which a top etching portion of the trench points to a bottom portion of the trench, or may be a direction in which a bottom portion of the trench points to a top etching portion of the trench. The first threshold value is 10um, and the length of the groove along the first direction is increased to be more than 10um, and the channel is formed along the drift layer by changing the length of the channel into the length of the whole drift layer, so that the resistance of the drift layer is reduced, and the on-resistance of the MOSFET is reduced.
In some embodiments, referring to fig. 1, the filler layer comprises: a first p+ layer and a first P-layer;
the first P+ layer is positioned below the grid electrode and is adjacent to the grid electrode;
the first P-layer is located below the first P+ layer and is adjacent to the first P+ layer.
The channel is a thin semiconductor layer between the source and drain of a MOSFET, and applying an external electric field to the MOSFET is a common method of turning on the channel of a MOSFET. When a voltage is applied to the MOSFET gate, an inversion layer is formed in the MOSFET in the direction of the electric field, in which current flows and is gate controlled.
In this embodiment, the first p+ layer is located at the uppermost layer of the filling layer, and the first p+ layer is disposed corresponding to the P-well layer, and is used to open an N-type channel on a side of the P-well layer adjacent to the trench. In addition to the need to turn on channels in the P-type lightly doped P-well layer, it is also desirable to turn on channels in the N-type lightly doped drift layer. The N-type lightly doped drift layer opens the N-type channel more easily than the P-type lightly doped P-well layer. The first P-layer is arranged corresponding to the drift layer and is used for opening an N-type channel at one side of the drift layer adjacent to the groove. Because the first P-layer is positioned below the first P+ layer and is adjacent to the first P+ layer, the channel of the first P-layer, which is opened by the first P-layer and is positioned on the drift layer, is connected with the channel of the first P+ layer, which is opened by the P-well layer, so that an entire channel from the drain electrode to the substrate to the N+ region is formed. According to the embodiment, a novel gate structure is designed to replace a traditional trench gate to form a channel, the length of the channel is changed from the original fixed length to the length of the whole drift layer, and the channel is formed along the drift layer, so that the resistance of the drift layer is reduced, and the on-resistance of the MOSFET is reduced.
In some embodiments, referring to fig. 1, the filler layer further comprises: an n+ layer, a second P-layer, and a second p+ layer;
the N+ layer is positioned below the first P-layer and is adjacent to the first P-layer;
the second P-layer is positioned below the N+ layer and is adjacent to the N+ layer;
the second p+ layer is located between and adjacent to the second P-layer and the substrate.
The positive end of the applied voltage is added to the drain electrode of the MOSFET, a low-doped N-region is added between the channel of the high-doped substrate N+ and the channel of the P-well layer, and because N-and N+ are of the same semiconductor type, a current conduction loop is not affected, and current can directly flow from N+ to N-; although N-is low doped, its resistivity is lower than the channel, thus, by adjusting its doping concentration and width, a higher reverse voltage is obtained, and at the same time, the on-resistance is controlled within the designed range, and this structure can flow a large current, which is applied to the power circuit. Thus, for a trench MOSFET of an N-type drift layer, the doping type of the substrate is n+ type. The N-type substrate forms a forward diode with the first P-layer and the first p+ layer in the fill layer, and the drain and gate are thus turned on.
In this embodiment, the n+ layer is located below and adjacent to the first P-layer; the second P-layer is positioned below the N+ layer and is adjacent to the N+ layer; the second p+ layer is located between and adjacent to the second P-layer and the substrate. The N+ layer, the second P-layer and the second P+ layer which are sequentially arranged from top to bottom form a reverse diode structure with the substrate, so that the drain electrode and the grid electrode are prevented from being directly communicated.
In some embodiments, the width of the trench is 0.6um.
The formation of the gate structure of a MOSFET device is a very critical process that involves thermal growth of the thinnest gate oxide layer and etching of the polysilicon gate. A polysilicon gate is a gate structure made of polysilicon material. Polysilicon gates, which have higher conductivity and lower resistance due to the characteristics of silicon materials, are commonly used in MOSFET devices. In addition, the polysilicon gate also has better heat resistance and lower leakage current. The polysilicon gate can control the on and off of the MOSFET device by changing the gate voltage, and plays a role in controlling current. The size of the polysilicon gate directly affects the electrical performance of the MOSFET device, and the reduction of the gate reduces the resistance and power consumption while also increasing thermal noise and channel current non-idealities, and the small gate presents a significant challenge to the manufacturing process. In this embodiment, the width of the trench is set to 0.6um.
In some embodiments, the first p+ layer has a thickness of 1um;
the thickness of the first P-layer was 7um.
The drift layer is formed by epitaxy of the substrate. Epitaxy refers to the process of growing a layer of new single crystal on a carefully processed single crystal substrate, which may be the same material as the substrate or a different material. The nascent monocrystalline layer is grown in extension from the crystalline phase of the substrate and is thus called an epitaxial layer. The thickness of the epitaxial layer is typically a few microns. The thickness of the first p+ layer and the thickness of the first P-layer need to be set corresponding to the thicknesses of the P-well layer and the drift layer, respectively. In this embodiment, the thickness of the first p+ layer is set to 1um, and the thickness of the first P-layer is set to 7um.
In some embodiments, the first P+ layer has a doping concentration of 1×10 19 cm -3 ；
The doping concentration of the first P-layer is 8×10 17 cm -3 。
The first P+ layer is arranged corresponding to the P-well layer and is used for opening an N-type channel at one side of the P-well layer adjacent to the groove. The N-type lightly doped drift layer opens the N-type channel more easily than the P-type lightly doped P-well layer. The first P-layer is arranged corresponding to the drift layer and is used for opening an N-type channel at one side of the drift layer adjacent to the groove. The doping concentrations of the first p+ layer and the first P-layer affect the threshold voltage of the trench MOSFET device. In the present embodiment, the doping concentration of the first P+ layer is set to be 1×10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of the first P-layer is set to 8×10 17 cm -3 。
In some embodiments, the n+ layer has a thickness of 1um;
the thickness of the second P-layer is 0.5um;
the thickness of the second p+ layer was 0.5um.
The change of the thicknesses of the N+ layer, the second P-layer and the second P+ layer can influence the capacitance characteristics of the trench MOSFET, when the thicknesses of the N+ layer, the second P-layer and the second P+ layer are larger, the capacitance between the drain electrode and the grid electrode is larger, and the control capability of the grid electrode on the drain electrode current is weaker; the trench MOSFET is exposed to the risk of breakdown when the thicknesses of the n+ layer, the second P-layer and the second p+ layer are small. In this embodiment, the thickness of the n+ layer is set to 1um, the thickness of the second P-layer is set to 0.5um, and the thickness of the second p+ layer is set to 0.5um.
In some embodiments, the doping concentration of the n+ layer is 1×10 19 cm -3 ；
The doping concentration of the second P-layer is 8×10 17 cm -3 ；
The doping concentration of the second P+ layer is 1×10 19 cm -3 。
In the present embodiment, the doping concentration of the n+ layer is set to 1×10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of the second P-layer is set to 8×10 17 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of the second P+ layer is set to be 1×10 19 cm -3 。
In some embodiments, as shown with reference to fig. 1, further comprising a substrate, a drift layer, a P-well layer, an n+ region, a p+ region, a source, a gate, and a drain;
the substrate is positioned above the drain electrode and is adjacent to the drain electrode;
the drift layer is positioned above the substrate and is adjacent to the substrate;
the P-well layer is positioned above the drift layer and is adjacent to the drift layer;
the N+ region and the P+ region are positioned above the P-well layer, and the N+ region is adjacent to the P-well layer and the P+ region;
the source is located above and adjacent to the n+ region and the p+ region.
Example 2
There is provided a method for manufacturing a trench MOSFET, as shown in fig. 2 and 3, comprising:
s100, epitaxially forming a drift layer above a substrate;
an epitaxial process refers to a process of growing a single crystal layer in complete alignment on a substrate. Generally, an epitaxial process is a process of growing a layer of crystals on a monocrystalline substrate that have the same lattice orientation as the original substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. Embedded source drain epitaxial growth of MOS transistors, epitaxial growth on LED substrates, and the like. According to the different phases of the growth source, the epitaxial growth modes are divided into solid phase epitaxy, liquid phase epitaxy and gas phase epitaxy. In integrated circuit fabrication, common epitaxy methods are solid phase epitaxy and vapor phase epitaxy.
Solid phase epitaxy refers to the process of epitaxially recrystallizing an amorphous layer on a semiconductor single crystal at a temperature below the melting point or eutectic point of the material. The recrystallization process without epitaxy does not belong to solid phase epitaxy. There are two main growth modes of solid phase epitaxy: an amorphous layer is directly contacted with a monocrystalline substrate for epitaxial growth; the other is solid phase epitaxy by sandwiching a layer of metal or carbide between an amorphous layer and a monocrystalline silicon substrate. Metals and carbides act as transport media. There are various methods for forming polycrystalline or amorphous thin films. A method for directly implanting ions includes such steps as high-dose implantation of germanium ions on silicon monocrystal substrate to form GeSi amorphous thin layer, annealing at 475-575 deg.C, and growing again to obtain strain alloy layer. The other is to deposit a thin film, such as evaporation or sputtering. Compared with the common epitaxial method, the solid phase epitaxial substrate has low temperature and small impurity diffusion, and is favorable for manufacturing the epitaxial layer with the abrupt doping interface.
In the vapor phase state, a semiconductor material is deposited on a single crystal wafer such that it grows a single crystal layer having a desired thickness and resistivity along the crystal axis of the single crystal wafer, a process called vapor phase epitaxy. The method is characterized in that: the epitaxial growth temperature is high, and the growth time is long, so that a thicker epitaxial layer can be manufactured; the concentration and conductivity type of the impurities may be arbitrarily changed during the epitaxy process. The common vapor phase epitaxy process for industrial production is as follows: silicon tetrachloride (germanium) epitaxy, silicon (germanium) alkane epitaxy, trichlorosilane, dichlorosilane, and the like (dichlorosilane has depositionLow temperature, high deposition speed, uniform deposition film, etc.), and the like. Common concepts and principles of silicon vapor phase epitaxy: with gaseous compounds of silicon (e.g. SiCl 4 、SiH 4 ) The silicon substrate surface is heated, and then is chemically reacted with hydrogen or thermally decomposed by itself, reduced to silicon, and deposited on the silicon substrate surface in a single crystal form. The growth method of vapor phase epitaxy includes chemical vapor phase epitaxy (CVE), molecular beam epitaxy (MBD), atomic Layer Epitaxy (ALE), and the like. Vapor phase epitaxy of semiconductors is the process in which a gaseous compound of silicon reacts with hydrogen or thermally decomposes itself to reduce to silicon at the heated substrate surface and deposits on the substrate surface in the form of a single crystal. The method specifically comprises the following steps: the reactant molecules are transferred from the gas phase to the surface of the growth layer in a diffusion manner; the reactant molecules are adsorbed by the growth layer; the adsorbed reactant molecules complete chemical reaction on the surface of the growth layer to produce semiconductors and other byproducts; byproduct molecules are resolved from the surface and discharged out of the reaction cavity along with the airflow; atoms generated by the reaction form a lattice or are added to the lattice to form a single crystal epitaxial layer.
The epitaxial system device includes: the system comprises a gas distribution and control system, a heating and temperature measuring device, a reaction chamber and an exhaust gas treatment device. The technological process includes the following steps: substrate and susceptor processing: the substrate treatment is mainly to remove oxide layer and dust particles on the surface of the substrate wafer, and the substrate is put into a graphite base after washing and drying. The already used graphite susceptor should be subjected to HCI etching in advance to remove the silicon that was left on the previous epitaxy. Preparing a doping agent: the dopant being a gaseous source, e.g. phosphane PH 3 Borane B 2 H 6 Etc.; liquid sources such as POCI 3 、BBr 3 And the like, the requirements of different devices on the resistivity and the conductivity type of the epitaxial layer are different, and the dosage of the doping source must be precisely controlled according to the resistivity. And (3) epitaxial growth: the main procedures are as follows: charging and ventilation, nitrogen gas and then hydrogen gas are introduced, and then a substrate is heated for heat treatment or HCl polishing, epitaxial growth, hydrogen gas flushing, cooling and nitrogen gas flushing are carried out. And when the temperature of the base is reduced to below 300 ℃, opening the furnace to take tablets. The quality of the vapor phase epitaxy requires that the quality of the epitaxial layer should satisfy: the crystal structure is complete, the resistivity is accurate and uniform, the epitaxial layer thickness is uniform and within the range, and the surface light is providedClean, free of oxidation and haze, less surface defects (pyramids, mastoid, star defects, etc.) and in vivo defects (dislocations, stacking faults, slip lines, etc.). The epitaxial quality inspection content comprises: resistivity, impurity concentration profile, epitaxial layer thickness, minority carrier lifetime, mobility, interlayer dislocation and stacking fault density, surface defects, and the like. Typical test items in production are defect density, resistivity and epitaxial layer thickness. The thickness measuring method of the epitaxial layer comprises a stacking fault method, a grinding angle or rolling groove dyeing method, a direct reading method, an infrared interferometry method and the like. The resistivity measurement method includes four-probe method, three-probe method, capacitance-voltage method and extended resistance method, and the capacitance-voltage method, the extended resistance method and the like are often adopted for epitaxial layers with higher resistivity or thinner thickness.
S200, etching the drift layer to form a groove;
etching is a process of selectively removing unwanted material from the surface of a silicon wafer by chemical or physical means, and is a generic term for stripping and removing material by solution, reactive ions or other mechanical means. The etching technology is mainly divided into dry etching and wet etching. The dry etching mainly uses the reaction gas and the plasma for etching; the wet etching mainly uses chemical reagents to chemically react with the etched material for etching.
Ion beam etching is a physical dry etching process. Thereby, argon ions are irradiated onto the surface with an ion beam of about 1 to 3 keV. Due to the energy of the ions, they strike the material of the surface. The wafer is vertically or obliquely directed into the ion beam and the etching process is absolutely anisotropic. The selectivity is low because it is not different for each layer. The gas and abraded material are evacuated by the vacuum pump, but since the reaction products are not gaseous, particles can deposit on the wafer or chamber walls. All materials can be etched in this way and the wear on the vertical walls is low due to the vertical radiation.
Plasma etching is a chemical etching process and has the advantage that the wafer surface is not damaged by accelerated ions. The method is used to remove the entire film (e.g., backside cleaning after thermal oxidation) because the etch profile is isotropic due to the movable particles of the etch gas. One type of reactor used for plasma etching is a downstream reactor whereby the plasma is ignited at a high frequency of 2.45GHz by impact ionization, the location of which is separated from the wafer.
The etch rate depends on the pressure, the power of the high frequency generator, the process gas, the actual gas flow and the wafer temperature. Anisotropy increases with an increase in high-frequency power, a decrease in pressure, and a decrease in temperature. The uniformity of the etching process depends on the gas, the distance between the two electrodes and the material of the electrodes. If the distance is too small, the plasma cannot be unevenly dispersed, resulting in non-uniformity. If the distance of the electrodes is increased, the etch rate is reduced because the plasma is distributed in the enlarged volume. Carbon has proven to be the material of choice for electrodes. Since fluorine and chlorine also attack carbon, the electrodes produce a uniformly strained plasma and the wafer edge is affected by the same effect as the wafer center. The selectivity and etch rate are largely dependent on the process gas. For silicon and silicon compounds, fluorine gas and chlorine gas are mainly used.
S300, forming a gate oxide layer on the side wall of the groove;
the oxidation process is to form a protective film on the silicon wafer, and the oxide film formed by the oxidation process has stability and can prevent other substances from penetrating in the semiconductor manufacturing process. The oxide film may also be used to block the flow of current between circuits, and the MOSFET isolates the gate from the current channel through the oxide film, which is referred to as the gate oxide. The oxidation process may be classified into wet oxidation and dry oxidation. The wet oxidation is to generate an oxide film by adopting a mode of reacting with high-temperature steam, and the oxide film grows fast, but the uniformity and density of the whole oxide layer are low, and byproducts such as hydrogen and the like are generated in the oxidation process. The dry oxidation is to generate an oxide film by directly reacting with high-temperature pure oxygen. Oxygen molecules penetrate relatively slowly into the wafer interior as compared to water molecules. Therefore, the growth rate of the oxide film by dry oxidation is slower than that by wet oxidation, but the dry oxidation does not generate byproducts, and the uniformity and density of the oxide film are higher.
The different atomic densities of the different crystal planes result in different etching rates, and the etching rate of some etchants to one crystal plane is much faster than the etching rate of other crystal planes, which is called anisotropic etching. The dry etching method using plasma applies energy to the plasma to cause the outermost electrons of the source gas in a neutral state to be stripped and converted into cations. The cations have an anisotropy and are suitable for etching in a certain direction. For silicon dioxide of the gate oxide layer, silicon is removed by using chlorine-based plasma with polysilicon etching selectivity, and for the bottom insulating layer, a fluorocarbon-based plasma source gas with etching selectivity and stronger efficacy is used for etching the silicon dioxide film.
In this embodiment, a gate oxide layer is formed on the sidewall of the trench by dry oxidation to form thermal oxygen on the sidewall and then by anisotropic etching.
S400, filling the groove to form a filling layer;
polysilicon deposition, i.e. forming gate electrodes and local connections on the silicide stack on the first layer of polysilicon (Poly 1), and the second layer of polysilicon (Poly 2) forming contact plugs between the source/drain 1 and the cell connections. The silicide is stacked on the third layer polysilicon (Poly 3) to form a cell connection, and the fourth layer polysilicon (Poly 4) and the fifth layer polysilicon (Poly 5) form two electrodes of the storage capacitor with a dielectric medium with high dielectric coefficient sandwiched therebetween. To maintain the desired capacitance value, the size of the capacitor may be reduced by using a dielectric with a high dielectric coefficient. Polysilicon deposition is a Low Pressure Chemical Vapor Deposition (LPCVD) process by depositing arsenic trioxide (AH) in a reaction chamber (i.e., in a furnace tube) 3 ) Phosphorus trihydride (PH) 3 ) Or diborane (B) 2 H 6 ) The doping gas of the silicon material is directly input into the silicon material gas of silane or DCS, so that the polysilicon doping process of the in-situ low-pressure chemical vapor deposition can be performed. Polysilicon deposition is performed at low pressure conditions of 0.2-1.0Torr and deposition temperatures between 600 and 650 ℃ using pure silane or silane diluted with nitrogen to a purity of 20% to 30%. The deposition rate of both deposition processes is between 100 and 200A/min, which is determined primarily by the temperature at which the deposition is performed。
In this embodiment, the fill layer is formed by depositing a second p+ layer, a second P-layer, an n+ layer, a first P-layer, and a first p+ layer within the trench.
S500, forming a P-well layer, an N+ region and a P+ region by ion implantation above the drift layer;
doping is the process of doping a certain amount of impurities into a semiconductor material in order to change the electrical properties of the semiconductor material. The doping method mainly comprises diffusion and ion implantation. Diffusion is accomplished by placing the semiconductor wafer in a precisely controlled high temperature quartz tube furnace with a mixed gas containing the impurities to be diffused, the number of impurity atoms diffused into the semiconductor being related to the impurity partial pressure of the mixed gas. For silicon diffusion, the temperature range is typically 800 degrees celsius to 1200 degrees celsius, boron being the most common P-type impurity, and arsenic and phosphorus being the most common N-type impurity. Ion implantation is the incorporation of charged ions into silicon at energies between 1keV and 1MeV, corresponding to average ion distribution depths ranging between 10nm and 10 um. Compared with the diffusion process, the ion implantation has the advantages that the impurity doping amount can be controlled accurately, good repeatability is maintained, and meanwhile, the processing process temperature of the ion implantation is lower than that of diffusion.
In this embodiment, the P-well layer, the n+ region, and the p+ region are formed by ion implantation.
S600, depositing a source electrode and a grid electrode.
Metal electrode deposition processes are classified into Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD). CVD refers to a process of chemically depositing a coating on the surface of a wafer, typically by applying energy to a gas mixture. Assuming that the substance (a) is deposited on the wafer surface, two gases (B and C) that can generate the substance (a) are first input to the deposition apparatus, and then energy is applied to the gases to cause the gases B and C to chemically react. PVD (physical vapor deposition) coating techniques are mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of physical vapor deposition are: vacuum evaporation, sputter coating, arc plasma coating, ion coating, molecular beam epitaxy, and the like. The corresponding vacuum coating equipment comprises a vacuum evaporation coating machine, a vacuum sputtering coating machine and a vacuum ion coating machine.
According to the embodiment, a novel gate structure is designed to replace a traditional trench gate to form a channel, the length of the channel is changed from the original fixed length to the length of the whole drift layer, and the channel is formed along the drift layer, so that the resistance of the drift layer is reduced, and the on-resistance of the MOSFET is reduced.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A trench MOSFET comprising: a groove;
the length of the groove along the first direction is greater than a first threshold value;
the trench includes: a filling layer;
the filling layer fills the inside of the groove;
and the filling layer and the substrate form a PN junction.
2. The trench MOSFET of claim 1, wherein the filler layer comprises: a first p+ layer and a first P-layer;
the first P+ layer is positioned below the grid electrode and is adjacent to the grid electrode;
the first P-layer is located below the first P+ layer and is adjacent to the first P+ layer.
3. The trench MOSFET of claim 2, wherein the filler layer further comprises: an n+ layer, a second P-layer, and a second p+ layer;
the N+ layer is positioned below the first P-layer and is adjacent to the first P-layer;
the second P-layer is positioned below the N+ layer and is adjacent to the N+ layer;
the second p+ layer is located between the second P-layer and the substrate and is adjacent to the second P-layer and the substrate.
4. The trench MOSFET of claim 1 wherein the trench has a width of 0.6um.
5. A trench MOSFET according to claim 3, wherein said first p+ layer has a thickness of 1um;
the thickness of the first P-layer is 7um.
6. A trench MOSFET according to claim 3, wherein said first p+ layer has a doping concentration of 1 x 10 19 cm -3 ；
The doping concentration of the first P-layer is 8×10 17 cm -3 。
7. A trench MOSFET according to claim 3, wherein said n+ layer has a thickness of 1um;
the thickness of the second P-layer is 0.5um;
the thickness of the second P+ layer is 0.5um.
8. A trench MOSFET according to claim 3, wherein said n+ layer has a doping concentration of 1 x 10 19 cm -3 ；
The doping concentration of the second P-layer is 8×10 17 cm -3 ；
The doping concentration of the second P+ layer is 1×10 19 cm -3 。
9. The trench MOSFET of claim 1 further comprising a substrate, a drift layer, a P-well layer, an n+ region, a p+ region, a source, a gate, and a drain;
the substrate is positioned above the drain electrode and is adjacent to the drain electrode;
the drift layer is positioned above the substrate and is adjacent to the substrate;
the P-well layer is positioned above the drift layer and is adjacent to the drift layer;
the N+ region and the P+ region are positioned above the P-well layer, and the N+ region is adjacent to the P-well layer and the P+ region;
the source is located above the N+ region and the P+ region and is adjacent to the N+ region and the P+ region.
10. A method for fabricating a trench MOSFET, comprising:
epitaxially forming a drift layer over the substrate;
etching the drift layer to form a groove;
forming a gate oxide layer on the side wall of the groove;
filling the groove to form a filling layer;
forming a P-well layer, an N+ region and a P+ region by ion implantation above the drift layer;
a source and a gate are deposited.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07130996A (en) * | 1993-06-30 | 1995-05-19 | Toshiba Corp | High-breakdown-strength semiconductor element |
| JPH08102538A (en) * | 1994-08-01 | 1996-04-16 | Toyota Motor Corp | Field effect type semiconductor device |
| US20050056886A1 (en) * | 2003-07-30 | 2005-03-17 | Jeno Tihanyi | Semiconductor arrangement having a MOSFET structure and a zener device |
| US20180158898A1 (en) * | 2016-12-07 | 2018-06-07 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07130996A (en) * | 1993-06-30 | 1995-05-19 | Toshiba Corp | High-breakdown-strength semiconductor element |
| JPH08102538A (en) * | 1994-08-01 | 1996-04-16 | Toyota Motor Corp | Field effect type semiconductor device |
| US20050056886A1 (en) * | 2003-07-30 | 2005-03-17 | Jeno Tihanyi | Semiconductor arrangement having a MOSFET structure and a zener device |
| US20180158898A1 (en) * | 2016-12-07 | 2018-06-07 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
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