CN117317007A - SiC UMOS with stepped CSL layer and preparation method - Google Patents

SiC UMOS with stepped CSL layer and preparation method Download PDF

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Publication number
CN117317007A
CN117317007A CN202311068358.3A CN202311068358A CN117317007A CN 117317007 A CN117317007 A CN 117317007A CN 202311068358 A CN202311068358 A CN 202311068358A CN 117317007 A CN117317007 A CN 117317007A
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layer
csl
sic
umos
stepped
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乔凯
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Sirius Semiconductor Chengdu Co ltd
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Sirius Semiconductor Chengdu Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention provides a SiC UMOS with a stepped CSL layer and a preparation method thereof, wherein the SiC UMOS comprises the following steps: a multi-layer CSL layer; a plurality of CSL layers are positioned below the P-well layer; the width of the plurality of CSL layers decreases in a direction away from the P-well layer. The invention improves the single CSL layer in the prior art, adopts the structure of the multi-layer CSL layer with a stepped structure, and can limit the expansion of the depletion regions of the P+ shielding layer and the N-drift layer, thereby increasing the conduction path of electrons, further improving the conductivity of SiC UMOS, reducing parasitic resistance and improving the current density of the SiC UMOS.

Description

SiC UMOS with stepped CSL layer and preparation method
Technical Field
The invention relates to the technical field of semiconductors, in particular to a SiC UMOS with a stepped CSL layer and a preparation method thereof.
Background
The third-generation semiconductor material silicon carbide has the characteristics of wide band gap, high breakdown field intensity, high heat conductivity, high saturated electron migration rate, stable physical and chemical properties and the like, and can be suitable for high-temperature, high-frequency, high-power and extreme environments. Silicon carbide has a larger forbidden bandwidth and a higher critical breakdown field strength. Compared with a silicon power device under the same condition, the withstand voltage degree of the silicon carbide device is about 10 times of that of a silicon material. In addition, the silicon carbide device has higher electron saturation rate, small forward on-resistance and lower power loss, is suitable for large-current and large-power application, and reduces the requirement on heat radiation equipment. Silicon carbide is more conveniently formed into silicon dioxide by thermal oxidation than other third generation semiconductors such as GaN. SiC has unique physical, chemical and electrical properties, and is a semiconductor material with great development potential in the extreme application fields of high temperature, high frequency, high power, radiation resistance and the like. The SiC power device has a series of advantages of high input impedance, high switching speed, high working frequency, high voltage resistance and the like, and is widely applied to the aspects of switching regulated power supplies, high frequency, power amplifiers and the like. Silicon carbide metal oxide semiconductor field effect transistor (SiCNOSFET) is used as an important power semiconductor device, the grid electrode of the SiCNOSFET can be turned on and off through voltage control, and the SiCNOSFET has the advantages of high input impedance and low conduction loss, and is widely applied to the fields of switching power supplies, motor control, mobile communication and the like.
Because the Trench MOSFET (Trench metal oxide semiconductor field effect transistor) is formed by deep trenches into the silicon carbide body, more cells can be connected in parallel in design, so that the on-resistance (Ron) is reduced, and larger current conduction and wider switching speed are realized. Compared with a planar power device, the grid electrode is formed in the vertical groove, but electric field concentration is easy to cause at two ends below the groove, so that the electric field at two ends below the groove is far greater than that at other places, the problem of local breakdown of a grid electrode oxide layer can be caused, and the reliability of the device is affected. In order to protect the gate oxide layer, a shielding region is usually introduced below the trench, because the shielding region can be effectively depleted from the drift layer to reduce the electric field peak value, however, the shielding region protects the gate oxide and forms a parasitic JFET with the P-Well layer, and the existence of the parasitic JFET can reduce the current density of the device, so in order to weaken the parasitic resistance of the parasitic JFET formed by the shielding region and the P-Well layer, a current expansion layer CSL is introduced in the prior art to improve the conductivity of the device, but the improvement effect is not significant.
Disclosure of Invention
The invention aims to provide a SiC UMOS with a stepped CSL layer and a preparation method thereof, wherein the single-layer CSL layer in the prior art is improved, and the stepped CSL layer is adopted to limit the expansion of a depletion region of a P+ shielding layer and an N-drift layer, so that the conduction path of electrons is increased, the conductivity of the SiC UMOS is improved, the parasitic resistance is reduced, and the current density of the SiC UMOS is improved.
A SiC UMOS having a stepped CSL layer, comprising: a multi-layer CSL layer;
a plurality of CSL layers are positioned below the P-well layer;
the width of the plurality of CSL layers decreases in a direction away from the P-well layer.
Preferably, the doping concentration of the plurality of CSL layers decreases in a direction away from the P-well layer.
Preferably, the width of the first CSL layer below the P-well layer is equal to the width of the P-well layer.
Preferably, the CSL layer has a thickness of 0.2-0.3um.
Preferably, the doping concentration of the CSL is 10 at minimum 16 cm -3 。
Preferably, the doping concentration of the CSL is at most 10 17 cm -3 。
Preferably, the method further comprises: the device comprises a source electrode, a drain electrode, a grid electrode, an N-type substrate, a P+ layer and an N+ layer;
the drain electrode is positioned below the N-type substrate;
the N-type substrate is positioned below the N-drift layer;
the N-drift layer is positioned below the P-well layer;
the P-well layer is positioned below the P+ layer and the N+ layer;
the P+ layer and the N+ layer are located below the source electrode;
the N+ layer and the P-well layer are provided with through holes;
the groove is arranged on the upper layer of the N-drift layer and is connected with the through hole;
the gate is located in the trench.
Preferably, the method further comprises: a P+ shielding layer;
the P+ shielding layer is located below the groove.
A method of preparing SiC UMOS having a stepped CSL layer, comprising:
doping the upper layer of the N-drift layer to form a plurality of CSL layers;
epitaxially forming a P-well layer, an N+ layer and a P+ layer above the CSL layer;
a through hole is formed in the P-well layer and the N+ layer, a groove is formed in the upper layer of the N-drift layer, and the through hole is connected with the groove;
a metal electrode and an interlayer dielectric are deposited.
Preferably, after the N-drift layer is doped to form a plurality of CSL layers, the method further includes: and doping the upper layer of the N-drift layer to form a P+ shielding layer.
Because the P+ shielding layer forms a JFET with the P-well layer while protecting the gate oxide layer, parasitic resistance is increased, and the current density of the SiC UMOS is reduced; a plurality of CSL layers are positioned below the P-well layer; the width of the plurality of CSL layers decreases in a direction away from the P-well layer. Because PN junctions of the P+ shielding layer and the N-drift layer are widened at one side of the N-drift layer, a current path is limited, so that the stepped CSL layer is adopted to limit the widening of the PN junctions of the P+ shielding layer and the N-drift layer, thereby increasing an electron conduction path, improving the conductivity and increasing the current density of the SiC UMOS.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic diagram of the structure of a SiC UMOS of the present invention;
FIG. 2 is a schematic flow chart of a method for preparing SiC UMOS according to the present invention;
fig. 3 is a schematic structural diagram of a SiC UMOS preparation method of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
Compared with a planar power device, a Trench MOSFET (Trench metal oxide semiconductor field effect transistor) has a gate formed in a vertical Trench, but electric fields are easily concentrated at two ends below the Trench, so that the electric fields at two ends below the Trench are far greater than those at other places, which can cause the problem of local breakdown of a gate oxide layer and affect the reliability of the device. In order to protect the gate oxide layer, a shielding region is usually introduced below the trench, because the shielding region can be effectively depleted from the drift layer to reduce the electric field peak value, however, the shielding region protects the gate oxide and forms a parasitic JFET with the P-Well layer, and the existence of the parasitic JFET can reduce the current density of the device, so in order to weaken the parasitic resistance of the parasitic JFET formed by the shielding region and the P-Well layer, a current expansion layer CSL is introduced in the prior art to improve the conductivity of the device, but the improvement effect is not significant.
Because the P+ shielding layer forms a JFET with the P-well layer while protecting the gate oxide layer, parasitic resistance is increased, and the current density of the SiC UMOS is reduced; a plurality of CSL layers are positioned below the P-well layer; the width of the plurality of CSL layers decreases in a direction away from the P-well layer. Because PN junctions of the P+ shielding layer and the N-drift layer are widened at one side of the N-drift layer, a current path is limited, so that the stepped CSL layer is adopted to limit the widening of the PN junctions of the P+ shielding layer and the N-drift layer, thereby increasing an electron conduction path, improving the conductivity and increasing the current density of the SiC UMOS.
Example 1
SiC UMOS with stepped CSL layer, referring to fig. 1, comprising: a multi-layer CSL layer;
the multi-layer CSL layer is positioned below the P-well layer;
the CSL layer (current expansion layer) is used for improving the electrical property and reliability of the SiC UMOS, and can reduce the resistance of the SiC UMOS to improve the working efficiency and reliability of the SiC UMOS, and meanwhile, the CSL layer (current expansion layer) can also reduce the leakage current of the SiC UMOS and improve the reliability of the SiC UMOS.
CSL layers (current spreading layers) are commonly used as a material layer of SiC UMOS to control carrier injection in semiconductor devices and to improve device performance. In a semiconductor device, carrier injection refers to a process of injecting electrons or holes into a semiconductor material to generate a current. However, such injection processes may lead to certain adverse effects such as thermal effects, carrier trapping, and material damage. These effects can reduce the performance and lifetime of the device. In order to solve these problems, the present invention introduces a CSL layer (current spreading layer) that can effectively limit carrier injection and diffusion while maintaining low resistance and high transparency. Because the doping concentration of the CSL layer is larger than that of the N-region, the extension of a PN junction formed by the P+ shielding layer and the N-drift layer can be limited, and the electronic conduction path can be increased, so that the conductivity of the SiC UMOS is improved, the flow of carriers can be better controlled by the SiC UMOS, and the performance and the reliability of the device are improved. And manufacturing a CSL layer (current expansion layer), namely performing N-type doping with a certain depth larger than the concentration of the epitaxial layer before P-well layer injection, so as to realize the effects of increasing a current path and reducing on-resistance.
The width of the multi-layer CSL layer decreases in a direction away from the P-well layer.
When the P+ shielding layer exists, the current density is maximum in the area between the P+ shielding layer and the P-well layer and gradually decreases from the direction away from the P-well layer, so that the width of the multi-layer CSL layer (current expansion layer) is gradually decreased in the direction away from the P-well layer.
Preferably, the doping concentration of the multi-layer CSL layer decreases in a direction away from the P-well layer.
Since the current density is maximized in the region between the P+ shield layer and the P-well layer when the P+ shield layer is present and then gradually decreases from the direction away from the P-well layer, in order to be able to limit the expansion of the depletion region of the P+ shield layer with the N-drift layer better, the doping concentration of the CSL layer (current spreading layer) is also set to decrease in the direction away from the P-well layer, and the doping concentration difference of each CSL layer (current spreading layer) is 2-9 times, since the doping concentration of the N-drift layer is usually 10 15 cm -3 The doping concentration of the P-well layer is typically 10 17 cm -3 As a preferred embodiment, the invention provides three CSL layers (current spreading layers) and then sets the doping concentration of the CSL layer closest to the P-well layer (current spreading layer) to 10 17 cm -3 The doping concentration of the intermediate CSL layer (current spreading layer) was set to 5×10 16 cm -3 Will be furthest from the P-well layerThe doping concentration of the CSL layer (current spreading layer) of (a) is set to 10 16 cm -3 The CSL layer (current spreading layer) may also be provided in two or more layers, specifically optimized according to the actual current density profile of the MOSFET. During specific preparation, preparing a plurality of CSL layers (current expansion layers) from bottom to top, firstly determining the width and concentration of the CSL layer (current expansion layer) at the bottom, and then adjusting parameters of an ion implanter according to the minimum value of the width and concentration of the CSL layer (current expansion layer) to realize the gradual increase of the width and concentration of the CSL layer (current expansion layer) in the direction approaching to the P-well layer.
According to the invention, by combining the CSL layer (current expansion layer) with the doping concentration decreasing in the direction away from the P-well layer and the CSL layer (current expansion layer) with the width decreasing in the direction away from the P-well layer, the expansion of the depletion region of the P+ shielding layer and the N-drift layer can be better limited, so that the electron conduction path is increased, and the conductivity of the SiC UMOS is greatly improved.
Preferably, the width of the first CSL layer below the P-well layer is equal to the width of the P-well layer.
Since the current density below the P-well layer is the largest, the width of the first CSL layer (current spreading layer) below the P-well layer is the largest, the invention sets the width of the CSL layer (current spreading layer) to the value of the width of the P-well, then the CSL layers (current spreading layers) decrease from the maximum width in sequence in the direction away from the P-well layer, for example, the width of the CSL layer (current spreading layer) closest to the P-well layer is equal to the width of the P-well layer, then the width of the next CSL layer (current spreading layer) is half the width of the P-well layer, and then the width of the next CSL layer (current spreading layer) is one fourth the width of the P-well layer, i.e., the width of each CSL layer (current spreading layer) is half the width of the previous CSL layer (current spreading layer), and the width of the CSL layer (current spreading layer) can also be optimized according to the actual current density of the MOSFET. According to the invention, the stepped CSL layer (current expansion layer) is arranged, so that the expansion of the depletion region between the P+ shielding layer and the N-drift layer can be limited, the electronic conduction path is increased, and the conductivity of the SiC UMOS is greatly improved.
Preferably, the CSL layer has a thickness of 0.2-0.3um.
Since the trench thickness is typically 1-2um and the p-well layer thickness is typically 0.8-1um, the sum of the thicknesses of the multiple CSL layers (current spreading layers) is 1um. The thickness of the CSL layer (current spreading layer) is designed according to the parameters of the SiC UMOS device, and the thicknesses of the CSL layers (current spreading layers) of different types are different, so in order to reduce the production cost, in the embodiment of the present invention, three CSL layers (current spreading layers) are provided, so the thickness of each CSL layer (current spreading layer) is set to 0.3um, and the thickness of each CSL layer (current spreading layer) can also be set differently, specifically, the thickness is optimized according to the actual current density distribution diagram of the MOSFET, and the production cost of the CSL layer (current spreading layer) with the greater number of layers and the thinner thickness is higher.
Preferably, the doping concentration of CSL is at least 10 16 cm -3 。
Preferably, the doping concentration of CSL is at most 10 17 cm -3 。
Since the doping concentration of the N-drift layer is usually 10 15 cm -3 The doping concentration of the P-well layer is typically 10 17 cm -3 The doping concentration of the CSL layer (current spreading layer) is between the doping concentration of the N-drift layer and the doping concentration of the P-well layer, so the minimum doping concentration of the CSL is set to 10 16 cm -3 The maximum doping concentration of CSL is set to 10 17 cm -3 . This ensures that electrons can flow from the N-drift layer to the CSL layer (current spreading layer) and then from the CSL layer (current spreading layer) to the P-well layer, which can result in a failure to pass current if the concentration of the CSL layer (current spreading layer) is set too high or too low.
Preferably, the method further comprises: the device comprises a source electrode, a drain electrode, a grid electrode, an N-type substrate, a P+ layer and an N+ layer;
the drain electrode is positioned below the N-type substrate;
the drain is the charge sink in the MOSFET, which is connected to the channel and is the charge sink. When the MOSFET is in a conducting state, a conducting path is formed between the drain electrode and the source electrode, electrons flow into the drain electrode from the source electrode, and current transmission is completed. The voltage change of the drain electrode has little influence on the working state of the MOSFET, and mainly plays a role in current inflow.
The N-type substrate is positioned below the N-drift layer;
the N-drift layer is positioned below the P-well layer;
the P-well layer is positioned below the P+ layer and the N+ layer;
the lateral diffusion difference of the P-well layer and the source constitutes the channel of the SiC MOSFET.
The P+ layer and the N+ layer are positioned below the source electrode;
the N+ layer and the P-well layer are provided with through holes;
the groove is arranged on the upper layer of the N-drift layer and is connected with the through hole;
the gate is located in the trench.
The source is the source of charge in the MOSFET and is the exit of the charge. When the MOSFET is in a conducting state, a conducting path is formed between the source electrode and the drain electrode, electrons flow into the drain electrode from the source electrode, and current transmission is completed. Meanwhile, the source electrode also plays a role of modulating the grid voltage, and the control of the MOSFET is realized by controlling the change of the source electrode voltage.
The gate is the control electrode in the MOSFET, and is separated from the channel by an insulating layer, which is a critical part of the MOSFET. The voltage variation of the gate can change the charge density in the channel, thereby controlling the magnitude of the current between the drain and the source.
Preferably, the method further comprises: a P+ shielding layer;
the P+ shielding layer is located below the trench.
According to the invention, the P+ shielding layer is arranged below the groove and can be used for exhausting N-drift layers on two sides, so that the electric field peak value below the groove is reduced, the grid oxide layer at the corner below the groove is protected from being broken down by high field intensity, but the P+ shielding layer, the P-well layer and the N-drift layer form a parasitic JFET (junction field effect transistor), the JFET adopts a PN junction as a grid of a device to control the opening and closing of a channel, when the PN junction is negatively biased on the grid, the two sides of the PN junction are exhausted, when the channel is completely exhausted, the device is in a channel pinch-off state, and the device is cut off. Otherwise, the device is turned on. The JFET is a structure in which two highly doped P regions are formed on an N-type semiconductor and connected together, and the P-type semiconductor on both sides of the N-type semiconductor is in contact with the N-type semiconductor because of the difference in the concentration of the doped carriers (the majority carriers in the N-type semiconductor are electrons and the majority carriers in the P-type semiconductor are holes), and after the contact, the electrons in the N-type semiconductor diffuse into the P-type semiconductor and the holes in the P-type semiconductor diffuse into the N-type semiconductor. However, as diffusion proceeds, electrons in the N-type semiconductor become less and then become positively charged from the electric neutrality, and the P-type semiconductor is further negatively charged. An internal electric field is generated from the N-type semiconductor to the P-type semiconductor. Due to the presence of the internal electric field, diffusion of majority carriers is suppressed, and minority carriers drift under the action of the internal electric field. Under the combined action of drift and diffusion, carriers of the N-type semiconductor and the P-type semiconductor are gradually balanced, electrons and holes are gradually combined at the interface of the N region and the P region to generate a space charge region, and the carriers of the region are mutually combined, so that the stability is strong, and the mobility is poor, namely a depletion layer.
When there is no voltage between the gate and source of the JFET, the channel becomes a smooth path open to electron flow. However, when a voltage of reverse polarity is applied between the gate and the source, the opposite occurs, which reverse biases the PN junction and narrows the channel by increasing the depletion layer and may place the JFET in the off or pinch-off region. It can be seen that the parasitic resistance in the N-drift layer is large, the current density of SiC UMOS is small, and the conductivity is poor due to the presence of the parasitic JFET.
Example 2
A method of preparing SiC UMOS having a stepped CSL layer, referring to fig. 2,3, comprising:
s100, doping the upper layer of the N-drift layer to form a plurality of CSL layers;
the invention adopts an ion implantation mode to dope the upper layer of the N-drift layer to form a plurality of CSL layers. Ion implantation is the emission of an ion beam in vacuum towards a solid material, which, after being directed towards the solid material, is slowly slowed down by the resistance of the solid material and finally stays in the solid material. Ions of one element are accelerated into a solid target, thereby altering the physical, chemical or electrical properties of the target. Ion implantation is commonly used in the fabrication of semiconductor devices, metal surface treatment, and materials science research. If the ions stop and remain in the target, the ions change the elemental composition of the target (if the ions differ from the composition of the target). Various ion implantation beam line designs include a common set of functional elements. The main part of the ion beam line comprises an apparatus called ion source for generating ion species. The source is tightly coupled to a bias electrode to extract ions into the beam line and most commonly to some way of selecting a particular ion species for transmission into the main accelerator section. The "mass" selection is accompanied by the extracted ion beam passing through a region of the magnetic field whose exit path is limited by a blocked aperture or "slit" which allows only ions to have mass and velocity/charge to continue along the beam line. If the target surface is larger than the ion beam diameter and the implant dose is uniformly distributed over the target surface, some combination of beam scanning and wafer motion may be used. Finally, the implanted surface is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implantation process stopped at the desired dose level.
Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When implanted into a semiconductor, each doping atom may generate charge carriers in the semiconductor after annealing. A hole may be created for the P-type dopant and an electron may be created for the N-type dopant. The conductivity of the semiconductor near the doped region is changed.
The CSL layer can be formed by implanting N-type ions, and the specific method comprises the following steps of: cleaning the semiconductor surface; selecting ion species, in this step, pentavalent impurity ions such as P, as, sb, bi; accelerating ions, which are capable of penetrating the surface layer of the semiconductor material only when the impurity ions are accelerated to a certain energy; implanting ions; and annealing treatment, which is used for eliminating defects generated in the injection process and improving the electrical property of the semiconductor material.
S200, epitaxially forming a P-well layer, an N+ layer and a P+ layer above the CSL layer;
an epitaxial process refers to a process of growing a single crystal layer in complete alignment on a substrate. Generally, an epitaxial process is a process of growing a layer of crystals on a monocrystalline substrate that have the same lattice orientation as the original substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. Embedded source drain epitaxial growth of MOS transistors, epitaxial growth on LED substrates, and the like. According to the different phases of the growth source, the epitaxial growth modes are divided into solid phase epitaxy, liquid phase epitaxy and gas phase epitaxy. In integrated circuit fabrication, common epitaxy methods are solid phase epitaxy and vapor phase epitaxy.
Solid phase epitaxy refers to the process of growing a single crystal layer on a substrate by a solid source, such as thermal annealing after ion implantation, which is essentially a solid phase epitaxy process. During the implantation processing, silicon atoms of the silicon wafer are bombarded by high-energy implantation ions and are separated from the original lattice positions, and amorphization occurs to form a surface amorphous silicon layer; and then, after high-temperature thermal annealing, the amorphous atoms return to the lattice positions again and keep consistent with the crystal orientation of the atoms in the substrate.
The growth method of vapor phase epitaxy includes chemical vapor phase epitaxy (CVE), molecular beam epitaxy (MBD), atomic Layer Epitaxy (ALE), and the like. In an embodiment of the present invention, chemical Vapor Epitaxy (CVE) is used to form the N-drift layer. The chemical vapor phase epitaxy and Chemical Vapor Deposition (CVD) principles are basically the same, and are all processes for depositing films by utilizing chemical reaction on the surface of a wafer after gas mixing; in contrast, since the single crystal layer is grown by chemical vapor epitaxy, the impurity content in the apparatus and the cleanliness of the silicon wafer surface are both higher. CVE can also be used in epitaxial silicon wafer processes and MOS transistor embedded source drain epitaxial processes in integrated circuit fabrication. The epitaxial silicon wafer process is to epitaxial a layer of monocrystalline silicon on the surface of the silicon wafer, and compared with the original silicon substrate, the epitaxial silicon layer has higher purity and fewer lattice defects, so that the yield of semiconductor manufacture is improved. In addition, the growth thickness and doping concentration of the epitaxial silicon layer grown on the silicon wafer can be flexibly designed, which brings flexibility to the design of the device, such as being used for reducing the substrate resistance, enhancing the substrate isolation and the like. The embedded source-drain epitaxy process refers to a process of growing doped silicon germanium or silicon outside the source-drain region of the transistor. The main advantages of introducing the embedded source drain epitaxy process include: a pseudomorphic layer containing stress due to lattice adaptation can be grown, and channel carrier mobility is improved; the source and drain can be doped in situ, the parasitic resistance of the source and drain junction is reduced, and the defect of high-energy ion implantation is reduced.
S300, forming through holes in the P-well layer and the N+ layer, forming grooves in the upper layer of the N-drift layer, and connecting the through holes with the grooves;
the invention provides a method for etching through holes on a P-well layer and an N+ layer, and a groove is arranged on the upper layer of the N-drift layer, wherein the etching is a technology for removing part of materials by using chemical reaction or physical impact. Etching techniques can be classified into wet etching and dry etching. After exposure plate making and development, the protective film of the area to be etched is removed, and the protective film is contacted with a chemical solution during etching, so that the effect of dissolution and corrosion is achieved, and the effects of concave-convex or hollowed-out molding are formed.
The method comprises the following specific steps: exposure method: the engineering is to open the size of the prepared material according to the graph, prepare the material, clean the material, dry the material, paste the film or coat, dry the film, expose the light, develop, dry the film, etch and take off the film.
Screen printing method: cutting, cleaning a plate (stainless steel or other metal material), screen printing, etching and demoulding.
Etching: the anti-corrosion ink is printed on the surface of the material by adopting an ink-jet printing technology, and then the anti-corrosion layer can be obtained after curing (generally photo-curing and also useful thermal curing) and then the next chemical corrosion or electric corrosion can be carried out.
S400, depositing a metal electrode and an interlayer medium.
The specific steps of S400 are divided into a deposition grid electrode, a deposition source electrode and a deposition drain electrode, wherein the deposition grid electrode is divided into two steps of generating an oxide layer and polysilicon deposition, the oxide layer is generated by adopting a wet oxidation method, and the organic matters in water are oxidized into small molecular organic matters or inorganic matters by using gaseous oxygen (usually air) as an oxidant under the conditions of high temperature (120-320 ℃) and high pressure (0.5-20 MPa). The high temperature can improve the solubility of O2 in the liquid phase, and the purpose of the high pressure is to inhibit the evaporation of water to maintain the liquid phase, while the water in the liquid phase can act as a catalyst to allow the oxidation reaction to proceed at a lower temperature.
Polysilicon deposition is the formation of gate electrodes and local interconnects on a silicide stack on a first layer of polysilicon (Poly 1) and a second layer of polysilicon (Poly 2) forms contact plugs between source/drain and cell interconnects. The silicide is stacked on the third layer polysilicon (Poly 3) to form a cell connection, and the fourth layer polysilicon (Poly 4) and the fifth layer polysilicon (Poly 5) form two electrodes of the storage capacitor with a dielectric medium with high dielectric coefficient sandwiched therebetween. To maintain the desired capacitance value, the size of the capacitor may be reduced by using a dielectric with a high dielectric coefficient. Polysilicon deposition is a Low Pressure Chemical Vapor Deposition (LPCVD) that can be performed in-situ by directly introducing a dopant gas of arsenic trioxide (AH 3), phosphorus trioxide (PH 3), or diborane (B2H 6) into the silicon material gas of silane or DCS in a reaction chamber (i.e., in a furnace). Polysilicon deposition is performed at low pressure conditions of 0.2-1.0Torr and deposition temperatures between 600 and 650 ℃ using pure silane or silane diluted with nitrogen to a purity of 20% to 30%. The deposition rates of both deposition processes areIs mainly determined by the temperature during deposition.
Metal electrode deposition processes are classified into Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD). CVD refers to a process of chemically depositing a coating on the surface of a wafer, typically by applying energy to a gas mixture. Assuming that the substance (a) is deposited on the wafer surface, two gases (B and C) that can generate the substance (a) are first input to the deposition apparatus, and then energy is applied to the gases to cause the gases B and C to chemically react.
PVD (physical vapor deposition) coating techniques are mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of physical vapor deposition are: vacuum evaporation, sputter coating, arc plasma coating, ion coating, molecular beam epitaxy, and the like. The corresponding vacuum coating equipment comprises a vacuum evaporation coating machine, a vacuum sputtering coating machine and a vacuum ion coating machine.
Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD) can be used as a means of depositing metal electrodes. In the embodiment of the invention, a chemical vapor deposition method is adopted to deposit the metal electrode, and the chemical vapor deposition process is divided into three stages: the reaction gas diffuses toward the surface of the substrate, the reaction gas is adsorbed on the surface of the substrate, and chemical reaction occurs on the surface of the substrate to form solid deposits, and the generated gas phase byproducts are separated from the surface of the substrate. The most common chemical vapor deposition reactions are thermal decomposition reactions, chemical synthesis reactions, chemical transport reactions, and the like. TiC or TiN is usually deposited by introducing TiCl into a reaction chamber at 850-1100 DEG C 4 ，H 2 ，CH 4 And forming a coating layer on the surface of the substrate through chemical reaction of the gases.
Preferably, after the N-drift layer is doped to form a plurality of CSL layers, the method further comprises: and doping the upper layer of the N-drift layer to form a P+ shielding layer.
In the embodiment of the invention, the P+ shielding layer is formed by doping the upper layer of the N-drift layer in an ion implantation mode. The P+ shielding layer can be formed by implanting P-type ions, and the specific method comprises the following steps of: cleaning the semiconductor surface; selecting ion species, and selecting trivalent impurity ions such as Al, ga and In the step; accelerating ions, which are capable of penetrating the surface layer of the semiconductor material only when the impurity ions are accelerated to a certain energy; implanting ions; and annealing treatment, which is used for eliminating defects generated in the injection process and improving the electrical property of the semiconductor material.
Because the P+ shielding layer forms a JFET with the P-well layer while protecting the gate oxide layer, parasitic resistance is increased, and the current density of the SiC UMOS is reduced; the multi-layer CSL layer is positioned below the P-well layer; the width of the multi-layer CSL layer decreases in a direction away from the P-well layer. Because PN junctions of the P+ shielding layer and the N-drift layer are widened at one side of the N-drift layer, a current path is limited, so that the stepped CSL layer is adopted to limit the widening of the PN junctions of the P+ shielding layer and the N-drift layer, thereby increasing an electron conduction path, improving the conductivity and increasing the current density of the SiC UMOS.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A SiC UMOS having a stepped CSL layer, comprising: a multi-layer CSL layer;
a plurality of CSL layers are positioned below the P-well layer;
the width of the plurality of CSL layers decreases in a direction away from the P-well layer.
2. A SiC UMOS having a stepped CSL layer according to claim 1, wherein the doping concentration of multiple layers of said CSL layer decreases in a direction away from the P-well layer.
3. The SiC UMOS with stepped CSL layer of claim 1, wherein the first CSL layer under the P-well layer has a width equal to the width of the P-well layer.
4. A SiC UMOS having a stepped CSL layer according to claim 1, wherein said CSL layer has a thickness of 0.2-0.3um.
5. The SiC UMOS with stepped CSL layer of claim 1, wherein said CSL has a doping concentration of at least 10 16 cm -3 。
6. The SiC UMOS with stepped CSL layer of claim 1, wherein said CSL has a doping concentration of at most 10 17 cm -3 。
7. A SiC UMOS having a stepped CSL layer as defined in claim 1, further comprising: the device comprises a source electrode, a drain electrode, a grid electrode, an N-type substrate, a P+ layer and an N+ layer;
the drain electrode is positioned below the N-type substrate;
the N-type substrate is positioned below the N-drift layer;
the N-drift layer is positioned below the P-well layer;
the P-well layer is positioned below the P+ layer and the N+ layer;
the P+ layer and the N+ layer are located below the source electrode;
the N+ layer and the P-well layer are provided with through holes;
the groove is arranged on the upper layer of the N-drift layer and is connected with the through hole;
the gate is located in the trench.
8. A SiC UMOS having a stepped CSL layer as defined in claim 7, further comprising: a P+ shielding layer;
the P+ shielding layer is located below the groove.
9. A method of preparing a SiC UMOS having a stepped CSL layer, comprising:
doping the upper layer of the N-drift layer to form a plurality of CSL layers;
epitaxially forming a P-well layer, an N+ layer and a P+ layer above the CSL layer;
a through hole is formed in the P-well layer and the N+ layer, a groove is formed in the upper layer of the N-drift layer, and the through hole is connected with the groove;
a metal electrode and an interlayer dielectric are deposited.
10. The method of preparing a SiC UMOS having a stepped CSL layer of claim 9, wherein after forming a plurality of CSL layers by upper layer doping of the N-drift layer, further comprising: and doping the upper layer of the N-drift layer to form a P+ shielding layer.
CN202311068358.3A 2023-08-23 2023-08-23 SiC UMOS with stepped CSL layer and preparation method Pending CN117317007A (en)

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