CN117423730A - sJ SiC VDMOS with split gate and preparation method thereof - Google Patents
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Abstract
The invention provides an SJ SiC VDMOS with split gates and a preparation method thereof, wherein the SJ SiC VDMOS comprises the following components: a silicon layer and split gates; the silicon layer includes: a first body region, an n+ region, a p+ region, and a first N pillar; the silicon layer is positioned between the silicon carbide layer and the source electrode and the grid electrode oxide layer and is adjacent to the source electrode and the grid electrode oxide layer; the split gate is located on the side of the gate and is covered by the gate oxide layer. According to the invention, the silicon material is deposited above the N column made of the silicon carbide material, so that the channel is prepared in the silicon material, and the channel has higher channel mobility in the silicon material because the channel mobility of silicon is higher than that of silicon carbide, and the SJ SiC VDMOS device also has high breakdown voltage caused by the silicon carbide material, and the split gate structure can reduce the relative area of a gate and a drain electrode, and reduce the gate-drain capacitance, so that the switching frequency of the SJ SiC MOS is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an SJ SiC VDMOS with a split gate and a preparation method thereof.
Background
The third-generation semiconductor material silicon carbide has the characteristics of wide band gap, high breakdown field intensity, high heat conductivity, high saturated electron migration rate, stable physical and chemical properties and the like, and can be suitable for high-temperature, high-frequency, high-power and extreme environments. Silicon carbide has a larger forbidden bandwidth and a higher critical breakdown field strength. Compared with a silicon power device under the same condition, the withstand voltage degree of the silicon carbide device is about 10 times of that of a silicon material.
Channel mobility is one of the important parameters of SiC MOSFETs, and refers to the mobility of electrons or holes in the channel under the action of an electric field. In a MOSFET, channel mobility determines the transmission efficiency and speed of current. The higher the channel mobility, the faster the electron or hole mobility in the channel, and the better the conductivity of the device. Factors influencing channel mobility are: the characteristics of silicon carbide materials, which have higher electron mobility and saturation drift velocity, result in SiC MOSFETs with higher channel mobility. In contrast, conventional silicon-based materials have lower mobility, limiting device performance. Channel structure and dimensions, which also have a significant impact on channel mobility. Shorter channel lengths and smaller channel widths may reduce current scattering in the channel, thereby improving channel mobility. Surface and interface states refer to the channel surface and the charge state between the channel and the insulating layer. These charge states affect the mobility of electrons or holes in the channel and thus the channel mobility. By optimizing materials and processes, the influence of surface states and interface states can be reduced, and the channel mobility can be improved.
The current methods for optimizing channel mobility are as follows: optimizing the material, selecting silicon carbide materials with higher channel mobility, such as 4H-SiC or 6H-SiC, can improve the performance of the device. By optimizing the structure and the size, the scattering of current in the channel can be reduced and the channel mobility can be improved by reducing the channel length and the channel width. And the optimization process is adopted, so that the influence of surface states and interface states is reduced, and the channel mobility can be improved. Reducing the temperature, when using SiC MOSFETs in a high temperature environment, heat dissipation measures may be taken or the operating temperature may be reduced to reduce the effect of temperature on channel mobility. However, the improvement of the channel mobility by the methods still cannot meet the current industrial production requirements.
Disclosure of Invention
The invention aims to provide an SJ SiC VDMOS with a split gate and a preparation method thereof, wherein a silicon material is deposited above an N column made of a silicon carbide material, so that a channel is prepared in the silicon material, the channel has higher channel mobility in the silicon material because the channel mobility of silicon is higher than that of silicon carbide, and the SJ SiC VDMOS device also has high breakdown voltage brought by the silicon carbide material.
A SJ SiC VDMOS with split gate, comprising: a silicon layer and split gates;
the silicon layer includes: a first body region, an n+ region, a p+ region, and a first N pillar;
the silicon layer is positioned between the silicon carbide layer and the source electrode and the grid electrode oxide layer and is adjacent to the source electrode and the grid electrode oxide layer;
the split gate is located on the side of the gate and is covered by the gate oxide layer.
Preferably, the method further comprises: an electron tunneling layer;
the electron tunneling layer is located below and adjacent to the silicon layer.
Preferably, the first body region includes a first extension under and adjoining the source and a second extension under and adjoining the n+ and p+ regions.
Preferably, the method further comprises: a silicon carbide layer;
the silicon carbide layer includes: a second body region, a second N pillar, and a substrate;
the second body region is positioned between the first body region and the second N column and is adjacent to the first body region and the second N column;
the silicon carbide layer is located between the drain electrode and the silicon layer and is adjacent to the silicon layer and the drain electrode.
Preferably, the doping concentration of the electron tunneling layer is 10 19 cm -3 。
Preferably, the thickness of the first N pillar is equal to the thickness of the silicon layer;
the thickness of the first N column is 0.1um.
Preferably, the silicon carbide layer has a thickness of 12um.
Preferably, the method further comprises: source, drain, gate, substrate, P column, n+ region and p+ region;
the drain electrode is positioned below the substrate;
the substrate is positioned below the P column and the second N column;
the source electrode is positioned above the silicon layer;
the P+ region is located below the source electrode;
the N+ region is positioned below the grid electrode and the source electrode;
the gate is located between the source and the silicon layer.
A preparation method of an SJ SiC VDMOS with split gates comprises the following steps:
epitaxial silicon carbide layer above the substrate and ion implantation to form P column, second body region and second N column;
epitaxial a silicon layer over the silicon carbide layer;
ion implantation is carried out in the silicon layer to form a first body region, a P+ region and an N+ region;
source, drain, gate and split gate are deposited.
Preferably, the epitaxial silicon carbide layer above the substrate and ion implantation to form a P pillar, a second body region, and a second N pillar further comprises: and forming an electron tunneling layer by ion implantation on the upper layer of the silicon carbide layer.
According to the invention, by utilizing the characteristic that a silicon material has higher channel mobility than a silicon carbide material, a part of silicon carbide layer of the planar SiC VDMOS is replaced by the silicon layer, so that a channel falls into the silicon material, and the channel mobility of the planar SiC VDMOS is improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a schematic diagram of the SJ SiC VDMOS structure of the present invention;
FIG. 2 is a schematic diagram of a preparation flow method of the SJ SiC VDMOS of the invention;
fig. 3 is a schematic diagram of a preparation flow structure of the SJ SiC VDMOS of the present invention.
Reference numerals illustrate:
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
The current methods for optimizing silicon carbide-based channel mobility are as follows: optimizing the material, selecting silicon carbide materials with higher channel mobility, such as 4H-SiC or 6H-SiC, can improve the performance of the device. By optimizing the structure and the size, the scattering of current in the channel can be reduced and the channel mobility can be improved by reducing the channel length and the channel width. And the optimization process is adopted, so that the influence of surface states and interface states is reduced, and the channel mobility can be improved. Reducing the temperature, when using SiC MOSFETs in a high temperature environment, heat dissipation measures may be taken or the operating temperature may be reduced to reduce the effect of temperature on channel mobility. However, the above methods are relatively costly and the improvement of channel mobility still does not meet the current industrial production requirements.
According to the invention, by utilizing the characteristic that the silicon material has higher channel mobility than the silicon carbide material, part of the silicon carbide layer of the SiC VDMOS is replaced by the silicon layer, so that a channel falls into the silicon material, the channel mobility of the SiC VDMOS is improved, and because a Si/SiC heterojunction has higher potential barrier, electrons are not easy to pass through the potential barrier, an electron tunneling layer is additionally arranged between the silicon layer and the silicon carbide layer, so that electrons can easily pass through the Si/SiC interface, the heterojunction resistance is reduced, the on current is increased, and the electrical performance of the SiC VDMOS is remarkably improved.
A SJ SiC VDMOS with split gate, comprising: a silicon layer and split gate 13;
the silicon layer includes: first body region 14, n+ region 6, p+ region 3, and first N column 10;
MOSFETs can be classified into planar gate 5 MOSFETs and superjunction MOSFETs according to manufacturing processes, and a planar structure transistor has a disadvantage in that if a rated voltage is increased, a drift layer becomes thick, and thus on-resistance increases. The nominal voltage of the MOSFET depends on the width of the drift region in the vertical direction and the doping parameters. To increase the voltage rating, the width of the drift region is typically increased while the doping concentration is reduced, but this results in a significant increase in the on-resistance of the MOSFET. In order to solve the problem of the increase of on-resistance due to the increase of rated voltage, the super junction structure MOSFET has a structure in which a plurality of vertical PN junctions are arranged at the drain electrode 12 and the source electrode 9, with the result that low on-resistance is realized while maintaining high voltage. The existence of the super junction breaks through the theoretical limit of silicon greatly, and the higher the rated voltage is, the more obviously the on-resistance is reduced.
The manufacturing material of the MOSFET is usually silicon or silicon carbide, the silicon material has higher thermal stability and electrical property, so that the silicon MOSFET device has higher reliability and long-term stability in the working process, the silicon MOSFET is suitable for various application fields such as analog circuits, digital circuits, mixed signals and the like, the third-generation semiconductor material silicon carbide has larger band gap, can bear higher temperature and higher voltage, is suitable for high-temperature, high-frequency, high-voltage and high-power circuits, but the channel mobility of the silicon carbide MOSFET is lower than that of the silicon MOSFET by one order of magnitude.
The silicon layer is positioned between the silicon carbide layer and the source electrode 9 and the grid electrode oxide layer 4 and is adjacent to the source electrode 9 and the grid electrode oxide layer 4;
placing a silicon layer between the silicon carbide layer and the source 9 and gate oxide layer 4 can cause the channel to fall completely in the silicon layer, thereby improving the channel mobility of the SJ SiC VDMOS.
The split gate 13 is located laterally of the gate 5 and is surrounded by the gate oxide layer 4.
The split gate 13 divides the traditional gate into two, the split gate is the split gate 13, the original gate is the control gate, the split gate 13 does not influence the normal operation of the control gate, and when the SJ SiC VDMOS is turned off in the forward direction, charges near the gate 5 are uniformly distributed, so that a concentrated electric field cannot be generated. However, since the JFET region of the device is completely covered by the gate 5, a large amount of charges are generated between the gate and the drain, and the capacitance of the SJ SiC VDMOS, mainly the reverse transmission capacitance, is increased. To further increase the switching frequency and switching losses, smaller reverse transfer capacitance and gate drain charge are required, as the switching speed is determined by the rate of charging and discharging of the gate capacitance. In order to solve the above problems, the present invention adopts a SJ SiC VDMOS of a planar split gate structure, as shown in fig. 1. When the SJ SiC VDMOS of the planar split gate structure is turned off in the forward direction, charges are attracted to the gates with both ends negatively biased, an electric field is concentrated at the bottom terminal of the gates, and a high concentrated electric field is generated. The area of the grid above the JFET region of the device is greatly reduced, the charge between grid and drain is reduced, the switching frequency of the device is improved, and the switching loss is reduced.
Preferably, the method further comprises: an electron tunneling layer 7;
the electron tunneling layer 7 is located below and adjacent to the silicon layer.
The electron tunneling layer 7 is a heavily doped N-type silicon carbide layer, the doping types of silicon carbide are divided into P type and N type, and the ion concentration of heavy doping (high doping concentration) is generally 10 18 cm -3 The ion concentration of the light doping (low doping concentration) is generally less than 10 18 cm -3 P-type doping is a group IIIA element, such as: boron, aluminum, gallium, indium, thallium. The N-type is doped with elements of group VA, such as nitrogen, phosphorus, arsenic, antimony, bismuth and mira.
According to the invention, the electron tunneling layer 7 is arranged at the interface of the silicon carbide layer and the silicon layer, when the grid voltage is positive, electrons in the body region in the silicon layer can be attracted, so that the part of the first body region 14, which is close to the grid oxide layer 4, is changed into an inversion layer, and because the electron tunneling layer 7 is connected with the silicon layer and the silicon carbide layer, electrons can more easily pass through Si/SiC heterojunction, the Si/SiC heterojunction resistance is reduced, and the on-current is improved.
Preferably, the first body region 14 comprises a first extension below the source 9 and adjoining the source 9 and a second extension below the n+ region 6 and the p+ region 3 and adjoining the n+ region 6 and the p+ region 3.
The first extension and the second extension of the first body region 14 are both rectangular, the first extension of the first body region 14 is rectangular between the source 9 and the second body region 2 and adjacent to the source 9 and the second body region 2, and the second extension of the first body region 14 is rectangular below the n+ region 6 and the p+ region 3 and adjacent to the n+ region 6 and the p+ region 3.
The first body region 14 is completely located in the silicon layer and covers the n+ region 6 and the p+ region 3, the n+ region 6 and the p+ region 3 in the silicon layer are respectively adjacent to the source electrode 9, the n+ region 6 and the source electrode 9 form ohmic contact, the p+ region 3 and the source electrode 9 form schottky contact, and the contact surface of the metal and the semiconductor is divided into two types of schottky contact and ohmic contact. Ohmic contacts are low barrier layers formed when a semiconductor with high doping concentration is contacted with a metal when the semiconductor is high in doping concentration, electrons can pass through the barrier layers by means of tunneling effect, and therefore low-resistance ohmic contacts are formed.
During normal operation of the SJ SiC VDMOS, the gate 5 opens an inversion layer in a body region of the silicon layer, and current can flow from the n+ region 6 to the source 9 to form a loop, where the n+ region 6 is heavily doped, and is easier to form ohmic contact with the source 9, and the p+ is also heavily doped, and is easier to form schottky contact with the source 9, and as a preferred embodiment, the doping concentration of the n+ region 6 is set to 10 20 cm -3 The doping concentration of the P+ region 3 is set to 10 19 cm -3 。
Preferably, the method further comprises: a silicon carbide layer;
the silicon carbide layer includes: a second body region 2, a second N pillar 8, and a substrate 11;
in the invention, the material of the N column and part of the body region is silicon carbide, and the material of the substrate 11 is also silicon carbide, because the silicon carbide has the characteristics of wide band gap, high breakdown field strength, high heat conductivity, high saturated electron migration rate, stable physical and chemical properties and the like, and can be suitable for high-temperature, high-frequency, high-power and extreme environments. Silicon carbide has a larger forbidden bandwidth and a higher critical breakdown field strength. Compared with a silicon power device under the same condition, the withstand voltage degree of the silicon carbide device is about 10 times of that of a silicon material. The invention has the advantages of silicon carbide MOSFETs while having high channel mobility.
The second body region 2 is located between the first body region 14 and the second N-pillar 8 and is contiguous with the first body region 14 and the second N-pillar 8;
the body region is made of two materials, namely a first body region 14 made of silicon material and a second body region 2 made of silicon carbide material, wherein the first body region 14 is completely positioned in a silicon layer, the second body region 2 is completely positioned in the silicon carbide layer, in the preparation process of the SJ SiC VDMOS, firstly, the silicon carbide layer and the silicon layer are sequentially and epitaxially grown above a substrate 11, then ion implantation is carried out to form each region, the second body region 2 and the first body region 14 are formed together through ion implantation during the preparation, and the effect of the second body region 2 is that the first body region 14 positioned below an N+ region 6 and a P+ region 3 is thinner, so that the electric leakage of the SJ SiC VDMOS can be possibly caused, and the second body region 2 is arranged below the first body region 14, so that the electric leakage of the SJ SiC VDMOS is prevented, and the reliability of the SJ SiC VDMOS is remarkably improved.
The silicon carbide layer is located between the drain electrode 12 and the silicon layer and is adjacent to the silicon layer and the drain electrode 12.
In the invention, the SJ SiC VDMOS is mainly made of three materials, namely a substrate 11 made of silicon carbide material, a second N column 8, a P column 1 and the like, an N+ region 6, a P+ region 3, a first body region 14, a first N column 10 and the like which are made of silicon material, an electrode made of metal, a source electrode 9 which is connected with a silicon layer, then the silicon layer is connected with a silicon carbide layer, and a drain electrode 12 which is connected with the silicon carbide layer, when the SJ SiC VDMOS works normally, current flows from the drain electrode 12 to the silicon carbide layer, then passes through a heterojunction of silicon and silicon carbide to the silicon layer, and finally flows from the silicon layer to the source electrode 9.
Preferably, the doping of the electron tunneling layer 7The impurity concentration is 10 19 cm -3 。
The thickness and doping concentration of the electron tunneling layer 7 influence the size of the Si/SiC heterojunction resistance, the larger the thickness of the electron tunneling layer 7 is, the smaller the Si/SiC heterojunction resistance is, the smaller the thickness of the electron tunneling layer 7 is, the larger the Si/SiC heterojunction resistance is, and if the thickness of the electron tunneling layer 7 is too large. The field intensity at the position of the electron tunneling layer 7 is overlarge, so that the problem of advanced breakdown of VDMOS is caused, the doping concentration of the electron tunneling layer 7 is larger, the Si/SiC heterojunction resistance is smaller, the doping concentration of the electron tunneling layer 7 is smaller, the Si/SiC heterojunction resistance is larger, if the doping concentration of the electron tunneling layer 7 is overlarge, the problem of partial electric leakage at the position of the electron tunneling layer 7, so that failure of SJ SiC VDMOS is caused, and as a preferable embodiment, the thickness of the electron tunneling layer 7 is set to be 0.07um, and the ion concentration of the electron tunneling layer 7 is set to be 10 19 cm -3 。
Preferably, the thickness of the first N-pillar 10 is equal to the thickness of the silicon layer, and the thickness of the first N-pillar 10 is also equal to the thickness of the first body region 14.
The thickness of the silicon layer is not excessively wide, and if the thickness of the silicon layer is excessively wide, various performances of the VDMOS such as high temperature characteristics, high frequency characteristics, switching characteristics, on-loss and the like are reduced, particularly, the breakdown voltage performance is greatly reduced, so that the silicon layer only needs to be minimum on the premise of ensuring that the trench is completely in the silicon layer, and as a preferred embodiment, the thickness of the silicon layer is set to be 0.1um, so that the simultaneous thickness of the trench completely in the silicon layer can be minimum.
The thickness of the first N pillar 10 is 0.1um.
When the SJ SiC VDMOS is in an off state, the body area is in a high-resistance state, electric leakage of the SJ SiC VDMOS can be prevented, current cannot pass through the MOSFET, when the SJ SiC VDMOS is in an on state, the grid electrode 5 opens a current channel in the body area, so that current can flow from the drain electrode 12 to the source electrode 9, the doping concentration of the body area determines the starting voltage of the SJ SiC VDMOS, the larger the doping concentration of the body area is, the larger the starting voltage of the SJ SiC VDMOS is, the thickness of the body area also influences the starting voltage of the SJ SiC VDMOS, the larger the thickness of the body area is, and S isThe larger the turn-on voltage of the J SiC VDMOS is, if the doping concentration or the thickness of the body region is too small, the situation that electric leakage occurs in the SJ SiC VDMOS can be caused, and as a preferred embodiment, the doping concentration of the body region is set to be 10 18 cm -3 The thickness of the first body region 14 is set to 0.1um.
Preferably, the silicon carbide layer has a thickness of 12um.
The thickness of the silicon carbide layer includes the thickness of the second N pillar 8 and the thickness of the substrate 11, and in the SJ SiC VDMOS epitaxial layer, the thickness of the silicon carbide layer affects the voltage-resistant performance of the SJ SiC VDMOS and the chip area, the thicker the silicon carbide layer, the larger the area of the drift region, the better the voltage-resistant performance of the SJ SiC VDMOS, but the larger the chip area, so the thickness of the silicon carbide layer should not be too large, and according to the electrical performance required by the SJ SiC VDMOS, as a preferred embodiment, the thickness of the silicon carbide layer is set to 12um.
Preferably, the method further comprises: a source 9, a drain 12, a gate 5, a substrate 11, a P pillar 1, an n+ region 6, and a p+ region 3;
the drain 12 is located under the substrate 11;
drain 12 is the charge sink in the MOSFET, which is connected to the channel and is the charge sink. When the MOSFET is in the on state, a conductive path is formed between the drain 12 and the source 9, and electrons flow from the source 9 into the drain 12, completing the current transfer. The voltage change of the drain 12 has less influence on the operation state of the MOSFET, and mainly plays a role of current inflow.
The substrate 11 is positioned below the P pillars 1 and the second N pillars 8;
the substrate 11 is a material for supporting crystal generation in the MOSFET, and the substrate 11 plays a role of mechanical support. In the present invention, the substrate 11 is made of a silicon carbide material, and its mechanical strength and stability can effectively support various stresses and distortions during crystal growth. This is critical to ensure uniformity and integrity of crystal growth. In addition, the substrate 11 can also prevent impurities and defects during crystal growth, thereby improving the quality of the MOSFET. Second, the substrate 11 plays an important role in the electrical performance of the MOSFET. The electrical properties of the substrate 11 determine the performance and stability of the device when the MOSFET is fabricated. For example, the conductivity of the substrate 11 directly affects the efficiency and speed of current transport. In addition, the electron affinity and the forbidden band width of the substrate 11 are also critical for adjusting the threshold voltage and electron mobility of the MOSFET. In addition, the substrate 11 also plays an important role in isolating the insulating layer of the MOSFET. During MOSFET fabrication, the insulating layer of the substrate 11 is typically composed of silicon dioxide. The quality and characteristics of the insulating layer directly affect the insulating properties of the MOSFET, such as electrical insulation and capacitive characteristics. The good insulating layer can effectively isolate different electrodes in the MOSFET structure and reduce leakage current and capacitive coupling effect.
The source electrode 9 is positioned above the silicon layer;
the source 9 is the source of charge in the MOSFET and is the outlet for the charge. When the MOSFET is in the on state, a conductive path is formed between the source electrode 9 and the drain electrode 12, and electrons flow from the source electrode 9 into the drain electrode 12, completing the current transmission. At the same time, the source electrode 9 also plays a role of modulating the gate voltage, and the control of the MOSFET is realized by controlling the change of the source electrode voltage.
The P+ region 3 is positioned below the source electrode 9;
the n+ region 6 is located under the gate 5 and the source 9;
the gate 5 is located between the source 9 and the silicon layer.
The gate 5 is the control electrode in the MOSFET, and is separated from the channel by an insulating layer, which is a critical part of the MOSFET. The voltage variation of the gate 5 can change the charge density in the channel and thus control the magnitude of the current between the drain 12 and the source 9.
Example 2
A method for preparing SJ SiC VDMOS with split gate, referring to fig. 2 and 3, comprising:
s100, a silicon carbide layer is epitaxially grown above a substrate 11 and ion implantation is performed to form a P column 1, a second body region 2 and a second N column 8;
the invention adopts an ion implantation mode to form the P column 1, the second body region 2 and the second N column 8. Ion implantation is the emission of an ion beam in vacuum towards a solid material, which, after being directed towards the solid material, is slowly slowed down by the resistance of the solid material and finally stays in the solid material. Ions of one element are accelerated into a solid target, thereby altering the physical, chemical or electrical properties of the target. Ion implantation is commonly used in the fabrication of semiconductor devices, metal surface treatment, and materials science research. If the ions stop and remain in the target, the ions change the elemental composition of the target (if the ions differ from the composition of the target). The ion implantation beam line design includes a common set of functional elements. The main part of the ion beam line comprises an apparatus called ion source for generating ion species. The source is tightly coupled to a bias electrode to extract ions into the beam line and most commonly to some way of selecting a particular ion species for transmission into the main accelerator section. The mass selection is accompanied by the extracted ion beam passing through a region of the magnetic field whose exit path is limited by a blocking aperture or slit which only allows ions to have mass and velocity/charge to continue along the beam line. If the target surface is larger than the ion beam diameter and the implant dose is uniformly distributed over the target surface, some combination of beam scanning and wafer motion may be used. Finally, the implanted surface is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implantation process stopped at the desired dose level.
Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When implanted into a semiconductor, each doping atom may generate charge carriers in the semiconductor after annealing. A hole may be created for the P-type dopant and an electron may be created for the N-type dopant. The conductivity of the semiconductor near the doped region is changed.
S200, extending a silicon layer above the silicon carbide layer;
the epitaxial process refers to a process of growing a single crystal layer in complete alignment on the substrate 11, and is an epitaxial process of growing a crystal layer in the same lattice orientation as the original substrate on the single crystal substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. The epitaxial growth modes are classified into solid phase epitaxy, liquid phase epitaxy and gas phase epitaxy according to the different phase states of the growth source. In integrated circuit fabrication, common epitaxy methods are solid phase epitaxy and vapor phase epitaxy.
Solid phase epitaxy refers to the process of growing a single crystal layer on a substrate by a solid source, such as thermal annealing after ion implantation, which is essentially a solid phase epitaxy process. During ion implantation processing, silicon atoms of the silicon wafer are bombarded by high-energy implantation ions and are separated from the original lattice positions, amorphization occurs, and a surface amorphous silicon layer is formed; and then, after high-temperature thermal annealing, the amorphous atoms return to the lattice positions again and keep consistent with the crystal orientation of the atoms in the substrate.
The growth method of vapor phase epitaxy includes chemical vapor phase epitaxy (CVE), molecular beam epitaxy (MBD), atomic Layer Epitaxy (ALE), and the like. In an embodiment of the present invention, chemical Vapor Epitaxy (CVE) is used to form the N-drift layer. The principle of chemical vapor epitaxy is basically the same as that of Chemical Vapor Deposition (CVD), and the process of depositing a film is carried out by mixing gases and then carrying out chemical reaction on the surface of a wafer; in contrast, since the single crystal layer is grown by chemical vapor epitaxy, the impurity content in the apparatus and the cleanliness of the silicon wafer surface are both higher. CVE can also be used in epitaxial silicon wafer processes and MOS transistor embedded source drain epitaxial processes in integrated circuit fabrication. The epitaxial silicon wafer process is to epitaxial a layer of monocrystalline silicon on the surface of the silicon wafer, and compared with the original silicon substrate, the epitaxial silicon layer has higher purity and fewer lattice defects, so that the yield of semiconductor manufacture is improved. In addition, the growth thickness and doping concentration of the epitaxial silicon layer grown on the silicon wafer can be flexibly designed, which brings flexibility to the design of the device, such as being used for reducing the substrate resistance, enhancing the substrate isolation and the like. The embedded source-drain epitaxy process refers to a process of growing doped silicon germanium or silicon outside the source-drain region of the transistor. The main advantages of introducing the embedded source drain epitaxy process include: a pseudomorphic layer containing stress due to lattice adaptation can be grown, and channel carrier mobility is improved; the source and drain can be doped in situ, the parasitic resistance of the source and drain junction is reduced, and the defect of high-energy ion implantation is reduced.
S300, forming a first body region 14, a P+ region 3 and an N+ region 6 in the silicon layer by ion implantation;
s400, depositing a source 9, a drain 12, a gate 5 and a split gate 13.
Metal electrode deposition processes are classified into Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD). CVD refers to a process of chemically depositing a coating on the surface of a wafer, typically by applying energy to a gas mixture. Assuming that the substance (a) is deposited on the wafer surface, two gases (B and C) that can generate the substance (a) are first input to the deposition apparatus, and then energy is applied to the gases to cause the gases B and C to chemically react.
PVD (physical vapor deposition) coating techniques are mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of physical vapor deposition are: vacuum evaporation, sputter coating, arc plasma coating, ion coating, molecular beam epitaxy, and the like. The corresponding vacuum coating equipment comprises a vacuum evaporation coating machine, a vacuum sputtering coating machine and a vacuum ion coating machine.
Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD) can be used as a means of depositing metal electrodes. In the embodiment of the invention, a chemical vapor deposition method is adopted to deposit the metal electrode, and the chemical vapor deposition process is divided into three stages: the reaction gas diffuses toward the surface of the substrate, the reaction gas is adsorbed on the surface of the substrate, and chemical reaction occurs on the surface of the substrate to form solid deposits, and the generated gas phase byproducts are separated from the surface of the substrate. The most common chemical vapor deposition reactions are thermal decomposition reactions, chemical synthesis reactions, chemical transport reactions, and the like.
The deposited gate electrode adopts a polysilicon deposition method, namely, a gate electrode and local connection lines are formed on the silicide stack on the first layer of polysilicon (Poly 1), and the second layer of polysilicon (Poly 2) forms contact plugs between the source electrode 9/drain electrode 12 and the cell connection lines. The silicide is stacked on the third layer polysilicon (Poly 3) to form a cell connection, and the fourth layer polysilicon (Poly 4) and the fifth layer polysilicon (Poly 5) form two electrodes of the storage capacitor with a dielectric medium with high dielectric coefficient sandwiched therebetween. To maintain the desired capacitance value, the size of the capacitor may be reduced by using a dielectric with a high dielectric coefficient. Polysilicon deposition is a low pressureChemical Vapor Deposition (LPCVD) is performed by depositing arsenic trioxide (AH) in a reaction chamber (i.e., in a furnace tube) 3 ) Phosphorus trihydride (PH) 3 ) Or diborane (B) 2 H 6 ) The doping gas of the silicon material is directly input into the silicon material gas of silane or DCS, so that the polysilicon doping process of the in-situ low-pressure chemical vapor deposition can be performed. Polysilicon deposition is performed at low pressure conditions of 0.2-1.0Torr and deposition temperatures between 600 and 650 ℃ using pure silane or silane diluted with nitrogen to a purity of 20% to 30%. The deposition rate of both deposition processes is between 100-200 a/min, which is determined primarily by the temperature at which the deposition is performed.
Preferably, S100, a silicon carbide layer is epitaxially grown over the substrate 11 and ion-implanted to form P pillars 1, second body regions 2, and second N pillars 8, further comprising: an electron tunneling layer 7 is formed by ion implantation on the upper layer of the silicon carbide layer.
The electron tunneling layer 7 is formed by ion implantation after the P column 1 and the second N column 8 are formed, and the position of the electron tunneling layer 7 is located at the upper layer of the second N column 8.
According to the invention, by utilizing the characteristic that a silicon material has higher channel mobility than a silicon carbide material, a part of silicon carbide layer of the planar SiC VDMOS is replaced by the silicon layer, so that a channel falls into the silicon material, and the channel mobility of the planar SiC VDMOS is improved, and because a Si/SiC heterojunction has higher potential barrier, electrons are not easy to pass through the potential barrier, an electron tunneling layer 7 is additionally arranged between the silicon layer and the silicon carbide layer, so that electrons can easily pass through a Si/SiC interface, the heterojunction resistance is reduced, the on-state current is increased, the electrical performance of the SJ SiC VDMOS is remarkably improved, a split gate structure is also introduced, the relative area between a gate 5 and a drain 12 can be reduced, the capacitance between the gate 5 and the drain 12 is reduced, and the switching frequency of the SJ SiC MOS is improved.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A SJ SiC VDMOS with split gates, comprising: a silicon layer and split gates;
the silicon layer includes: a first body region, an n+ region, a p+ region, and a first N pillar;
the silicon layer is positioned between the silicon carbide layer and the source electrode and the grid electrode oxide layer and is adjacent to the source electrode and the grid electrode oxide layer;
the split gate is located on the side of the gate and is covered by the gate oxide layer.
2. A SJ SiC VDMOS with split gates according to claim 1, further comprising: an electron tunneling layer;
the electron tunneling layer is located below and adjacent to the silicon layer.
3. The SJ SiC VDMOS with split gate of claim 1, wherein the first body region includes a first extension below and contiguous with the source and a second extension below and contiguous with the n+ and p+ regions.
4. A SJ SiC VDMOS with split gates according to claim 1, further comprising: a silicon carbide layer;
the silicon carbide layer includes: a second body region, a second N pillar, and a substrate;
the second body region is positioned between the first body region and the second N column and is adjacent to the first body region and the second N column;
the silicon carbide layer is located between the drain electrode and the silicon layer and is adjacent to the silicon layer and the drain electrode.
5. The SJ SiC VDMOS with split gate of claim 2 wherein the electron tunneling layer has a doping concentration of 10 19 cm -3 。
6. The SJ SiC VDMOS with split gate of claim 1, wherein the thickness of the first N pillar is equal to the thickness of the silicon layer;
the thickness of the first N column is 0.1um.
7. The SJ SiC VDMOS with split gate of claim 4 wherein the silicon carbide layer has a thickness of 12um.
8. A SJ SiC VDMOS with split gates according to claim 1, further comprising: source, drain, gate, substrate, P column, n+ region and p+ region;
the drain electrode is positioned below the substrate;
the substrate is positioned below the P column and the second N column;
the source electrode is positioned above the silicon layer;
the P+ region is located below the source electrode;
the N+ region is positioned below the grid electrode and the source electrode;
the gate is located between the source and the silicon layer.
9. The preparation method of the SJ SiC VDMOS with the split gate is characterized by comprising the following steps of:
epitaxial silicon carbide layer above the substrate and ion implantation to form P column, second body region and second N column;
epitaxial a silicon layer over the silicon carbide layer;
ion implantation is carried out in the silicon layer to form a first body region, a P+ region and an N+ region;
source, drain, gate and split gate are deposited.
10. The method of claim 9, wherein the step of forming P pillars, second body regions, and second N pillars by epitaxially growing a silicon carbide layer over the substrate and ion implanting, further comprises: and forming an electron tunneling layer by ion implantation on the upper layer of the silicon carbide layer.
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