CN117334747A - SiC planar MOS of source electrode groove integrated SBD and preparation method - Google Patents

SiC planar MOS of source electrode groove integrated SBD and preparation method Download PDF

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CN117334747A
CN117334747A CN202311632899.4A CN202311632899A CN117334747A CN 117334747 A CN117334747 A CN 117334747A CN 202311632899 A CN202311632899 A CN 202311632899A CN 117334747 A CN117334747 A CN 117334747A
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layer
region
source
source electrode
planar mos
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乔凯
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Shenzhen Sirius Semiconductor Co ltd
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Shenzhen Sirius Semiconductor Co ltd
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Abstract

The invention provides a SiC planar MOS of a source electrode groove integrated SBD and a preparation method thereof, wherein the SiC planar MOS comprises the following components: a schottky metal; the Schottky metal is positioned between the N-drift layer and the source electrode; the schottky metal is attached to the bottom wall of the source trench and abuts the source and drift layers. According to the invention, the Schottky diode is connected in anti-parallel to the two side walls at the bottom of the source electrode groove, the starting voltage of the Schottky diode is far smaller than that of the body diode, the Schottky diode can be started under lower voltage drop when the SiC planar MOS is in a reverse state, a reverse freewheeling effect is achieved under the condition that the area of a chip is not increased, and the reversing capability of the SiC planar MOS is remarkably improved.

Description

SiC planar MOS of source electrode groove integrated SBD and preparation method
Technical Field
The invention relates to the technical field of semiconductors, in particular to a SiC planar MOS of a source trench integrated SBD and a preparation method thereof.
Background
The third-generation semiconductor material silicon carbide has the characteristics of wide band gap, high breakdown field intensity, high heat conductivity, high saturated electron migration rate, stable physical and chemical properties and the like, and can be suitable for high-temperature, high-frequency, high-power and extreme environments. Silicon carbide has a larger forbidden bandwidth and a higher critical breakdown field strength. Compared with a silicon power device under the same condition, the withstand voltage degree of the silicon carbide device is about 10 times of that of a silicon material. In addition, the silicon carbide device has higher electron saturation rate, small forward on-resistance and lower power loss, is suitable for large-current and large-power application, and reduces the requirement on heat radiation equipment. Silicon carbide is more conveniently formed into silicon dioxide by thermal oxidation than other third generation semiconductors such as GaN. SiC has unique physical, chemical and electrical properties, and is a semiconductor material with great development potential in the extreme application fields of high temperature, high frequency, high power, radiation resistance and the like. The SiC power device has a series of advantages of high input impedance, high switching speed, high working frequency, high voltage resistance and the like, and is widely applied to the aspects of switching regulated power supplies, high frequency, power amplifiers and the like.
MOS field effect transistor power devices fabricated using silicon carbide materials can withstand higher voltages and faster switching speeds than Si devices. For conventional Si MOS, the body diode turn-on voltage is only around 0.7V, and is therefore commonly used as a freewheel channel under reverse bias of the MOSFET. However, the band gap of the SiC material is wider, the starting voltage of the SiC MOSFET body diode is too high (2.7-3.0V), and the SiC MOSFET is difficult to play a role in protecting the MOSFET under reverse bias. In the prior art, siC MOSFETs generally enhance the device freewheeling ability by shorting the body diode through an antiparallel schottky diode or JFET, but both methods occupy additional area, so that the chip area is increased, or the freewheeling channel is controlled to be turned on when the SiC MOS is inverted through a split gate, but the gate reliability is reduced, the process is complicated, the production cost is high, and the current density is low.
Disclosure of Invention
The invention aims to provide a SiC planar MOS of a source electrode groove integrated SBD and a preparation method thereof, wherein a Schottky diode is reversely connected in parallel to two side walls at the bottom of a source electrode groove by the SiC planar MOS, the starting voltage of the Schottky diode is far smaller than that of a body diode, the Schottky diode can be started under lower voltage drop when the SiC planar MOS is in a reverse state, the reverse freewheeling effect is achieved under the condition that the area of a chip is not increased, and the reversing capability of the SiC planar MOS is remarkably improved.
A SiC planar MOS of a source trench integrated SBD comprising: a schottky metal;
the Schottky metal is positioned between the N-drift layer and the source electrode;
the schottky metal is attached to the bottom wall of the source trench and abuts the source and drift layers.
Preferably, the method further comprises: a P+ shielding layer;
the P+ shielding layer is located below the Schottky metal and is adjacent to the Schottky metal and the drift layer.
Preferably, the schottky metal has a length of 0.6um.
Preferably, the schottky metal has a thickness of 0.2um.
Preferably, the doping concentration of the P+ shielding layer is 10 19 cm -3 To 10 20 cm -3 。
Preferably, the thickness of the p+ shielding layer is 0.5um.
Preferably, the distance between the bottom of the source trench and the body region is 0.4um to 0.6um.
Preferably, the method further comprises: the device comprises a source electrode, a drain electrode, a grid electrode, a substrate, an N-drift layer, a P-well layer, a P+ region and an N+ region;
the drain electrode is positioned below the substrate;
the substrate is positioned below the N-drift layer;
the N-drift layer is positioned below the P-well layer;
the P-well layer is positioned below the N+ region;
the N+ region is located below the source electrode;
the P+ region is positioned below the source electrode and is adjacent to the N+ region, the P-well layer and the N-drift layer;
the source electrode is positioned above the grid electrode, the N+ region and the P+ region;
the gate is located over the n+ region, the N-drift layer, and the P-well layer.
A preparation method of a SiC planar MOS of a source trench integrated SBD comprises the following steps:
epitaxially forming an N-drift layer over the substrate;
forming a P-well layer, an N+ region and a P+ region by ion implantation above the N-drift layer;
depositing a gate and ILD layer over the N-drift layer, the n+ region, the p+ region, and the P-well layer;
etching a through hole on the P+ region, and etching a groove on the N-drift layer, wherein the through hole is connected with the groove;
depositing schottky metal at the bottom of the groove;
and depositing a source electrode and a drain electrode.
Preferably, the etching of the via hole on the p+ region, after etching the trench on the N-drift layer, further includes:
and forming a P+ shielding layer by ion implantation on the upper layer of the N-drift layer.
According to the invention, the source electrode groove is formed in the P+ region towards the N-drift layer, the source electrode groove replaces part of the P+ region and the N-drift layer, the Schottky metal is deposited on the two side wall surfaces of the bottom of the source electrode groove, compared with the prior art, the Schottky diode in anti-parallel connection on a plane has smaller chip area, the Schottky metal on the two sides of the source electrode is larger than the reverse current of the Schottky metal on the single side of the source electrode, and the P+ shielding layer is arranged below the source electrode groove and is used for shielding a channel between the source electrode and the drain electrode due to the large electric field intensity below the source electrode groove, so that electric leakage is reduced, the electric field distribution in the drift layer can be improved by the P+ shielding layer, electric field peaks below the grid electrode are relieved, the grid electrode oxide layer is protected, and the reliability of the SiC planar MOS is remarkably improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic diagram of a SiC planar MOS structure of the present invention;
FIG. 2 is a schematic diagram of a process flow for preparing SiC planar MOS according to the present invention;
fig. 3 is a schematic structural diagram of a SiC planar MOS fabrication flow of the present invention;
FIG. 4 is a schematic view showing the structure of the SiC planar MOS along the AA' section of the invention;
fig. 5 is a schematic view of the structure of the SiC planar MOS of the present invention along BB' section.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
MOS field effect transistor power devices fabricated using silicon carbide materials can withstand higher voltages and faster switching speeds than Si devices. For conventional Si MOS, the body diode turn-on voltage is only around 0.7V, and is therefore commonly used as a freewheel channel under reverse bias of the MOSFET. However, the band gap of the SiC material is wider, the starting voltage of the SiC MOSFET body diode is too high (2.7-3.0V), and the SiC MOSFET is difficult to play a role in protecting the MOSFET under reverse bias. In the prior art, siC MOSFETs generally enhance the device freewheeling ability by shorting the body diode through an antiparallel schottky diode or JFET, but both methods occupy additional area, so that the chip area is increased, or the freewheeling channel is controlled to be turned on when the SiC MOS is inverted through a split gate, but the gate reliability is reduced, the process is complicated, the production cost is high, and the current density is low.
According to the invention, the source electrode groove is formed in the P+ region towards the N-drift layer, the source electrode groove replaces part of the P+ region and the N-drift layer, the Schottky metal is deposited on the two side wall surfaces of the bottom of the source electrode groove, compared with the prior art, the Schottky diode in anti-parallel connection on a plane has smaller chip area, the Schottky metal on the two sides of the source electrode is larger than the reverse current of the Schottky metal on the single side of the source electrode, and the P+ shielding layer is arranged below the source electrode groove and is used for shielding a channel between the source electrode and the drain electrode due to the large electric field intensity below the source electrode groove, so that electric leakage is reduced, the electric field distribution in the drift layer can be improved by the P+ shielding layer, electric field peaks below the grid electrode are relieved, the grid electrode oxide layer is protected, and the reliability of the SiC planar MOS is remarkably improved.
Example 1
A SiC planar MOS of a source trench integrated SBD, referring to fig. 1, 4, 5, comprising: schottky metal (Schottky);
the schottky metal is located between the N-drift layer (drift layer) and the source (S);
the contact surface of the metal and the semiconductor is classified into two types of schottky contact and ohmic contact. Ohmic contact is that when semiconductor doping concentration is high, a low barrier layer is formed when semiconductor with high doping concentration contacts metal, electrons can pass through the barrier by tunnel effect, so that ohmic contact with low resistance is formed, for example, an n+ region and a source electrode form ohmic contact. Ohmic contacts are characterized by a linear current-voltage characteristic of the contact surface and a negligible contact resistance relative to the bulk resistance of the semiconductor, resulting in a voltage drop less than the voltage drop across the device when current is passed.
The schottky contact is also made by utilizing the metal-semiconductor (M-S) contact characteristic, because the current transport of the metal-semiconductor contact mainly depends on majority carriers (electrons), the electron mobility is high, and the schottky junction can be precisely manufactured and processed on submicron scale, so that the schottky barrier diode can be applied to the sub-millimeter wave and terahertz wave frequency bands. The schottky diode is a metal-semiconductor device which is made of noble metal (gold, silver, aluminum, platinum, etc.) as a positive electrode, an N-type semiconductor as a negative electrode, and a rectifying characteristic utilizing a potential barrier formed on a contact surface of the two. Since a large number of electrons exist in the N-type semiconductor and only a very small number of free electrons exist in the noble metal, electrons diffuse from the semiconductor having a high concentration to the metal having a low concentration. There are no holes in the metal, i.e., there is no diffusion movement of holes from the metal to the semiconductor. As electrons continue to diffuse from the semiconductor to the metal, the electron concentration at the surface of the semiconductor gradually decreases, and the surface neutrality is broken, thus forming a potential barrier whose electric field direction is semiconductor→metal. However, under the action of the electric field, electrons in the metal also generate drift motion from metal to semiconductor, so that the electric field formed by diffusion motion is weakened. After a space charge region with a certain width is established, electron drift movement caused by an electric field and electron diffusion movement caused by different concentrations reach relative balance, and a Schottky barrier is formed. The internal circuit structure of a typical schottky rectifier is formed by using an N-type semiconductor as a substrate, and forming an N-epitaxial layer using arsenic as a dopant thereon. The anode is made of molybdenum or aluminum and other materials to form a barrier layer. With silicon dioxide (SiO) 2 ) So as to eliminate the electric field in the edge area and improve the withstand voltage of the pipe. The N-type substrate has a small on-state resistance, and an n+ cathode layer is formed below the substrate, which serves to reduce the contact resistance of the cathode. By adjusting the structural parameters, a Schottky barrier is formed between the N-type substrate and the anode metal. When a forward bias voltage (anode metal is connected with the positive electrode of the power supply, and N-type substrate is connected with the negative electrode of the power supply) is applied to the two ends of the Schottky barrier layerNarrowing, its internal resistance becomes small; conversely, if a reverse bias is applied to both ends of the schottky barrier, the schottky barrier layer becomes wider and its internal resistance becomes larger.
The work function of the metal is wm=e 0 -E Fm The work function of the semiconductor is ws=e 0 -E Fs ，E 0 At vacuum level, i.e. the energy of stationary electrons in vacuum, while work function W is at vacuum level E 0 And fermi level E F Difference of E Fm Fermi level of metal, E Fs The fermi level of a semiconductor is the minimum energy required for electrons of fermi level to escape from the material into the vacuum. The magnitude of the work function marks the strength of the binding capacity of the material to electrons. When the work function of the metal is larger than that of the N-type semiconductor, a very high electron barrier, namely a Schottky barrier, is formed on one side of the metal, electrons with energy higher than that of the barrier can flow from the metal to the semiconductor, and ideally the barrier height on one side of the metal is not changed along with bias, so that when the metal side is reversely biased, a very large interface resistance is generated, and when the metal side is positively biased, electrons flowing from the semiconductor to the metal become very small after overcoming the built-in potential, and the metal-semiconductor contact with different positive and negative characteristics becomes the Schottky contact. Ohmic contacts are formed when the work function of the metal is less than the work function of the N-type semiconductor. If the metal is in contact with the P-type semiconductor, an ohmic contact is formed when the work function of the metal is greater than that of the P-type semiconductor, and a schottky contact is formed when the work function of the metal is less than that of the P-type semiconductor.
In the embodiment of the invention, the Schottky metal adopts high work function metals such as titanium (Ti), nickel (Ni), chromium (Cr), gold (Au) and the like to form Schottky contact with the N-type silicon carbide semiconductor.
The schottky metal is attached to the bottom wall of the source trench and abuts the source and drift layers.
Preferably, the method further comprises: a P+ shielding layer;
the P+ shielding layer is located below the Schottky metal and is adjacent to the Schottky metal and the drift layer.
In the invention, the P+ shielding layer coats the bottom of the Schottky metal, is used for shielding a channel between the drain electrode and the source electrode, prevents electric leakage, can cause electric leakage of a device if the P+ shielding layer does not completely coat the bottom of the Schottky metal, and can protect the bottom of the source electrode groove from being broken down by a strong electric field due to the large electric field intensity of the bottom of the source electrode groove, and can change the electric field distribution of the bottom of the grid electrode groove, relieve the electric field peak at the bottom of the grid electrode groove, avoid the breakdown of the grid electrode oxide layer and improve the reliability of the grid electrode oxide layer.
Preferably, the schottky metal has a length of 0.6um.
The schottky metal length is the length of the main viewing surface of fig. 1 extending perpendicular to the direction of BB', and the contact area of the schottky diode determines its maximum current and power class. The schottky diode with large contact area has higher capacity and can bear larger current and power. This is important for high frequency applications and high power applications. The longer the length, the larger the area of the schottky diode, the stronger the reverse freewheeling ability, but if the length of the schottky metal is too large, the voltage withstanding capability of the planar SiC MOS is reduced, and the leakage condition of the planar SiC MOS is also caused, and as a preferred embodiment, the present invention sets the length of the schottky metal to 0.6um, and provides a sufficient reverse freewheeling path while guaranteeing the voltage withstanding capability and the working performance of the planar SiC MOS.
Preferably, the schottky metal has a thickness of 0.2um.
The thickness of the schottky metal affects the performance of the schottky diode, and the thinner the schottky metal is, the smaller the heat capacity and capacitance are, and thus the faster the response speed is, for the same material, with the same diameter. As a preferred embodiment, the present invention sets the thickness of the schottky metal to 0.2um.
Preferably, the doping concentration of the P+ shielding layer is 10 19 cm -3 To 10 20 cm -3 。
Silicon carbide doping types are classified into P-type and N-type, + is heavily doped (high doping concentration), -is lightly doped (low doping concentration), and P-type is doped with group IIIA elements, such as: boron, aluminum, gallium, indium, thallium. N-type doping with group VA elements such As nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi) and permangana (Mc).
The P+ shielding layer is a P-type heavily doped semiconductor, the P+ shielding layer blocks current from flowing from the bottom of the Schottky metal to prevent the super junction SiC MOS from leaking, if the doping concentration of the P+ shielding layer is too low, the super junction SiC MOS is caused to leak from the bottom of the Schottky metal, and as a preferable embodiment, the doping concentration of the P+ shielding layer is set to be 10 19 cm -3 The source trench can be protected from leakage and the reliability of the gate oxide layer at the bottom of the gate trench can be improved.
Preferably, the thickness of the p+ shield layer is 0.5um.
The thickness of the P+ shielding layer influences the shielding effect of the P+ shielding layer, the thicker the P+ shielding layer is, the stronger the shielding effect is, but if the thickness of the P+ shielding layer is too thick, the on-resistance of the super junction SiC MOS becomes larger, and as a preferable embodiment, the thickness of the P+ shielding layer is set to be 0.5um, the leakage of the super junction SiC MOS is prevented, and the bottom of the grid oxide layer is protected by combining a source groove, so that the electric field peak below the grid oxide layer is reduced, and the grid oxide layer is prevented from being broken down by a strong electric field.
Preferably, the bottom of the source trench is spaced from the body by a distance of 0.4um to 0.6um.
The contact area of the schottky metal is determined by the distance between the bottom of the source trench and the body region, and the larger the distance between the bottom of the source trench and the body region is, the larger the contact area of the schottky metal is, and the contact area of the schottky diode determines the maximum bearing current and power level. The schottky diode with large contact area has higher capacity and can bear larger current and power. The invention can adapt to high-frequency circuits and high-power circuits, the larger the distance between the bottom of the source electrode groove and the body region is, the stronger the reverse freewheeling capacity of the Schottky diode is, if the distance between the bottom of the source electrode groove and the body region is too large, the electric leakage of the Schottky metal part can be easily caused, and the electric performance of the planar SiC MOS is influenced.
Preferably, the method further comprises: the device comprises a source electrode, a drain electrode, a grid electrode, a substrate, an N-drift layer, a P-well layer, a P+ region and an N+ region;
the drain electrode is positioned below the substrate;
the drain is the charge sink in the MOSFET, which is connected to the channel and is the charge sink. When the MOSFET is in a conducting state, a conducting path is formed between the drain electrode and the source electrode, electrons flow into the drain electrode from the source electrode, and current transmission is completed. The voltage change of the drain electrode has little influence on the working state of the MOSFET, and mainly plays a role in current inflow.
The substrate is positioned below the N-drift layer;
the electric field distribution of the N-drift layer plays a key role in the conduction characteristics and current control of the MOSFET. When a gate voltage is applied to the MOSFET, the electric field distribution in the drift region is modulated by the gate voltage, thereby controlling the flow of current between the source and drain. During MOSFET operation, current between source and drain is transferred primarily through the N-drift layer. The doping type and concentration of the N-drift layer determine the conduction type (N-type or P-type) and magnitude of the current. The structure and characteristics of the N-drift layer directly influence the current control capability of the MOS transistor. By adjusting the shape, the size and the doping concentration of the N-drift layer, accurate control of current can be realized, so that the requirements of different applications are met.
The N-drift layer is positioned below the P-well layer;
the P-well layer is positioned below the N+ region;
the N+ region is positioned below the source electrode;
the P+ region is positioned below the source electrode and is adjacent to the N+ region, the P-well layer and the N-drift layer;
the source electrode is positioned above the grid electrode, the N+ region and the P+ region;
the source is the source of charge in the MOSFET and is the exit of the charge. When the MOSFET is in a conducting state, a conducting path is formed between the source electrode and the drain electrode, electrons flow into the drain electrode from the source electrode, and current transmission is completed. Meanwhile, the source electrode also plays a role of modulating the grid voltage, and the control of the MOSFET is realized by controlling the change of the source electrode voltage.
The gate is located over the n+ region, the N-drift layer, and the P-well layer.
The gate is the control electrode in the MOSFET, and is separated from the channel by an insulating layer, which is a critical part of the MOSFET. The voltage variation of the gate can change the charge density in the channel, thereby controlling the magnitude of the current between the drain and the source.
Example 2
A method for preparing a SiC planar MOS of a source trench integrated SBD, referring to fig. 2 and 3, includes:
s100, epitaxially forming an N-drift layer above a substrate;
the epitaxial process refers to a process of growing a single crystal layer in complete alignment on a substrate, and the epitaxial process is a process of growing a crystal layer in the same lattice orientation as the original substrate on a single crystal substrate. Epitaxial processes are widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. The epitaxial growth modes are classified into solid phase epitaxy, liquid phase epitaxy and gas phase epitaxy according to the different phase states of the growth source. In integrated circuit fabrication, common epitaxy methods are solid phase epitaxy and vapor phase epitaxy.
Solid phase epitaxy refers to the process of growing a single crystal layer on a substrate by a solid source, such as thermal annealing after ion implantation, which is essentially a solid phase epitaxy process. During ion implantation processing, silicon atoms of the silicon wafer are bombarded by high-energy implantation ions and are separated from the original lattice positions, amorphization occurs, and a surface amorphous silicon layer is formed; and then, after high-temperature thermal annealing, the amorphous atoms return to the lattice positions again and keep consistent with the crystal orientation of the atoms in the substrate.
The growth method of vapor phase epitaxy includes chemical vapor phase epitaxy (CVE), molecular beam epitaxy (MBD), atomic Layer Epitaxy (ALE), and the like. In an embodiment of the present invention, chemical Vapor Epitaxy (CVE) is used to form the N-drift layer. The principle of chemical vapor epitaxy is basically the same as that of Chemical Vapor Deposition (CVD), and the process of depositing a film is carried out by mixing gases and then carrying out chemical reaction on the surface of a wafer; in contrast, since the single crystal layer is grown by chemical vapor epitaxy, the impurity content in the apparatus and the cleanliness of the silicon wafer surface are both higher. CVE can also be used in epitaxial silicon wafer processes and MOS transistor embedded source drain epitaxial processes in integrated circuit fabrication. The epitaxial silicon wafer process is to epitaxial a layer of monocrystalline silicon on the surface of the silicon wafer, and compared with the original silicon substrate, the epitaxial silicon layer has higher purity and fewer lattice defects, so that the yield of semiconductor manufacture is improved. In addition, the growth thickness and doping concentration of the epitaxial silicon layer grown on the silicon wafer can be flexibly designed, which brings flexibility to the design of the device, such as being used for reducing the substrate resistance, enhancing the substrate isolation and the like. The embedded source-drain epitaxy process refers to a process of growing doped silicon germanium or silicon outside the source-drain region of the transistor. The main advantages of introducing the embedded source drain epitaxy process include: a pseudomorphic layer containing stress due to lattice adaptation can be grown, and channel carrier mobility is improved; the source and drain can be doped in situ, the parasitic resistance of the source and drain junction is reduced, and the defect of high-energy ion implantation is reduced.
S200, forming a P-well layer, an N+ region and a P+ region by ion implantation above the N-drift layer;
the invention adopts an ion implantation mode to implant ions above the N-drift layer to form a P-well layer, an N+ region and a P+ region. Ion implantation is the emission of an ion beam in vacuum towards a solid material, which, after being directed towards the solid material, is slowly slowed down by the resistance of the solid material and finally stays in the solid material. Ions of one element are accelerated into a solid target, thereby altering the physical, chemical or electrical properties of the target. Ion implantation is commonly used in the fabrication of semiconductor devices, metal surface treatment, and materials science research. If the ions stop and remain in the target, the ions change the elemental composition of the target (if the ions differ from the composition of the target). The ion implantation beam line design includes a common set of functional elements. The main part of the ion beam line comprises an apparatus called ion source for generating ion species. The source is tightly coupled to a bias electrode to extract ions into the beam line and most commonly to some way of selecting a particular ion species for transmission into the main accelerator section. The mass selection is accompanied by the extracted ion beam passing through a region of the magnetic field whose exit path is limited by a blocking aperture or slit which only allows ions to have mass and velocity/charge to continue along the beam line. If the target surface is larger than the ion beam diameter and the implant dose is uniformly distributed over the target surface, some combination of beam scanning and wafer motion may be used. Finally, the implanted surface is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implantation process stopped at the desired dose level.
Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When implanted into a semiconductor, each doping atom may generate charge carriers in the semiconductor after annealing. A hole may be created for the P-type dopant and an electron may be created for the N-type dopant. The conductivity of the semiconductor near the doped region is changed.
S300, depositing a grid electrode and an ILD layer above the N-drift layer, the N+ region, the P+ region and the P-well layer;
the material of the ILD layer is typically SiO 2 Or SiN, the ILD layer is deposited to perform insulation function and simultaneously block moisture and protect the internal structure of the chip, wherein the ILD layer comprises a plurality of layers of films, and the thickness of each layer is different.
The polysilicon deposition is performed by Low Pressure Chemical Vapor Deposition (LPCVD) at a low pressure of 0.2-1.0Torr and a deposition temperature of between 600 and 650deg.C using pure silane or silane diluted with nitrogen to a purity of 20% to 30%. The deposition rate of both deposition processes is between 100-200 a/min, which is determined primarily by the temperature at which the deposition is performed. The resistivity of polysilicon depends on the temperature at which it is deposited, the dopant concentration, and the annealing temperature, which in turn affects the grain size. Increasing the deposition temperature will cause a decrease in resistivity, increasing the dopant concentration will decrease the resistivity, and higher annealing temperatures will form larger sized grains and a consequent decrease in resistivity. The larger the grain size of the polysilicon, the more difficult the etching process is, since large grain sizes will result in rough polysilicon sidewalls, so polysilicon deposition must be performed at low temperatures to achieve smaller grain sizes, polysilicon etching and photoresist stripping, followed by high temperature annealing to form larger grain sizes and lower resistivity.
S400, etching a through hole on the P+ region, etching a groove on the N-drift layer, and connecting the through hole with the groove;
etching is a process of selectively removing unwanted material from the surface of a silicon wafer by chemical or physical means, and is a generic term for stripping and removing material by solution, reactive ions or other mechanical means. The etching technology is mainly divided into dry etching and wet etching. The dry etching mainly uses the reaction gas and the plasma for etching; the wet etching mainly uses chemical reagents to chemically react with the etched material for etching.
Ion beam etching is a physical dry etching process. Thereby, argon ions are irradiated onto the surface with an ion beam of about 1 to 3 keV. Due to the energy of the ions, they strike the material of the surface. The wafer is vertically or obliquely directed into the ion beam and the etching process is absolutely anisotropic. The selectivity is low because it is not different for each layer. The gas and abraded material are evacuated by the vacuum pump, but since the reaction products are not gaseous, particles can deposit on the wafer or chamber walls. All materials can be etched in this way and the wear on the vertical walls is low due to the vertical radiation.
Plasma etching is a chemical etching process and has the advantage that the wafer surface is not damaged by accelerated ions. The method is used to remove the entire film (e.g., backside cleaning after thermal oxidation) because the etch profile is isotropic due to the movable particles of the etch gas. One type of reactor used for plasma etching is a downstream reactor whereby the plasma is ignited at a high frequency of 2.45GHz by impact ionization, the location of which is separated from the wafer.
The etch rate depends on the pressure, the power of the high frequency generator, the process gas, the actual gas flow and the wafer temperature. Anisotropy increases with an increase in high-frequency power, a decrease in pressure, and a decrease in temperature. The uniformity of the etching process depends on the gas, the distance between the two electrodes and the material of the electrodes. If the distance is too small, the plasma cannot be unevenly dispersed, resulting in non-uniformity. If the distance of the electrodes is increased, the etch rate is reduced because the plasma is distributed in the enlarged volume. Carbon has proven to be the material of choice for electrodes. Since fluorine and chlorine also attack carbon, the electrodes produce a uniformly strained plasma and the wafer edge is affected by the same effect as the wafer center. The selectivity and etch rate are largely dependent on the process gas. For silicon and silicon compounds, fluorine gas and chlorine gas are mainly used.
S500, depositing schottky metal at the bottom of the groove;
the schottky metal is deposited by chemical vapor deposition.
S600, depositing a source electrode and a drain electrode.
Metal electrode deposition processes are classified into Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD). CVD refers to a process of chemically depositing a coating on the surface of a wafer, typically by applying energy to a gas mixture. Assuming that the substance (a) is deposited on the wafer surface, two gases (B and C) that can generate the substance (a) are first input to the deposition apparatus, and then energy is applied to the gases to cause the gases B and C to chemically react.
PVD (physical vapor deposition) coating techniques are mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of physical vapor deposition are: vacuum evaporation, sputter coating, arc plasma coating, ion coating, molecular beam epitaxy, and the like. The corresponding vacuum coating equipment comprises a vacuum evaporation coating machine, a vacuum sputtering coating machine and a vacuum ion coating machine.
Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD) can be used as a means of depositing metal electrodes. In the embodiment of the invention, a chemical vapor deposition method is adopted to deposit the metal electrode, and the chemical vapor deposition process is divided into three stages: the reaction gas diffuses toward the surface of the substrate, the reaction gas is adsorbed on the surface of the substrate, and chemical reaction occurs on the surface of the substrate to form solid deposits, and the generated gas phase byproducts are separated from the surface of the substrate.
Preferably, the method is characterized in that the through hole is etched on the P+ region, and after the trench is etched on the N-drift layer, the method further comprises:
and forming a P+ shielding layer by ion implantation on the upper layer of the N-drift layer.
After forming the trench, ion implantation is performed at the bottom of the trench to form a p+ shielding layer.
According to the invention, the source electrode groove is formed in the P+ region towards the N-drift layer, the source electrode groove replaces part of the P+ region and the N-drift layer, the Schottky metal is deposited on the two side wall surfaces of the bottom of the source electrode groove, compared with the prior art, the Schottky diode in anti-parallel connection on a plane has smaller chip area, the Schottky metal on the two sides of the source electrode is larger than the reverse current of the Schottky metal on the single side of the source electrode, and the P+ shielding layer is arranged below the source electrode groove and is used for shielding a channel between the source electrode and the drain electrode due to the large electric field intensity below the source electrode groove, so that electric leakage is reduced, the electric field distribution in the drift layer can be improved by the P+ shielding layer, electric field peaks below the grid electrode are relieved, the grid electrode oxide layer is protected, and the reliability of the SiC planar MOS is remarkably improved.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A SiC planar MOS of a source trench integrated SBD, comprising: a schottky metal;
the Schottky metal is positioned between the N-drift layer and the source electrode;
the schottky metal is attached to the bottom wall of the source trench and abuts the source and drift layers.
2. The SiC planar MOS of a source trench integrated SBD of claim 1 further comprising: a P+ shielding layer;
the P+ shielding layer is located below the Schottky metal and is adjacent to the Schottky metal and the drift layer.
3. The SiC planar MOS of a source trench integrated SBD of claim 1 wherein the schottky metal has a length of 0.6um.
4. The SiC planar MOS of a source trench integrated SBD of claim 1 wherein the schottky metal has a thickness of 0.2um.
5. The SiC planar MOS of claim 2 wherein the p+ shield layer has a doping concentration of 10 19 cm -3 To 10 20 cm -3 。
6. The SiC planar MOS of a source trench integrated SBD of claim 2 wherein said p+ shield layer has a thickness of 0.5um.
7. The SiC planar MOS of a source trench integrated SBD of claim 1 in which the bottom of the source trench is from 0.4um to 0.6um from the body region.
8. The SiC planar MOS of a source trench integrated SBD of claim 1 further comprising: the device comprises a source electrode, a drain electrode, a grid electrode, a substrate, an N-drift layer, a P-well layer, a P+ region and an N+ region;
the drain electrode is positioned below the substrate;
the substrate is positioned below the N-drift layer;
the N-drift layer is positioned below the P-well layer;
the P-well layer is positioned below the N+ region;
the N+ region is located below the source electrode;
the P+ region is positioned below the source electrode and is adjacent to the N+ region, the P-well layer and the N-drift layer;
the source electrode is positioned above the grid electrode, the N+ region and the P+ region;
the gate is located over the n+ region, the N-drift layer, and the P-well layer.
9. The preparation method of the SiC planar MOS of the source electrode trench integrated SBD is characterized by comprising the following steps of:
epitaxially forming an N-drift layer over the substrate;
forming a P-well layer, an N+ region and a P+ region by ion implantation above the N-drift layer;
depositing a gate and ILD layer over the N-drift layer, the n+ region, the p+ region, and the P-well layer;
etching a through hole on the P+ region, and etching a groove on the N-drift layer, wherein the through hole is connected with the groove;
depositing schottky metal at the bottom of the groove;
and depositing a source electrode and a drain electrode.
10. The method for fabricating a SiC planar MOS of a source trench integrated SBD according to claim 9, wherein said etching a via in said p+ region, after etching a trench in said N-drift layer, further comprises:
and forming a P+ shielding layer by ion implantation on the upper layer of the N-drift layer.
CN202311632899.4A 2023-12-01 2023-12-01 SiC planar MOS of source electrode groove integrated SBD and preparation method Pending CN117334747A (en)

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