CN106876485A - Double trench MOSFET devices of a kind of SiC of integrated schottky diode and preparation method thereof - Google Patents
Double trench MOSFET devices of a kind of SiC of integrated schottky diode and preparation method thereof Download PDFInfo
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 238000002347 injection Methods 0.000 claims description 18
- 239000007924 injection Substances 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 17
- 238000000137 annealing Methods 0.000 claims description 15
- 229910052681 coesite Inorganic materials 0.000 claims description 14
- 229910052906 cristobalite Inorganic materials 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 239000000377 silicon dioxide Substances 0.000 claims description 14
- 229910052682 stishovite Inorganic materials 0.000 claims description 14
- 229910052905 tridymite Inorganic materials 0.000 claims description 14
- 238000007254 oxidation reaction Methods 0.000 claims description 12
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- 238000002161 passivation Methods 0.000 claims description 11
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- 238000001259 photo etching Methods 0.000 claims description 9
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention discloses a kind of double trench MOSFET devices of SiC of integrated schottky diode, two grooves are provided with the primitive cell structure of the double trench MOSFET device active areas of the SiC, the gate groove at primitive cell structure center and the peripheral source groove of gate groove are provided in respectively；The bottom surrounding of gate groove and source groove has carried out the doping with drift region films of opposite conductivity；The central area of channel bottom in source, is provided with Schottky contacts, the Schottky diode that formation is electrically connected with source electrode；In source, channel bottom surrounding forms Ohmic contact with drift region films of opposite conductivity doped region；The depth of two grooves is both greater than the p bases.The application is using the double groove structures of source and grid, and bottom surrounding in gate groove bottom and source groove carries out the doping with drift region films of opposite conductivity, realizes the shielding to mos gate, increases the reliability of grid.The electric field of base can be shielded simultaneously, prevent the break-through of base；And it is integrated with the MPS Schottky diodes with surge capacity high.
Description
Technical field
The invention belongs to semiconductor applications, and in particular to a kind of double trench MOSFETs of SiC of integrated schottky diode
Device and preparation method thereof.
Background technology
The U-shaped groove MOSFETs of SiC (UMOSFET) has many advantages, and such as p bases can be eliminated with being epitaxially-formed
The influence that imperfect tape comes when ion implanting forms p bases, with more preferable mos gate quality and channel mobility, and more holds
Channel length easy to control.In addition, the primitive cell structure (elementary cell of composition device active region) of trench MOSFET can be accomplished
Smaller, current density is higher, especially for the expensive price of SiC material, can significantly reduce chip cost.But UMOSFET
There is channel bottom electric field concentration, so that the problem of gate medium poor reliability.As shown in figure 1, being a kind of conventional n-channel
The schematic diagram of UMOSFET primitive cell structures, in the off case, the high pressure being added in drain electrode will be acted on drift layer, groove
The A points of bottom will be the place that electric field is most concentrated, and the electric-field intensity in medium is 2-3 times in SiC, causes channel bottom
Gate medium is easily breakdown, poor reliability.
On the other hand, under many applicable cases, such as in full-bridge application, transistor needs one afterflow two of inverse parallel
Pole pipe works together, and such as conventional at present silicon IGBT module, all inverse parallel silicon fast recovery diode are used as fly-wheel diode.Such as
Fruit is integrated with fly-wheel diode in a device, then the integrated level and reliability of chip are not only increased, while also effective
Reduce chip cost.
The content of the invention
For problems of the prior art, it is an object of the invention to provide a kind of integrated schottky diode
The double trench MOSFET devices of SiC, it efficiently solves problems of the prior art.Another object of the present invention is to carry
For a kind of method of the double trench MOSFET devices of SiC for making integrated schottky diode.
To achieve the above object, the present invention uses following technical scheme：
A kind of double trench MOSFET devices of SiC of integrated schottky diode, the double trench MOSFET devices of the SiC
The primitive cell structure of active area sequentially consists of drain electrode, n+ substrates, cushion, n- drift layers, p bases and n++ layers；In primitive unit cell
Two grooves are provided with structure, the gate groove at primitive cell structure center and the peripheral source ditch of the gate groove are provided in respectively
Groove；The bottom surrounding of the gate groove and source groove has carried out the doping with drift region films of opposite conductivity；In source trench bottom
The central area in portion, is provided with Schottky contacts, the Schottky diode that formation is electrically connected with source electrode；In source channel bottom surrounding
Ohmic contact is formed with drift region films of opposite conductivity doped region；The depth of two grooves is both greater than the p bases.
Further, the gate groove Xia p+ areas are to suspend, i.e., be not electrically connected with source electrode.
Further, the gate groove Xia p+ areas are electrically connected with source electrode and the p bases.
Further, the doping concentration of the p bases is in 1E15-5E17cm-3Between, the thickness of p bases is 0.2-3 μm.
Further, described n++ layers doping concentration is more than 1E19cm-3, n++ layers of thickness is 0.2-2 μm.
Further, p bases lower section and the region between the gate groove, the channel bottom doping depth of source groove
Doping concentration is than n- drift floor heights.
Further, the wall doping that the p-type doped region of the channel bottom of the source groove passes through source groove with the p bases
It is electrically connected, i.e. source electrode is also electrically connected with p bases.
A kind of method of the double trench MOSFET devices of SiC for preparing integrated schottky diode, methods described is included such as
Lower step：
1) cushion, n- drift layers, p bases and n++ layers are sequentially prepared on substrate；
2) patterned first mask layer on surface of SiC is done, is deposited with CVD method, then again with the side of chemical wet etching
Method forms SiO2Figure；With ICP method etching SiC grooves, source, gate groove are formed；Also knot termination environment and scribe area are entered simultaneously
Row etching；
3) the second mask layer on surface of SiC is done, as the mask being subsequently implanted into, carries out Al ion implantings, in source groove
Side wall and bottom surrounding form doping, the direction of injection is the direction that inclination angle is set perpendicular to wafer direction and band one；Injection
After the completion of remove the second mask layer；
4) the 3rd mask layer on surface of SiC is done, with the method for photoetching after the completion of deposit, in other region glue as the
Four mask layers form covering protection, and in gate groove unglazed photoresist, while also forming the glue of field limiting ring form in knot termination environment
Mask；Use ICP anisotropic etchings, the SiO of removal gate groove bottom2Medium, and continue to retain the SiO of gate trench sidewall2It is situated between
Matter, protection gate groove area；Al ion implantings, p+ doping is formed in gate groove bottom；Photoresist and SiO are removed after the completion of injection2
Medium, and carry out RCA cleanings；In one layer of graphite linings of surface deposition, high temperature activation anneal is carried out；Use O2、N2Plasma etching or
Person removes graphite linings with thermal oxidation process；
5) cleaned with RCA and BOE, carry out sacrifice oxidation；One layer of SiO is grown with the method for thermal oxide2, corroded with BOE and gone
Remove；The method growth gate dielectric layer of reusable heat oxidation, again in NO or N after oxidation2O or POCl3Annealed in atmosphere；Formed sediment with CVD method
Product highly doped polysilicon, or undoped polycrystal is first deposited, then form DOPOS doped polycrystalline silicon with the method for injection and annealing；With
Polysilicon fills gate groove, and surface is planarized；Glue mask is formed with the method for photoetching, the polycrystalline outside gate groove is etched away
Silicon, forms polycrystal grid；
6) deposit isolation passivation layer, the medium of source groove and ohmic contact regions is removed with the method for chemical wet etching, is retained
Medium on gate polysilicon, formation grid are isolated with source.Metal ohmic contact is deposited in source ohmic contact regions, Europe is overleaf deposited
Nurse contacting metal, carries out rapid thermal annealing in a vacuum or inert atmosphere, and source, leakage Ohmic contact are formed respectively；
7) schottky metal is deposited with PVD methods, the method etched again with photoetching is removed outside source groove and ohmic contact regions
The metal in other regions, then thermal annealing is carried out, the Schottky contacts of source channel bottom zone line are formed, it is high simultaneously for periphery
Doping p+ areas can form Ohmic contact；
8) electrode metal of thickness is done, source electrode is electrically connected with schottky metal, and electrode briquetting metal passes through above primitive unit cell
Isolation passivation layer and gate isolation；Do the electrode metal of thickness in the back side；Last layer thickness passivation layer, and windowing are finally done, is exposed
Source, the weld zone of grid voltage block metal.
Further, step 1) in the substrate for highly doped low-resistance n+ layer, concentration is more than 1E18cm-3, it is described slow
The thickness for rushing layer is 1-2 μm；The concentration of the drift layer is in 1E14-1E17cm-3Between, thickness is more than 5 μm；The p bases
Doping concentration is in 1E15-5E17cm-3Between, thickness is 0.2-3 μm；Described n++ layers concentration is more than 1E19cm-3, thickness is more than
0.2μm。
First mask layer described in further, it is characterised in that step 2) is SiO2, thickness is 2-4 μm, the source, grid
The depth of groove is more than the thickness sum of n++ layers and p bases, is 1-4 μm；The width of gate groove is 0.5-2 μm, the width of source groove
It is 2.5-10 μm to spend, and uses SiO2The selection of mask etching SiC is compared more than 3.
Further, step 3) described in doped region concentration be more than 1E18cm-3, surface concentration is more than 1E19cm-3, depth is
More than 0.35 μm.
Further, step 4) in gate groove bottom formed p+ doping concentrations be more than 1E18cm-3, depth is more than 0.35 μ
m；The thickness of the graphite linings is 10-100nm；The annealing temperature of high temperature activation anneal is more than 1600 DEG C, and the time is more than 3 minutes.
Further, step 5) in thermal oxide method growth SiO2Thickness is 10-100nm；The temperature of thermal oxide is
Between 1200 DEG C -1500 DEG C, thermal oxide is in O2Carried out in atmosphere.
Further, step 6) described in isolation passivation layer be using CVD method deposit SiO2Or SiOxNy layers, thickness
More than 0.5 μm；The annealing temperature of rapid thermal annealing is between 900-1100 DEG C, the time is between 1 minute to 15 minutes；Source, leakage
Metal ohmic contact be Ni or Ti/Ni.
Further, step 7) described in schottky metal be Ti, Mo, Ni or Pt；The annealing temperature of thermal annealing is 400-600
DEG C, the time is 5-30 minutes.
Further, step 8) described in thick passivation layer be SiO2、Si3N4Or polyimides.
Further, step 1) described in also have one layer JFET layers between n- drift regions and the p bases, it is described JFET layers
Concentration is less than 1E18cm-3, higher than n- drift region, thickness is equal to p bases to the distance of p+ areas junction depth under gate groove.
The present invention has following Advantageous Effects：
The application is using the double groove structures of source and grid, and bottom surrounding in gate groove bottom and source groove is carried out and drift
The doping of area's films of opposite conductivity is moved, the shielding to mos gate is realized, increases the reliability of grid.The electricity of base can be shielded simultaneously
, prevent the break-through of base.Schottky contacts are done in the central area of source channel bottom, is adulterated with periphery films of opposite conductivity
Region forms Ohmic contact, the integrated MPS Schottky diodes with surge capacity high.
Brief description of the drawings
Fig. 1 is the primitive unit cell planar structure schematic diagram of UMOSFET in the prior art；
Fig. 2 is the primitive unit cell planar structure schematic diagram of MOSFET element of the invention；
Fig. 3 is the device plane schematic diagram of hexagonal primitive unit cell close-packed configuration for the active area of the embodiment of the present invention；
Fig. 4 is the circuit diagram of MOSFET element of the present invention；
Fig. 5 is extension material structure schematic diagram in MOSFET element preparation process of the present invention；
Fig. 6 is the primitive unit cell planar structure schematic diagram after SiC etching grooves in MOSFET element preparation process of the present invention；
Fig. 7 is the primitive unit cell planar structure schematic diagram after the groove ion implanting of source in MOSFET element preparation process of the present invention；
Fig. 8 is the primitive unit cell planar structure schematic diagram after gate groove ion implanting in MOSFET element preparation process of the present invention；
Fig. 9 is that the primitive unit cell planar structure schematic diagram after polysilicon gate is formed in MOSFET element preparation process of the present invention；
Figure 10 is that the primitive unit cell planar structure formed in MOSFET element preparation process of the present invention after source, leakage Ohmic contact is illustrated
Figure；
Figure 11 is formation schottky junctions primitive unit cell planar structure schematic diagram after touch in MOSFET element preparation process of the present invention；
Figure 12 is the primitive unit cell planar structure schematic diagram after the completion of prepared by MOSFET element of the present invention.
Specific embodiment
Below, refer to the attached drawing, is more fully illustrated to the present invention, shown in the drawings of exemplary implementation of the invention
Example.However, the present invention can be presented as various multi-forms, the exemplary implementation for being confined to describe here is not construed as
Example.And these embodiments are to provide, so that the present invention is fully and completely, and will fully convey the scope of the invention to this
The those of ordinary skill in field.
As shown in Fig. 2 invention provides a kind of double trench MOSFET devices of SiC of integrated schottky diode,
The primitive cell structure of the double trench MOSFET device active areas of the SiC sequentially consists of drain electrode, n+ substrates, cushion, n- drifts
Shifting layer, p bases and n++ layers；Two grooves are provided with primitive cell structure, the gate groove at primitive cell structure center is provided in respectively
With the peripheral source groove of gate groove；The bottom surrounding of gate groove and source groove has been carried out and drift region films of opposite conductivity
Doping, on the one hand can with gate groove bottom doping together with shield grid, source channel bottom electric field, reduce electric field concentrate, carry
For reliability；On the other hand the embedded pn diode sections of integrated Schottky diode are also served as, possesses Surge handling capability high；
The central area of channel bottom in source, is provided with Schottky contacts, the Schottky diode that formation is electrically connected with source electrode；In Yuan Gou
Trench bottom surrounding forms Ohmic contact with drift region films of opposite conductivity doped region；The depth of two grooves is both greater than the p
Base；The depth of gate groove and source groove can it is consistent can also be inconsistent, preferably both depth are consistent, are easy in device system
Step etching is formed simultaneously during work.
Grid groove Xia p+ areas are to suspend in one embodiment of the present of invention, i.e., be not electrically connected with source electrode.It is of the invention another
Grid groove Xia p+ areas are electrically connected with source electrode and p bases in one embodiment, are all connections because of grid groove, by subregion
Grid groove is also carried out the injection of side wall, completes p+ with p bases so as to be electrically connected with source electrode, and the grid of this subregion are no longer acted as
With.
The base layer (being p base layers for N-shaped MOSFET, be identical reason to p-type MOSFET) of device is used
It is epitaxially-formed, therefore with extraordinary quality of materials and point-device thickness and doping concentration, it is high-quality beneficial to making
The mos gate structure of amount.Doping concentration is in 1E15-5E17cm-3Between, according to threshold voltage designs.Base layer thickness is more than 0.2 μ
M, preferably between 0.2-3 μm, too thin easy break-through is too thick to increase channel length and resistance.
N++ layers above p bases is more than 1E19cm as source conductive layer, doping concentration-3Between, thickness is more than 0.2 μm,
Preferably between 0.2-2 μm.The too thin easy break-through of Ohmic contact of thickness, the too thick depth that can increase conducting resistance and etching groove
And difficulty.
The n- layers of pressure-resistant drift layer as device below p bases, its doping concentration, thickness according to device design it is pressure-resistant
Ability determination, design is optimized by being minimized in certain resistance to pressure conducting resistance.Such as 1200V devices, concentration can be with
It is 5-8E15cm-3, thickness can be 10-15 μm.Region below p bases and between channel bottom doping depth, adulterates dense
Spend the drift layer that can also compare slightly higher, such as can be 1E16-1E17cm-3Between, main purpose can be to reduce electronics warp
Can preferably be spread to drift layer all directions after crossing raceway groove, reduce conducting resistance.The doping concentration of n+ substrates is more than 1E18cm-3。
The p-type doped region of channel bottom is electrically connected with p base layers by the wall doping of source groove, therefore, source electrode
Also it is electrically connected with p bases simultaneously, it is to avoid parasitic npn-structure.The p of source channel bottom surrounding is doped to high concentration of p-type area, is beneficial to
Ohmic contact is formed with metal, is connected with the Schottky contacts at center, together form the pole of Schottky two of embedded pn diodes
Pipe.
As shown in figure 3, wherein AA ' cross section structures schematic diagram is Fig. 1.The planar structure of primitive unit cell can for rectangle, bar shaped,
The various forms such as hexagon.Simple being arranged in parallel of primitive unit cell forms an active area for device, and arrangement mode can be simple
Arrangement, or the form such as solid matter, atomic structural arrangement.Meanwhile, whole device is by active area, knot termination environment and scribe line area
Composition, and grid, source electrode on the active area to each primitive unit cell enters row metal extraction respectively, does corresponding briquetting metal, is beneficial to
The follow-up package application of device.This is known to industry engineer, not indicate that on schematic diagram.
As shown in figure 4, MOSFET constitutes antiparallel circuit structure with Schottky diode, realize in a chip
It is integrated.The power density and reliability of device can be effectively increased, the module of encapsulation or the volume and expense of system is reduced.
The N-shaped doping mentioned in the present invention is that comparatively, the also referred to as first doping is mixed with second with p-type doping
It is miscellaneous, that is, N-shaped exchanges equally applicable to device with p-type.
Device architecture is applicable not only to SiC in the present invention, is also equally applicable to Si, GaN, Ga2O3Deng semi-conducting material,
But preparation method is different.
SiC MOSFET structures of the invention, can be used for the transistor arrangement of other MOS controls, such as IGBT.In MOS controls
Structure division there is related structure and principle.
Present invention also offers a kind of double trench MOSFET devices of SiC for preparing integrated schottky diode of the invention
Method, the method is described in detail by taking N-shaped (n-channel) SiC MOSFET as an example below.
As shown in figure 5, substrate (or referred to as substrate) is highly doped low-resistance n+ layers, concentration is more than 1E18cm-3.Buffering
The concentration of layer is about 1E18cm-3, about 1-2 μm of thickness, the purpose of cushion is to reduce lattice between substrate and epitaxial layer not
Matching, while the defect of teste substrate is in cushion, it is to avoid defect extends to drift layer.The concentration of drift layer exists
1E14-1E17cm-3Between, thickness is more than 5 μm, undertakes the pressure-resistant function of device, and concentration, thickness optimize according to the rated insulation voltage of device
Depending on design.It is p base layers above drift region, concentration is 1E15-5E17cm-3Between, thickness is more than 0.2 μm, than being preferably
0.2-2μm.There is one layer JFET layers between n- drift regions and p bases in another embodiment, concentration is less than 1E18cm-3, than drift
Qu Genggao is moved, thickness is approximately equal to p bases to the distance of Shan Xia p+ areas junction depth, it is therefore an objective to reduce the interregional electric conductions of this JFET
Resistance.It is n+ areas above p bases, doping concentration is more than 1E19cm-3, thickness is more than 0.2 μm.
As shown in fig. 6, on surface of SiC is done patterned first mask.First mask can be usually SiO2, thickness
The SiO that thickness according to mask demand is subsequently implanted into is consumed when adding etching groove2The sum of thickness, is typically 2-4 μm.With
CVD method is deposited, and then forms SiO with methods such as chemical wet etchings again2Figure.With ICP method etching SiC grooves, source, grid are formed
Groove.Also knot termination environment and scribe area are etched simultaneously.Pressure-resistant and electric conduction of the depth of groove according to design device
Depending on resistance, it is added with the thickness of p bases slightly deeply, usually between 1-4 μm than n++ area.The width of gate groove preferably exists
Between 0.5-2 μm, the width of source groove is preferably between 2.5-10 μm.Use SiO2Mask etching SiC selection ratios can accomplish 3
More than, therefore will remaining major part SiO after the completion of etching2, as the block mask of next step ion implanting.In addition, using SiO2
Mask etching SiC can obtain low defect, the groove effect of U-shaped bottom, beneficial to the reliability of device.
As shown in fig. 7, the second mask is done, as the mask being subsequently implanted into.Xiao Te in the middle of in the groove of mask protection source
Base region and gate groove.Middle schottky area width is typically 1.5-8 μm.Mask can be photoresist, medium etc., excellent
Selection of land can be with photoresist.It is general for photoresist depending on mask thicknesses are according to mask material and the energy of subsequent ion injection
More than 2.5 μm.Al ion implantings are carried out, the doped region concentration for being formed is injected and is more than 1E18cm-3, surface concentration is more than
1E19cm-3, depth is more than 0.35 μm.The direction of injection is the direction perpendicular to wafer direction and with certain inclination angle.One constant inclination
The direction injection at angle to the side wall of source groove primarily to can carry out effective injection, the highly doped p+ of formation completes source
Pole is electrically connected with p bases.The purpose that the implantation concentration on surface is higher is to form the surface of more high-dopant concentration, being beneficial to
It is subsequently formed the Ohmic contact in source channel bottom p+ areas.The second mask is removed after the completion of injection.
As shown in figure 8, in the mask layer of surface deposition the 3rd, it is therefore preferable to medium, such as SiO2.3rd mask is mainly rear
The side wall of protection gate groove during continuous injection.With the method for photoetching after the completion of deposit, in other region glue as the 4th mask layer
Form covering protection, and in gate groove unglazed photoresist, while also forming the glue mask of field limiting ring form in knot termination environment.With
ICP anisotropic etchings, the SiO of removal gate groove bottom2Medium, and continue to retain the SiO of gate trench sidewall2Medium, protects grid
Channel region.Al ion implantings, p+ doping is formed in gate groove bottom, and concentration is more than 1E18cm-3, depth be more than 0.35 μm, preferably
Ground depth is consistent with source channel bottom p+ areas.Also form the junction termination structures of field limiting ring form simultaneously, it is of the invention other
Can also be using the junction termination structures of other forms, such as JTE (knot termination extension) of injection, JTE, JTE of etching in embodiment
With field limiting ring combining form etc..Photoresist and SiO are removed after the completion of injection2Medium, and carry out RCA cleanings.In surface deposition one
Layer graphite linings, thickness is about 10-100nm, carries out high temperature activation anneal, and annealing temperature is more than 1600 DEG C, and the time is more than 3 minutes.
Use O2、N2Plasma etching removes graphite linings with thermal oxidation process.
As shown in figure 9, being cleaned with RCA and BOE, sacrificial oxidation process is carried out.One layer of SiO is grown with the method for thermal oxide2,
Thickness is about 10-100nm, uses BOE erosion removals.Sacrificial oxidation process can remove defect and the damage that surface etch is brought
Layer.The method growth gate dielectric layer of reusable heat oxidation, depending on thickness is according to the threshold voltage of device, preferably thickness is 40-
80nm.The temperature of thermal oxide is between 1200 DEG C -1500 DEG C, thermal oxide is in O2Carried out in atmosphere, again in NO or N after oxidation2O or
POCl3Etc. annealing in atmosphere, improve the interfacial state of MOS.Highly doped polysilicon is deposited with CVD method, it is also possible to which first deposit nothing is mixed
Miscellaneous polycrystal, then form doping with the method for injection and annealing.Gate groove is filled with polysilicon, surface is planarized.
Glue mask is formed with the method for photoetching, the polysilicon outside gate groove is etched away, polysilicon gate is formed.
As shown in Figure 10, deposit isolation passivation layer, the general method with CVD deposits SiO2Or SiOxNy layers, thickness is preferred
Ground is more than 0.5 μm, and the medium of source groove and ohmic contact regions is removed with the method for chemical wet etching, retains Jie on gate polysilicon
Matter, formation grid are isolated with source.Metal ohmic contact is deposited in source ohmic contact regions, metal ohmic contact is overleaf deposited,
Carry out rapid thermal annealing under vacuum or inert atmosphere, annealing temperature is between 900-1100 DEG C, the time be 1 minute to 15 minutes it
Between, source, leakage Ohmic contact are formed respectively.Source, leakage metal ohmic contact it is general be Ni, Ti/Ni etc..
As shown in figure 11, schottky metal is deposited with PVD methods.PVD methods can produce the Metal deposition of isotropic,
Beneficial to the Metal deposition of source trenched side-wall.The method etched again with photoetching removes other regions outside source groove and ohmic contact regions
Metal.Schottky metal can be Ti, Mo, Ni, Pt etc..Thermal annealing is carried out again, and such as to Ti schottky metals, annealing temperature is
400-600 DEG C, the time is 5-30 minutes, forms the Schottky contacts of source channel bottom zone line, highly doped simultaneously for periphery
Miscellaneous p+ areas can form Ohmic contact.Annealing can improve the performance and uniformity of Schottky contacts.
As shown in figure 12, the electrode metal of thickness is done, is easy to encapsulation during device application.Source is electrically connected with schottky metal
It is logical, electrode briquetting metal above primitive unit cell, by isolating passivation layer and gate isolation.Gate electrode briquetting metal draws in the other end
Go out, as shown in Fig. 3 floor map.Do the electrode metal of thickness in the back side.Finally do last layer thickness passivation layer, such as SiO2、Si3N4、
Polyimides etc., and windowing, expose source, the weld zone of grid voltage block metal.
It is described above simply to illustrate that of the invention, it is understood that the invention is not limited in above example, meet
The various variants of inventive concept are within protection scope of the present invention.
Claims (10)
1. a kind of double trench MOSFET devices of SiC of integrated schottky diode, the double trench MOSFET devices of the SiC have
The primitive cell structure of source region sequentially consists of drain electrode, n+ substrates, cushion, n- drift layers, p bases and n++ layers；Its feature exists
In, it is provided with two grooves in primitive cell structure, the gate groove and the gate groove at primitive cell structure center are provided in respectively
The source groove of periphery；The bottom surrounding of the gate groove and source groove has carried out the doping with drift region films of opposite conductivity；
The central area of channel bottom in source, is provided with Schottky contacts, the Schottky diode that formation is electrically connected with source electrode；In Yuan Gou
Trench bottom surrounding forms Ohmic contact with drift region films of opposite conductivity doped region；The depth of two grooves is both greater than the p
Base.
2. double trench MOSFET devices of the SiC of integrated schottky diode according to claim 1, it is characterised in that
The gate groove Xia p+ areas are to suspend, i.e., be not electrically connected with source electrode.
3. double trench MOSFET devices of the SiC of integrated schottky diode according to claim 1, it is characterised in that
The gate groove Xia p+ areas are electrically connected with source electrode and the p bases.
4. double trench MOSFET devices of the SiC of integrated schottky diode according to claim 1, it is characterised in that
The doping concentration of the p bases is in 1E15-5E17cm-3Between, the thickness of p bases is 0.2-3 μm.
5. double trench MOSFET devices of the SiC of integrated schottky diode according to claim 1, it is characterised in that
Described n++ layers doping concentration is more than 1E19cm-3, n++ layers of thickness is 0.2-2 μm.
6. double trench MOSFET devices of the SiC of integrated schottky diode according to claim 1, it is characterised in that
The doping concentration in the p bases lower section and the region between the gate groove, the channel bottom doping depth of source groove is than described
N- drift floor heights.
7. double trench MOSFET devices of the SiC of integrated schottky diode according to claim 1, it is characterised in that
The p-type doped region of the channel bottom of the source groove is electrically connected with the p bases by the wall doping of source groove, i.e.
Source electrode is also electrically connected with p bases.
8. a kind of double trench MOSFET devices of SiC for preparing any described integrated schottky diodes of claim 1-7
Method, it is characterised in that methods described comprises the following steps：
1) cushion, n- drift layers, p bases and n++ layers are sequentially prepared on substrate；
2) patterned first mask layer on surface of SiC is done, is deposited with CVD method, then again with the method shape of chemical wet etching
Into SiO2Figure；With ICP method etching SiC grooves, source, gate groove are formed；Also knot termination environment and scribe area are carved simultaneously
Erosion；
3) the second mask layer on surface of SiC is done, as the mask being subsequently implanted into, carries out Al ion implantings, the side of groove in source
Wall and bottom surrounding form doping, and the direction of injection is the direction perpendicular to wafer direction and with a setting inclination angle；Injection is completed
After remove the second mask layer；
4) the 3rd mask layer on surface of SiC is done, with the method for photoetching after the completion of deposit, covers in other region glue as the 4th
Film layer forms covering protection, and in gate groove unglazed photoresist, while also forming the glue mask of field limiting ring form in knot termination environment；
Use ICP anisotropic etchings, the SiO of removal gate groove bottom2Medium, and continue to retain the SiO of gate trench sidewall2Medium, protection
Gate groove area；Al ion implantings, p+ doping is formed in gate groove bottom；Photoresist and SiO are removed after the completion of injection2Medium, and
Carry out RCA cleanings；In one layer of graphite linings of surface deposition, high temperature activation anneal is carried out；Use O2、N2Plasma etching or with heat
Method for oxidation removes graphite linings；
5) cleaned with RCA and BOE, carry out sacrifice oxidation；One layer of SiO is grown with the method for thermal oxide2, use BOE erosion removals；Again
Gate dielectric layer is grown with the method for thermal oxide, again in NO or N after oxidation2O or POCl3Annealed in atmosphere；Deposited with CVD method high
DOPOS doped polycrystalline silicon, or undoped polycrystal is first deposited, then form DOPOS doped polycrystalline silicon with the method for injection and annealing；Use polycrystalline
Silicon fills gate groove, and surface is planarized；Glue mask is formed with the method for photoetching, the polysilicon outside gate groove is etched away,
Form polycrystal grid；
6) deposit isolation passivation layer, the medium of source groove and ohmic contact regions is removed with the method for chemical wet etching, retains grid many
Medium on crystal silicon, formation grid are isolated with source.Metal ohmic contact is deposited in source ohmic contact regions, ohm is overleaf deposited and is connect
Metal is touched, rapid thermal annealing is carried out in a vacuum or inert atmosphere, source, leakage Ohmic contact are formed respectively；
7) schottky metal is deposited with PVD methods, the method etched again with photoetching removes outside source groove and ohmic contact regions other
The metal in region, then thermal annealing is carried out, the Schottky contacts of source channel bottom zone line are formed, it is highly doped simultaneously for periphery
P+ areas can form Ohmic contact；
8) do the electrode metal of thickness, source electrode is electrically connected with schottky metal, electrode briquetting metal above primitive unit cell, by isolating
Passivation layer and gate isolation；Do the electrode metal of thickness in the back side；Last layer thickness passivation layer, and windowing are finally done, exposes source, grid
The weld zone of briquetting metal.
9. the preparation method of the double trench MOSFET devices of the SiC of integrated schottky diode according to claim 8, its
Be characterised by, step 1) in the substrate for highly doped low-resistance n+ layer, concentration is more than 1E18cm-3, the cushion
Thickness is 1-2 μm；The concentration of the drift layer is in 1E14-1E17cm-3Between, thickness is more than 5 μm；The doping of the p bases is dense
Degree is in 1E15-5E17cm-3Between, thickness is 0.2-3 μm；Described n++ layers concentration is more than 1E19cm-3, thickness is more than 0.2 μm.
10. the preparation method of the double trench MOSFET devices of the SiC of integrated schottky diode according to claim 8,
Characterized in that, step 2) described in the first mask layer be SiO2, thickness is 2-4 μm, and the source, the depth of gate groove are more than n+
The thickness sum of+layer and p bases, is 1-4 μm；The width of gate groove is 0.5-2 μm, and the width of source groove is 2.5-10 μm, is used
SiO2The selection of mask etching SiC is compared more than 3.
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| PCT/CN2017/081004 WO2018161412A1 (en) | 2017-03-06 | 2017-04-19 | Sic dual-trench mosfet device having integrated schottky diode and preparation method therefor |
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| WO2018161412A1 (en) | 2018-09-13 |
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