CN108807504A - Silicon carbide MOSFET device and its manufacturing method - Google Patents
Silicon carbide MOSFET device and its manufacturing method Download PDFInfo
- Publication number
- CN108807504A CN108807504A CN201810990494.0A CN201810990494A CN108807504A CN 108807504 A CN108807504 A CN 108807504A CN 201810990494 A CN201810990494 A CN 201810990494A CN 108807504 A CN108807504 A CN 108807504A
- Authority
- CN
- China
- Prior art keywords
- silicon carbide
- source
- gate
- groove
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 389
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 388
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 113
- 239000002184 metal Substances 0.000 claims abstract description 113
- 229920005591 polysilicon Polymers 0.000 claims abstract description 103
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 94
- 238000005530 etching Methods 0.000 claims abstract description 93
- 238000002347 injection Methods 0.000 claims abstract description 16
- 239000007924 injection Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 76
- 238000001259 photo etching Methods 0.000 claims description 58
- 230000008569 process Effects 0.000 claims description 57
- 150000002500 ions Chemical class 0.000 claims description 38
- 238000005468 ion implantation Methods 0.000 claims description 32
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 23
- 239000010703 silicon Substances 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 20
- 238000005516 engineering process Methods 0.000 claims description 15
- 239000011521 glass Substances 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 13
- 238000003763 carbonization Methods 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 9
- 229910003978 SiClx Inorganic materials 0.000 claims description 9
- 229910052799 carbon Inorganic materials 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- -1 phosphonium ion Chemical class 0.000 claims description 8
- 229910002601 GaN Inorganic materials 0.000 claims description 5
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 5
- 229910003460 diamond Inorganic materials 0.000 claims description 4
- 239000010432 diamond Substances 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims description 3
- 229910001195 gallium oxide Inorganic materials 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- 241001080929 Zeugopterus punctatus Species 0.000 claims 1
- 238000005457 optimization Methods 0.000 abstract description 8
- 230000006872 improvement Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 43
- 230000015572 biosynthetic process Effects 0.000 description 18
- 238000011084 recovery Methods 0.000 description 17
- 230000003071 parasitic effect Effects 0.000 description 10
- 238000000151 deposition Methods 0.000 description 8
- 238000002513 implantation Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 230000005684 electric field Effects 0.000 description 6
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 6
- 230000009471 action Effects 0.000 description 5
- 230000005611 electricity Effects 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 230000001413 cellular effect Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 4
- 239000002210 silicon-based material Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000001976 improved effect Effects 0.000 description 3
- 238000001727 in vivo Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000024241 parasitism Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical compound [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007123 defense Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000036541 health Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000009776 industrial production Methods 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000037230 mobility Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000012913 prioritisation Methods 0.000 description 1
- 230000001603 reducing effect Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
A kind of silicon carbide MOSFET device of present invention offer and its manufacturing method, by doing the P injections of silicon carbide depth in specified region, and through etching groove above silicon carbide depth P doped regions, deposit metal or polysilicon, the metal or polysilicon deposited is in direct contact with silicon carbide N-extension, form Schottky contacts or Si/SiC heterojunctions with rectification characteristic, the improvement to Conventional silicon carbide UMOSFET basic performances while having apparent optimization function, realize the integrated of how sub- rectifying device, while greatly optimizing device third quadrant working performance, also reduce device gate-drain capacitance, improve devices switch speed.
Description
Technical field
The invention belongs to power semiconductor technologies, in particular to a kind of metal oxide semiconductor field-effect
(MOSFET) device architecture and its manufacturing method.
Background technology
According to statistics, 90% or more electricity consumption is controlled by power device in the world.Power device and its module are that realization is more
The conversion of kind electrical energy form provides efficient approach, in fields such as national defense construction, communications and transportation, industrial production, health cares
It is widely applied.Since the fifties in last century first item power device applications, per the release of generation power device, all make
The energy is obtained more efficiently to convert and use.The history of power semiconductor, that is, power semiconductor are weeded out the old and bring forth the new
History.
Conventional power devices and module are dominated by silicon-based power devices, mainly double with thyristor, power P IN devices, power
Based on the devices such as pole junction device, power MOSFET and isolated-gate field effect transistor (IGFET), obtained in full power range
It is widely applied, the master of power semiconductor has been captured with its long history, very ripe designing technique and technology
Lead market.However, increasingly maturation, its characteristic of silicon-based power devices with power semiconductor technologies development gradually approach its reason
By the limit.While researcher makes great efforts to seek more preferably parameter in the narrow optimization space of silicon-based power devices, it is also noted that
The third generations wide bandgap semiconductor materials such as SiC, GaN are excellent in the fields such as high-power, high-frequency, high temperature resistant, radioresistance
Material property.
Silicon carbide MOSFET device is the generation semiconductor devices manufactured with semiconductor material with wide forbidden band silicon carbide.Carbonization
The many attracting characteristics of silicon materials, critical breakdown electric field intensity, high thermal conductivity, the big forbidden band of such as 10 times of silicon materials are wide
Degree and high electronics saturation drift velocity etc. make SiC material become the research hotspot of power semiconductor in the world, and
High power applications occasion, such as high-speed railway, hybrid vehicle, intelligent high-pressure direct current transportation, silicon carbide device are endowed
Very high expectation.Silicon carbide power device is notable to the reducing effect of power attenuation simultaneously so that silicon carbide power device quilt
It is described as " green energy resource " device of drive " new energy revolution ".However because the undesirable of MOS raceway grooves leads to MOS channel mobilities
It is too low, significantly limit silicon carbide MOSFET on state current density.Therefore, with higher gully density, to bigger
The extensive concern and research that the silicon carbide UMOSFET of on state current density is subject to.Although silicon carbide UMOSFET has more low pass state
Resistance and greater compactness of cellular layout, due to the problem that bottom gate electric field across oxide is excessively high, make for a long time to silicon carbide UMOSFET
With integrity problem is brought, device poor robustness is caused.Conventional silicon carbide UMOSFET structures are as shown in Figure 1.
Silicon carbide MOSFET device is in the application, it usually needs is used with a diode inverse parallel.It can there are two types of mode
To reach this purpose.One is directly using device Pbase and N-The parasitic diode that area is formed.The parasitism silicon carbide two
Pole pipe conduction voltage drop is big (silicon carbide PN junction conduction voltage drop is about 3.1V), and poor (drift region when forward conduction of reverse recovery characteristic
Conductance modulation injects excessive carrier) cause high power attenuation, this with emphasize environmentally protective application theory instantly
It runs counter to；Cause working efficiency low because operating rate is low simultaneously, for silicon carbide MOSFET device in inverter circuit, copped wave electricity
It is totally unfavorable in the applications such as road；The second is by the way that device and external diode inverse parallel are used.However this method causes to produce
The reduction of reliability after the rising of cost and metal connecting line so that the popularization of silicon carbide MOSFET device in practical applications by
Prodigious obstruction is arrived.
Invention content
The present invention is in view of the above-mentioned problems, propose a kind of silicon carbide MOSFET device that can optimize in inverter circuit, chopper circuit
Deng present in application due to gate medium electric field it is excessively high caused by poor robustness, power attenuation is high, working efficiency is low, production cost
The silicon carbide MOSFET device and its manufacturing method of the problems such as higher.Specifically, the present invention passes through in Conventional silicon carbide
On the basis of UMOSFET structures, by doing the P injections of silicon carbide depth in specified region, and through ditch above silicon carbide depth P doped regions
Groove etched, deposit metal or polysilicon.The metal or polysilicon deposited is in direct contact with silicon carbide N-extension, is formed with whole
The Schottky contacts or Si/SiC heterojunctions of properties of flow are by changing metal material, technology controlling and process and silicon carbide N-extension
Concentration can regulate and control schottky barrier height, to form the Schottky contacts compared with low conduction voltage drop (Von).Usual contact Von
Range in 0.8V~2V.To realize internal collection of the positive working performance better than the Schottky diode of parasitic diode
At.Since the diode is how sub- device, since there is no few sub- storage in reversely restoring process, there is faster Reverse recovery
Time, lower reverse recovery loss and more preferably Reverse recovery reliability have more compared with parasitic diode
Reverse recovery performance.Mode of the improvement relative to one diode of external inverse parallel, significantly reduces power electronic system body
Product reduces encapsulation and spends.Simultaneously because without metal lead wire between diode, avoid that metal lead wire brings posts
It comes into force and answers, to improve system application reliability.Meanwhile relative to the mode of numerous internal single-chip integration diodes, this hair
Bright structure has more compact cell density.Meanwhile double deep silicon carbide P-doped zones designed by the present invention contribute to lifter
The resistance to voltage levels of part, and device gate dielectric layer electric field is reduced, thus the basic performance to traditional UMOSFET devices and permanent application
Reliability is also substantially improved.Simultaneously as promotion of double depth silicon carbide P-doped zones for device pressure resistance so that the areas JFET
Doping can effectively improve, therefore there is institute's invention device lower ratio to lead Ron.sp.In addition, integrating how sub- rectifying device has
It leaks electricity low feature.Therefore structure of the invention advantage with good performance.
For achieving the above object, technical solution of the present invention is as follows：
1, a kind of silicon carbide MOSFET device, including set gradually from bottom to top metal-drain 1, silicon carbide N+Substrate 2
And silicon carbide N-Epitaxial layer 3；The silicon carbide N-3 upper left side of epitaxial layer has the first source groove, the first source beneath trenches from upper and
There is down silicon carbide P+ doped regions 5 and silicon carbide P-doped zone 4；The silicon carbide N-3 upper right side of epitaxial layer has the second source
Groove, the second source beneath trenches have silicon carbide P+ doped regions 5 and silicon carbide P-doped zone 4 from top to bottom；First, second
Source groove fills and forms Schottky contact metal 14；There is 3 top of the silicon carbide N-epitaxial layer gate groove, depth to be shallower than
Two source grooves, inside gate groove and surface have a gate structure, and the gate structure includes gate dielectric layer 10 from bottom to top, more
Crystal silicon grid 11 and grid 12, gate dielectric layer 10 separate polysilicon gate 11 and silicon carbide body from 11 top of polysilicon gate passes through
Grid 12 is drawn；Polysilicon gate 11 is inside gate groove, and grid 12 is on gate groove surface；Have respectively between source groove and gate groove
There are the first mesa structure, the second mesa structure, the first mesa structure, the second mesa structure are by the areas silicon carbide Pbase 7, carbonization
The contact zones silicon P+ 8 and silicon carbide N+source region 9 are constituted, wherein the contact zones silicon carbide P+ 8 and silicon carbide N+source region 9 are located at carbonization
7 top of the areas silicon Pbase, the contact zones silicon carbide P+ 8 are contacted with source trench contact, silicon carbide N+source region 9 with gate groove, and silicon carbide
The areas Pbase 7 are then contacted with source groove, gate groove simultaneously, and its depth is shallower than source groove and gate groove；Source trench metal and carbonization
Silicon N- epitaxial layers 3 are in direct contact to form the Schottky contacts with rectification characteristic in source trenched side-wall bottom；Device surface is by one
Layer source metal 6 covers, and source metal 6 is mutually isolated by boron-phosphorosilicate glass BPSG13 with grid 12.
It is preferred that carbofrax material Si, Ge, GaAs, GaN, diamond, SiGe, gallium oxide semi-conducting material
Instead of.
It is preferred that 14 region of the Schottky contact metal replaces with polysilicon 15.
It is preferred that having split-gate polysilicons 16 below the gate structure.
It is preferred that the bottom of the Schottky contact metal 14 or polysilicon 15 extends to the doping of silicon carbide p-type
Area 4 and the middle part of silicon carbide P+ doped regions 5, contact with silicon carbide N-epitaxial layer 3.As shown in Figure 10.
It is preferred that 14 lower section of Schottky contact metal is dielectric layer 17.
It is preferred that source beneath trenches in Z-direction there is discontinuous groove, gash depth to be less than or equal to carbon
4 depth of SiClx P-doped zone, wherein the trench interiors are deposited with Schottky contact metal 14 or polysilicon 15, channel bottom
For silicon carbide N-epitaxial layer 3.
Further, as shown in figure 4, the split-gate structures include split-gate polysilicons 16 and surround
The dielectric layer 17 of split-gate polysilicons 16 forms；
Further, the silicon carbide P-doped zone 4 can be adulterated through One Diffusion Process with forming broader silicon carbide p-type
Area 4；
Further, the silicon carbide P-doped zone 4, silicon carbide P+ doped regions 5 can be dielectric layer 17；
Further, a kind of silicon carbide MOSFET device, used in width, small gap material is not limited only to be carbonized
Silicon, silicon materials, for other by wide, the combination of small gap material is equally applicable.
2, for achieving the above object, the present invention also provides a kind of manufacturing method of above-mentioned silicon carbide MOSFET device,
Include the following steps：
1st step：Silicon carbide plate is chosen, as subsequent silicon carbide N+substrate 2, silicon carbide N-epi region 3；
2nd step：By energetic ion injection technology, Al ion implantation is carried out, forms the areas silicon carbide Pbase 7, or by outer
The mode of prolonging forms the areas silicon carbide Pbase 7, then forms the device behind the areas silicon carbide Pbase 7；
3rd step：By photoetching, ion injecting process, Al ion implantation is carried out using PSD mask plates, forms silicon carbide P+
Contact zone 8；
4th step：By processes such as photoetching, ion implantings, phosphonium ion injection is carried out using NSD mask plates, forms silicon carbide N
+ source region 9；
5th step：By trench etch process, the source groove of specified size is etched using Trench mask plates；
6th step：Al ion implantation is carried out by photoetching, ion injecting process, forms silicon carbide P-doped zone 4；The step
Or deeper source groove is formed by etching in the 5th step, then silicon carbide P-doped zone is formed through extension, etching technics again
4；
7th step：Al ion implantation is carried out by photoetching, ion injecting process, forms silicon carbide P+ doped regions 5；
8th step：By deposit and etching technics, in source, channel bottom deposits one layer of metal, forms Schottky contact metal
14, remove extra metal by etching；
9th step：By trench etch process, the gate groove of specified size is etched using Trench mask plates；
10th step：Gate dielectric layer 10 is formed by dry-oxygen oxidation technique；
11st step：By deposit and etching technics, one layer of polysilicon is deposited in gate groove, forms polysilicon gate 11, is led to
Over etching removes extra polysilicon；
12nd step：Grid 12 is formed by deposit, photoetching and etching technics；
13rd step：Boron-phosphorosilicate glass BPSG13 is formed by deposit, photoetching and etching technics；
14th step：Source metal 6, metal-drain 1, so far, device are formed by deposit, photoetching and etching technics respectively
It completes.
Further, gate groove can also be initially formed, and after completing gate structure, re-form source groove；
Further, deeper gate groove can also be formed in the 9th step, and channel bottom and side wall is aoxidized.And
In channel bottom deposit split-gate polysilicons 16, through dielectric layer deposited 17, etch media layer 17, depositing polysilicon grid 11,
Split-gate structures are formed, as shown in Figure 4；
Further, in the 8th step, the source trench schottky contacting metal 14 deposited also can be replaced 15 material of polysilicon
Material；
Further, after the 6th step forms silicon carbide P-doped zone 4, can make to be formed broader by high-temperature diffusion process
Silicon carbide P-doped zone 4；
Further, when the 5th step forms source groove, etching dynamics can be increased, to form deeper etching groove.And
It is described below by the replacement of the 6th, the 7th step：By deposit, etching technics, in source, channel bottom deposits to form certain thickness oxygen
Change layer.Etched technique forms the gate dielectric layer 10 that apparent height is less than the areas silicon carbide Pbase 7.
Further, after the 5th step forms source groove, it can be further added by primary etching, formed not in former source channel bottom
Continuous groove.Secondarily etched gash depth is equal to 4 depth of silicon carbide P-doped zone formed in the later stage；
Further, after the 5th step forms source groove, it can be further added by primary etching, formed not in former source channel bottom
Continuous groove.Secondarily etched gash depth is less than 4 depth of silicon carbide P-doped zone formed in the later stage；
Further, after the 5th step forms source groove, it can be further added by primary etching, formed and connected in former source channel bottom
Continuous groove, secondarily etched gash depth are equal to 4 depth of silicon carbide P-doped zone formed in the later stage.
3, following scheme of the invention can also solve the problems, such as to be carried in " background technology "：Specifically, the present invention by
On the basis of Conventional silicon carbide UMOSFET structures (such as Fig. 1), the P injections of silicon carbide depth are done again by specified region, and in two
It is above silicon carbide depth P doped regions and intermediate through etching groove, deposit metal or polysilicon.The metal or polysilicon and carbon deposited
SiClx N- extensions are in direct contact, and form Schottky contacts or Si/SiC heterojunctions with rectification characteristic.The usual contact
Von is in the range of 0.6V~1.8V.To realize positive working performance better than in the Schottky diode body of parasitic diode
It is integrated.Schottky diode is how sub- device, since there is no few sub- storage in reversely restoring process, is had reversed faster extensive
It answers time, lower reverse recovery loss and more Reverse recovery reliability has more compared with parasitic diode
Reverse recovery performance.Mode of the improvement relative to one diode of external inverse parallel, significantly reduces power electronic system
Volume reduces encapsulation and spends.Simultaneously because without the metal lead wire between diode, avoid what metal lead wire was brought
Ghost effect, to improve system application reliability.Meanwhile relative to the mode of numerous monolithically integrated diodes in vivo, originally
Inventive structure has more compact cell density.Likewise, structure of the invention is to device basic performance, including voltage block energy
The promotion of power, device application reliability more permanent than the reduction of reduction, how sub- element leakage led and device can promotion have
Prodigious effect of optimization.Therefore structure of the invention has good electric property advantage.
For achieving the above object, the present invention also provides second of silicon carbide MOSFET device, structure is as follows：
Including set gradually from bottom to top metal-drain 1, silicon carbide N+Substrate 2 and silicon carbide N-Epitaxial layer 3；The carbon
SiClx N-3 upper left side of epitaxial layer has first grid structure, the silicon carbide N-3 upper right side of epitaxial layer has second grid structure,
First, second gate structure includes grid 12, polysilicon gate 11 and gate dielectric layer 10, wherein 11 quilt of polysilicon gate
Gate dielectric layer 10 surrounds, and top is drawn by grid 12, the silicon carbide N-3 top of epitaxial layer has active groove, the source ditch
Slot is deposited by Schottky contact metal 14 and is filled, and Schottky contact metal 14 is in direct contact with silicon carbide N-epitaxial layer 3, forms Xiao
Te Ji is contacted, and is respectively provided with the first mesa structure, the second mesa structure between source groove and gate structure, the first mesa structure,
Second mesa structure is made of the areas silicon carbide Pbase 7, the contact zones silicon carbide P+ 8 and silicon carbide N+source region 9, wherein carbonization
The contact zones silicon P+ 8 and silicon carbide N+source region 9 are located at the top of areas silicon carbide Pbase 7, the contact zones silicon carbide P+ 8 and source trench contact,
Silicon carbide N+source region 9 is contacted with gate structure, and the areas silicon carbide Pbase 7 are then contacted with source groove, gate structure simultaneously, and its
Depth is shallower than source groove and gate structure；14 lower section both sides of the Schottky contact metal, 7 lower section of the areas partially carbonized silicon Pbase
With P-doped zone, depth is deeper silicon carbide P-doped zone 4 in P-doped zone, and depth is more shallow, width is narrower for carbon
SiClx P+ doped regions 5；Silicon carbide P+ doped regions 5 form Ohmic contact with Schottky contact metal 14, and the device surface is by one
Layer source metal 6 covers, and source metal 6 is separated by with grid 12 with boron-phosphorosilicate glass BPSG13.
It is preferred that carbofrax material Si, Ge, GaAs, GaN, diamond, SiGe, gallium oxide semi-conducting material
Instead of.
It is preferred that former Schottky contact metal 14 replaces with polysilicon 15.
It is preferred that having split-gate polysilicons 16 below two gate structures.
It is preferred that the bottom of the Schottky contact metal 14 or polysilicon 15 extends to the doping of silicon carbide p-type
Area 4 and the middle part of silicon carbide P+ doped regions 5, contact with silicon carbide N-epitaxial layer 3.
It is preferred that the silicon carbide N of Schottky contact metal 14 and 7 lower part of the areas silicon carbide Pbase-Epitaxial layer 3 is straight
Contact so that it not only forms rectifying contact in metal bottom and silicon carbide N-epitaxial layer 3, also in source channel bottom side wall with
Silicon carbide N-extension 3 contacts, and forms rectifying contact.
It is preferred that the silicon carbide P-doped zone 4, silicon carbide P+ doped regions 5 replace with dielectric layer 17.
It is preferred that the subregion that 14 bottom of the Schottky contact metal is contacted with silicon carbide N-epitaxial layer 3
There is 15th area of polysilicon, the region to form Si/SiC heterojunctions with silicon carbide N-epitaxial layer 3 for lower section.
It is preferred that source beneath trenches both sides in Z-direction there is discontinuous groove, gash depth to be equal to or small
In 4 depth of silicon carbide P-doped zone, trench interiors are equally deposited with Schottky contact metal 14 and are filled.Channel bottom is carbonization
Silicon N- epitaxial layers 3.
Further, the gate structure bottom section has split-gate structures, as shown in figure 27.The split-
Gate structures include split-gate polysilicons 16 and surround the dielectric layer 17 of split-gate polysilicons 16；
Further, the structure has 14 depth and width of Schottky contact metal of bigger so that it is not only in gold
Belong to bottom and form rectifying contact with silicon carbide N-extension 3, also contacts, formed with silicon carbide N-extension 3 in source channel bottom side wall
Rectifying contact；
Further, a kind of silicon carbide MOSFET device, used in width, small gap material is not limited only to be carbonized
Silicon, silicon materials, for other by wide, the combination of small gap material is equally applicable.
4, for achieving the above object, the present invention also provides a kind of manufacturing methods of silicon carbide MOSFET device, including
Following steps：
1st step：Silicon carbide plate is chosen, that is, is used as subsequent silicon carbide N+substrate 2, silicon carbide N-epitaxial layer 3；
2nd step：By energetic ion injection technology, carry out Al ion implantation, form the areas silicon carbide Pbase 7, the step or
The areas silicon carbide Pbase 7 are formed by extensional mode；
3rd step：By photoetching, ion injecting process, Al ion implantation is carried out using PSD mask plates, forms silicon carbide P+
Contact zone 8；
4th step：By photoetching, ion injecting process, phosphonium ion injection is carried out using NSD mask plates, formed silicon carbide N+
Source region 9；
5th step：By trench etch process, the source groove of specified size is etched using Trench mask plates；
6th step：By processes such as photoetching, ion implantings, Al ion implantation is carried out at an angle, forms silicon carbide p-type
Doped region 4；
7th step：By processes such as photoetching, ion implantings, Al ion implantation is carried out, forms silicon carbide P+ doped regions 5；
8th step：By deposit and etching technics, in source, channel bottom deposits one layer of metal, forms Schottky contact metal
14, remove extra metal by etching；
9th step：By trench etch process, the gate groove of specified size is etched using Trench mask plates；
10th step：Gate dielectric layer 10 is formed by dry-oxygen oxidation technique；
11st step：By deposit and etching technics, one layer of polysilicon is deposited in gate groove, forms polysilicon gate 11, is led to
Over etching removes extra polysilicon；
12nd step：Grid 12 is formed by deposit, photoetching and etching technics；
13rd step：Boron-phosphorosilicate glass BPSG13 is formed by deposit, photoetching and etching technics；
14th step：Source metal 6, metal-drain 1 are formed by deposit, photoetching and etching technics respectively；So far, device
It completes.
Further, in the 8th step, the source trench schottky contacting metal 14 deposited also can be replaced 15 material of polysilicon
Material；
Further, deeper gate groove can also be formed in the 9th step, and channel bottom and side wall is aoxidized.And
In channel bottom deposit split-gate polysilicons 16, through depositing gate dielectric layer 10, etching gate dielectric layer 10, depositing polysilicon grid
11, split-gate structures are formed, as shown in figure 27；
Further, in the 5th step source etching groove, etching depth and width can be increased, meanwhile, in the 6th, the 7th step
It when Al ion implantation, injects in vertical manner so that Schottky contacts are not only realized in source channel bottom, while also in Yuan Gou
Slot two side is formed.
Further, when the 5th step forms source groove, etching dynamics can be increased, to form deeper etching groove.And
It is described below by the replacement of the 6th, the 7th step：By deposit, etching technics, in source, channel bottom deposits to form certain thickness oxygen
Change layer.Etched technique forms the gate dielectric layer 10 that apparent height is less than the areas silicon carbide Pbase 7.
Further, secondarily etched in the progress of source channel bottom after the 5th step forms source groove, and before the 6th step,
Polycrystalline silicon deposit filling is carried out to the secondary groove, forms 15th area of polysilicon.
Further, after the 5th step forms source groove, it can be further added by primary etching, formed not in former source channel bottom
Continuous groove.Secondarily etched gash depth is equal to 4 depth of silicon carbide P-doped zone formed in the later stage；
Further, after the 5th step forms source groove, it can be further added by primary etching, formed not in former source channel bottom
Continuous groove.Secondarily etched gash depth is less than 4 depth of silicon carbide P-doped zone formed in the later stage；
Further, gate groove can also be initially formed, and after completing gate structure, re-form source groove.
The principle of the invention set forth below：
Silicon carbide MOSFET device is in the application, it usually needs is used with a diode inverse parallel.If not considering in vivo
Single-chip integration then can reach this purpose there are two types of mode.One is directly using silicon carbide MOSFET device silicon carbide
The parasitic silicon carbide PiN diodes that the areas Pbase are formed with silicon carbide N-area, silicon carbide N+substrate.Parasitism silicon carbide PiN is positive
Conduction voltage drop Von is about 3.1V, and great forward conduction voltage drop is totally unfavorable for the application under low pressure and low power, significantly increases
Device on-state loss.Simultaneously as the device belongs to bipolar device, the product of few son will be generated because conductance modulation acts in on-state
It is tired.Although the accumulation of few son can reduce on-state voltage drop in the on-state, for switching transient, it is especially off transient state, due to
Turn-off time caused by few son stores increases, turn-off power loss increases, inverse peak current increases and turns off reliability decrease etc.
Problem causes the very poor reverse recovery characteristic of the parasitic diode.Therefore for antiparallel diode, it should have low lead
It is logical pressure drop Von, the basic demand that restores soon；The second is by the way that the diode inverse parallel of device and device exterior is used.Although
The basic demand that this method has reached low conduction voltage drop Von, restored soon, but this method is because device number increases, power system
Increase, cooling requirements are promoted etc., and many factors cause the rising of production cost and the reduction of reliability after metal connecting line increase,
So that selection and the non-optimal of parallel connection outside diode.This also promotes other formation for realizing anti-paralleled diode method.This hair
It is bright by doing silicon carbide depth P injection in specified region, and in silicon carbide depth P doped regions above through etching groove, deposit metal or
Polysilicon.The metal or polysilicon deposited is in direct contact with silicon carbide N-extension, forms the schottky junctions with rectification characteristic
Tactile or Si/SiC heterojunctions, as shown in Figure 2.When institute's inventive structure is in MOSFET blocking work, due to the resistance to splenium of device
Divide and is provided by silicon carbide P-doped zone 4 and silicon carbide N-epitaxial layer 3, improvement the carrying for traditional structure voltage endurance capability of device
Rising has optimization function；Due to the shielding action of silicon carbide P-doped zone 4, Schottky contacts or heterojunction leak electricity
To be greatly reduced, while component grid oxidizing layer electric field is reduced, to improve the permanent application reliability of device.Institute's invention device
When working in MOSFET forward directions, since silicon carbide P-doped zone is to the promotion of device avalanche breakdown pressure resistance and to gate dielectric layer
Protection, device JFET region dopings can do more, lead value to reduce MOSFET ratios, optimize break-over of device performance；
Structure of the invention has great optimization function for the work of device third quadrant.The barrier height being previously mentioned can pass through
The modes such as metal species, process conditions and silicon carbide N-extension are adjusted, the Schottky contacts that Von is about 0.6V~2V are formed；
Simultaneously because the defencive function of silicon carbide P-doped zone so that the electric leakage of Schottky contacts interface is smaller.Have been generally acknowledged that silicon carbide
The Von of PiN diodes is 3.1V or so.The insertion of Schottky-barrier diode greatly reduces under the work of device third quadrant
On-state loss, since there is no sub- storage effect less, have simultaneously because Schottky-barrier diode belongs to how sub- device
Shorter reverse recovery time, lower turn-off power loss, lower Reverse recovery peak point current, more preferably in reversely restoring process
The reliability of device；In addition, since Schottky-barrier diode integrated in vivo does not increase device area, make invention device
It is arranged with compact cellular, to the on state current with bigger.Since gate leakage capacitance has very devices switch speed
Big influence, therefore in order to further enhance devices switch speed, the present invention also provides a kind of structures, such as Fig. 4, Tu26Suo
Show.This construction reduces the facing areas between device gate structures and silicon carbide N-extension, that is, reduce gate-drain charge, to drop
Low device gate-drain capacitance has greatly improved effect for devices switch speed tool；
The Schottky contact metal 14 can also use polysilicon 15 to substitute.By polysilicon 15 and silicon carbide N-extension 3
In source, channel bottom side wall, which contacts, to form Si/SiC hetero-junctions.According to pertinent literature, which has rectification characteristic.It is just
It is about 1.1V to conduction voltage drop Von.Equally have for the work of device third quadrant relative to parasitic diode and is extremely improved
Effect.Simultaneously as it is similarly how sub- device, and it is similar to Schottky diode, equally there is splendid Reverse recovery performance；
In order to promote device pressure resistance, the present invention also increases 4 lateral dimension of silicon carbide P-doped zone in device architecture.The increasing of the part
The promotion of big 10 reliability of promotion and gate dielectric layer for being conducive to device pressure resistance；In order to further increase diode operation pattern
Under device electrology characteristic, the present invention also provides another new constructions, as shown in Figure 8, Figure 9.By in source channel bottom
Carry out it is secondarily etched, and in the groove carry out polysilicon deposit.And source groove is still deposited with Schottky contact metal.From whole
For the increase situation for flowing contact surface, which increases 50% or so rectifying contact face, to increase diode applications
When conducting junction.Since Si/SiC hetero-junctions electric leakage performance is much better than Schottky contacts, while P-type silicon is for Schottky junction
With good shielding action so that the electric leakage of Schottky junction further decreases.To further increase the work of device third quadrant
Performance, institute's inventive structure also proposed another optimization structure.I.e. by continuing etching source channel bottom, mixed in silicon carbide p-type
4 inside of miscellaneous area forms discontinuous groove structure.The groove structure is equally deposited with Schottky contact metal 14 or polysilicon 15
Filling.The depth of secondary etching groove is equal to or less than 4 depth of silicon carbide P-doped zone, is connect with increasing Schottky/hetero-junctions
Contacting surface is accumulated, to optimised devices third quadrant working performance.It is described another for being proposed the problem of introducing in background introduction
Kind prioritization scheme, basic principle and first scheme of the invention are essentially identical, therefore details are not described herein again.
In conclusion beneficial effects of the present invention are：
One, structure of the invention realizes how sub- rectifying device, including Schottky-barrier diode and Si/SiC hetero-junctions
Internal insertion so that device relative to device inside parasitic diode, has more preferably on-state in third quadrant operation interval
Performance and Reverse recovery performance, including shorter reverse recovery time, lower turn-off power loss, lower Reverse recovery peak value electricity
Stream, more preferably in reversely restoring process device reliability.Meanwhile integrate how sub- rectifying device have the characteristics that electric leakage it is low；
Two, structure of the invention relative to Conventional silicon carbide UMOSFET there is higher pressure resistance and lower ratio to lead
Ron.sp, simultaneously because gate dielectric layer maximum electric field is minimized so that the permanent application reliability of device is significantly enhanced,
With good robustness；
Three, relative to the mode of external anti-paralleled diode, structure of the invention reduces metal lead wire number of interconnections, reduces
Parasitic inductance, improves device reliability energy；System device number is reduced, system bulk is reduced, reduces heat dissipation system
System volume；Packaging cost is reduced, to which production cost is minimized；
Four, there is structure of the invention compact cellular to arrange, relative to Conventional silicon carbide UMOSFET (SiC UMOSFET)
Area is almost without increase so that device production cost further decreases；
Five, the present invention is optimized for device dynamic performance, it is proposed that split-gate structures.The structure significantly drops
Low grid-silicon carbide N-extension facing area, reduce in device opening process institute must grid charge, so reduce device gate
Drain capacitance improves devices switch speed；
Six, structure of the invention is compatible with Conventional silicon carbide UMOSFET device production process.With simple for process, it is easy to real
Existing advantage.
Seven, the present invention works while optimizing Conventional silicon carbide UMOSFET basic performances also directed to device third quadrant
Performance optimizes, and has obtained more preferably diode applications performance.
Description of the drawings
Fig. 1 is Conventional silicon carbide UMOSFET device cellular structural schematic diagrams；
Fig. 2 is the basic structure cell schematic diagram of the double groove MOSFET devices of a kind of silicon carbide that embodiment 1 provides；
Fig. 3 is the basic structure cell schematic diagram of the double groove MOSFET devices of a kind of silicon carbide that embodiment 2 provides；
Fig. 4 is the basic structure cell schematic diagram of the double groove MOSFET devices of a kind of silicon carbide that embodiment 3 provides；
Fig. 5 is the basic structure cell schematic diagram of the double groove MOSFET devices of a kind of silicon carbide that embodiment 4 provides；
Fig. 6 is the basic structure cell schematic diagram of the double groove MOSFET devices of a kind of silicon carbide that embodiment 5 provides；
Fig. 7 is the region 1 structure of embodiment " Region A " Z-direction schematic diagram；
Fig. 8 is the basic structure cell schematic diagram of the double groove MOSFET devices of a kind of silicon carbide that embodiment 6 provides；
Fig. 9 is the basic structure cell schematic diagram of the double groove MOSFET devices of a kind of silicon carbide that embodiment 7 provides；
Figure 10 is the basic structure cell schematic diagram of the double groove MOSFET devices of a kind of silicon carbide that embodiment 8 provides；
Figure 11 is the silicon carbide substrates schematic diagram that the embodiment of the present invention 9 provides；
Figure 12 is the offer of the embodiment of the present invention 9 by 7 schematic diagram of the areas ion implantation technology formation silicon carbide Pbase；
Figure 13 is being shown by the contact zones the processes such as photoetching, ion implanting formation silicon carbide P+ 8 for the offer of the embodiment of the present invention 9
It is intended to；
Figure 14 be the embodiment of the present invention 9 provide by processes such as photoetching, ion implantings, utilize NSD mask plates to carry out phosphorus
Ion implanting forms 9 schematic diagram of silicon carbide N+source region；
Figure 15 be the embodiment of the present invention 9 provide by trench etch process, etched using Trench mask plates specified
The source groove schematic diagram of size；
Figure 16 is the offer of the embodiment of the present invention 9 by the processes such as photoetching, ion implanting progress Al ion implantation, formation carbon
4 schematic diagram of SiClx P-doped zone；
Figure 17 is the offer of the embodiment of the present invention 9 by the processes such as photoetching, ion implanting progress Al ion implantation, formation carbon
5 schematic diagram of SiClx P+ doped regions；
Figure 18 be the embodiment of the present invention 9 provide by deposit and etching technics, in source channel bottom deposit one layer of metal,
Form 14 schematic diagram of Schottky contact metal；
Figure 19 be the embodiment of the present invention 9 provide by trench etch process, etched using Trench mask plates specified
The gate groove schematic diagram of size；
Figure 20 is the offer of the embodiment of the present invention 9 by dry-oxygen oxidation technique formation 10 schematic diagram of gate dielectric layer；
Figure 21 is being illustrated by deposit, photoetching and etching technics formation polysilicon gate 11 for the offer of the embodiment of the present invention 9
Figure；
Figure 22 is the offer of the embodiment of the present invention 9 by deposit, photoetching and etching technics formation 12 schematic diagram of grid；
Figure 23 is the offer of the embodiment of the present invention 9 by deposit, photoetching and etching technics formation boron-phosphorosilicate glass
BPSG13 schematic diagrames；
Figure 24 is the offer of the embodiment of the present invention 9 by deposit, photoetching and etching technics formation source electrode 6, metal-drain 1
Schematic diagram.
Figure 25 is the basic structure cell schematic diagram of the double groove MOSFET devices of a kind of silicon carbide that embodiment 10 provides；
Figure 26 is the basic structure cell schematic diagram of the double groove MOSFET devices of a kind of silicon carbide that embodiment 11 provides；
Figure 27 is the basic structure cell schematic diagram of the double groove MOSFET devices of a kind of silicon carbide that embodiment 12 provides；
Figure 28 is the basic structure cell schematic diagram of the double groove MOSFET devices of a kind of silicon carbide that embodiment 13 provides；
Figure 29 is the basic structure cell schematic diagram of the double groove MOSFET devices of a kind of silicon carbide that embodiment 14 provides；
Figure 30 is the basic structure cell schematic diagram of the double groove MOSFET devices of a kind of silicon carbide that embodiment 15 provides；
Figure 31 is the region 10 structure of embodiment " Region A " Z-direction schematic diagram；
Figure 32 is the basic structure cell schematic diagram of the double groove MOSFET devices of a kind of silicon carbide that embodiment 16 provides；
Figure 33 is the basic structure cell schematic diagram of the double groove MOSFET devices of a kind of silicon carbide that embodiment 17 provides；
Figure 34 is the silicon carbide substrates schematic diagram that the embodiment of the present invention 18 provides；
Figure 35 is the offer of the embodiment of the present invention 18 by 7 schematic diagram of the areas ion implantation technology formation silicon carbide Pbase；
Figure 36 be the embodiment of the present invention 18 provide by processes such as photoetching, ion implantings, utilize PSD mask plates to carry out aluminium
Ion implanting forms 8 schematic diagram of the contact zones silicon carbide P+；
Figure 37 be the embodiment of the present invention 18 provide by processes such as photoetching, ion implantings, utilize NSD mask plates to carry out phosphorus
Ion implanting forms 9 schematic diagram of silicon carbide N+source region；
Figure 38 be the embodiment of the present invention 18 provide by trench etch process, etched using Trench mask plates specified
The source groove schematic diagram of size；
Figure 39 be the embodiment of the present invention 18 provide by processes such as photoetching, ion implantings, with certain incident angle into
Row Al ion implantation forms 4 schematic diagram of silicon carbide P-doped zone；
Figure 40 is the offer of the embodiment of the present invention 18 by the processes such as photoetching, ion implanting, progress Al ion implantation, formation
5 schematic diagram of silicon carbide P+ doped regions；
Figure 41 be the embodiment of the present invention 18 provide by deposit and etching technics, in source channel bottom deposit one layer of gold
Belong to, forms 14 schematic diagram of Schottky contact metal；
Figure 42 be the embodiment of the present invention 18 provide by trench etch process, etched using Trench mask plates specified
The gate groove schematic diagram of size；
Figure 43 is the offer of the embodiment of the present invention 18 by dry-oxygen oxidation technique formation 10 schematic diagram of gate dielectric layer；
Figure 44 is being illustrated by deposit, photoetching and etching technics formation polysilicon 11 for the offer of the embodiment of the present invention 18
Figure；
Figure 45 is the offer of the embodiment of the present invention 18 by deposit, photoetching and etching technics formation 12 schematic diagram of grid；
Figure 46 is the offer of the embodiment of the present invention 18 by deposit, photoetching and etching technics formation boron-phosphorosilicate glass
BPSG13 schematic diagrames；
Figure 47 is being shown by deposit, photoetching and etching technics formation source electrode 6, drain electrode 1 for the offer of the embodiment of the present invention 18
It is intended to.
1 is metal-drain；2 be silicon carbide N+substrate；3 be silicon carbide N-epitaxial layer；4 be silicon carbide P-doped zone；5 are
Silicon carbide P+ doped regions；6 be source metal；7 be the areas silicon carbide Pbase；8 be the contact zones silicon carbide P+；9 be silicon carbide N+source
Area；10 be gate dielectric layer；11 be polysilicon gate；12 be grid；13 be boron-phosphorosilicate glass BPSG；14 be Schottky contact metal；
15 be polysilicon；16 be split-gate polysilicons, and 17 be dielectric layer.
Specific implementation mode
Illustrate that embodiments of the present invention, those skilled in the art can be by this specification below by way of specific specific example
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Embodiment 1：
A kind of silicon carbide MOSFET device, the structure cell of basic structure as shown in Fig. 2, including setting successively from bottom to top
The metal-drain 1 set, silicon carbide N+Substrate 2 and silicon carbide N-Epitaxial layer 3；The silicon carbide N-3 upper left side of epitaxial layer has first
Source groove, the first source beneath trenches have silicon carbide P+ doped regions 5 and silicon carbide P-doped zone 4 from top to bottom；The carbonization
Silicon N-3 upper right side of epitaxial layer have the second source groove, the second source beneath trenches from top to bottom have silicon carbide P+ doped regions 5 and
Silicon carbide P-doped zone 4；First, second source groove, which is filled, forms Schottky contact metal 14；Silicon carbide N-the epitaxial layer
There is gate groove, depth to be shallower than two source grooves for 3 tops, and gate groove inside and surface have gate structure, the grid knot
Structure includes from bottom to top gate dielectric layer 10, polysilicon gate 11 and grid 12, and gate dielectric layer 10 is polysilicon gate 11 and silicon carbide
Body is separated from 11 top of polysilicon gate is drawn by grid 12；Polysilicon gate 11 is inside gate groove, and grid 12 is in gate groove table
Face；The first mesa structure, the second mesa structure, the first mesa structure, the second table top are respectively provided between source groove and gate groove
Structure is made of the areas silicon carbide Pbase 7, the contact zones silicon carbide P+ 8 and silicon carbide N+source region 9, wherein silicon carbide P+ contacts
Area 8 and silicon carbide N+source region 9 are located at the top of areas silicon carbide Pbase 7, and the contact zones silicon carbide P+ 8 and source trench contact, silicon carbide N+
Source region 9 is contacted with gate groove, and the areas silicon carbide Pbase 7 are then contacted with source groove, gate groove simultaneously, and its depth is shallower than source ditch
Slot and gate groove；Source trench metal is in direct contact to be formed with rectification spy in source trenched side-wall bottom with silicon carbide N-epitaxial layer 3
The Schottky contacts of property；Device surface is covered by one layer of source metal 6, and source metal 6 passes through boron-phosphorosilicate glass with grid 12
BPSG13 is mutually isolated.
Wherein, 1 thickness of metal-drain be 0.5 μm~2 μm, width be 2~2.5 μm, 12 metal thickness of grid be 0.5 μm~
2 μm, width is 0.2~0.4 μm, and source metal thickness is 4 μm~6 μm, and width is 2~2.5 μm；2 thickness of silicon carbide N+substrate
It is 1~3 μm, a concentration of 1e18~1e19cm-3；3 thickness of silicon carbide N-extension is 6~9 μm, a concentration of 1e15~1e16cm-3；
4 thickness of silicon carbide P-doped zone is 1~2 μm, and width is 0.5~2 μm, a concentration of 1e17~6e17cm-3；Silicon carbide P+ doping
5 thickness of area is 1~2 μm, and width is 0.2~1 μm, a concentration of 1e18~6e18cm-3；7 thickness of the areas silicon carbide Pbase be 0.3~
0.8 μm, width is 0.5~1.1 μm, a concentration of 6e16~4e17cm-3；8 thickness of the contact zones silicon carbide P+ is 0.2~0.4 μm,
Width is 0.2~0.4 μm, a concentration of 8e17~1e19cm-3；9 thickness of silicon carbide N+source region is 0.2~0.4 μm, width 0.2
~0.3 μm, a concentration of 2e18~1e19cm-3；10 thickness of gate dielectric layer is 50nm；11 thickness of polysilicon gate is 0.4~1 μm, wide
Degree is 0.4~1 μm.14 thickness of Schottky contact metal is 1~2 μm, and width is 0.4~1.5 μm.A kind of carbon provided by the invention
SiClx MOSFET also optimizes device by internal integrated schottky barrier diode while optimised devices basic performance
Third quadrant working performance reduces power system cost.
Embodiment 2：
The present embodiment structure is roughly the same with embodiment 1, the difference is that：Used Schottky contact metal 14 with
Polysilicon 15 replaces, as shown in Figure 3.Equally formed with rectifying contact in source channel bottom side wall and silicon carbide N-extension 3
Si/SiC heterojunction structures.Heterojunction structure forward conduction voltage drop Von is about 1.1V, is worked for device third quadrant same
With larger castering action.Simultaneously as the hetero-junctions belongs to how sub- device so that diode has good Reverse recovery
Performance.
Embodiment 3：
The present embodiment difference from Example 1 is that the gate structure bottom section has split-gate structures,
As shown in Figure 4.The split-gate structures include split-gate polysilicons 16 and encirclement split-gate polysilicons 16
Gate dielectric layer 10 form.The split-gate polysilicons 16 are drawn in back by metal lead wire, can be grounded, can also be with
Source shorted.Which significantly reduces device gate-drain charge, to reduce miller capacitance, for carrying for devices switch speed
Rising has prodigious optimization function.
Embodiment 4：
The present embodiment difference from Example 1 is：The silicon carbide P-doped zone 4 has the lateral dimension of bigger,
As shown in Figure 5.4 lateral dimension of silicon carbide P-doped zone of bigger makes silicon carbide P-doped zone 4 for device surface structure,
Including gate structure and Schottky contact structure, Si/SiC heterojunction structures, there is more preferably protective effect.
Embodiment 5：
The present embodiment difference from Example 1 is：The silicon carbide P-doped zone 4 and silicon carbide P+ doped regions 5 with
Dielectric layer 17 replaces, as shown in Figure 6.The introducing of dielectric layer 17, for device surface structure, including gate structure and Schottky
Contact structures, Si/SiC heterojunction structures have good protective effect.
Embodiment 6：
The present embodiment difference from Example 1 is that it is in discontinuously arranged groove that source beneath trenches have in Z-direction
Distribution, the groove are filled simultaneously when depositing Schottky contact metal 14 or polysilicon 15.Channel bottom is silicon carbide N-extension
Layer 3.The gash depth is consistent with silicon carbide P-doped zone 4 or gate dielectric layer 10 simultaneously, as shown in Figure 8.1 source groove of embodiment
Rectangular structure is as shown in Figure 7.Relative to embodiment 1, the on state current that the present embodiment optimizes when device third quadrant works is close
Degree.
Embodiment 7：
The present embodiment structure is roughly the same with embodiment 6, the difference is that, gash depth is mixed less than silicon carbide p-type
4 depth of miscellaneous area, as shown in Figure 9.For embodiment 6, the present embodiment has the electric leakage under lower blocking state so that embedding
The diode entered has more preferably reliability.
Embodiment 8：
The present embodiment structure is roughly the same with embodiment 1, the difference is that, the Schottky contact metal 14 or polycrystalline
The bottom of silicon 15 extends to the middle part of silicon carbide P-doped zone 4 and silicon carbide P+ doped regions 5, is connect with silicon carbide N-epitaxial layer 3
It touches.As shown in Figure 10.The improvement increases unipolar device rectification area, to optimize device third quadrant working performance.
Embodiment 9：
The present embodiment is equally by taking the silicon carbide MOSFET device production method of 1200V as an example, to above-mentioned 1~8 embodiment
Specific implementation illustrates, and according to common sense in the field, the device of different performance parameter can be prepared according to actual demand.
1st step：The silicon carbide plate of suitable resistivity and thickness is chosen, that is, is used as subsequent silicon carbide N+substrate 2, silicon carbide
The areas N- 3, as shown in figure 11.Wherein, 2 thickness of silicon carbide N+substrate is 1~3 μm, a concentration of 1e18~1e19cm-3；Silicon carbide N-
3 thickness of extension is 6~9 μm, a concentration of 1e15~1e16cm-3；
2nd step：By energetic ion injection technology, Implantation Energy is about 1500~2000keV, carries out Al ion implantation,
Form the areas silicon carbide Pbase 7.The step can also by extensional mode formed thickness be 0.3~0.8 μm, width be 0.5~
1.1 μm, a concentration of areas 6e16~4e17cm-3 silicon carbide Pbase 7.Form device such as Figure 12 institutes behind the areas silicon carbide Pbase 7
Show；
3rd step：By processes such as photoetching, ion implantings, using PSD mask plates, at a temperature of 450 DEG C~550 DEG C into
Row Al ion implantation, Implantation Energy are about 1300~1700keV, and it is 0.2~0.4 μm to form thickness, and width is 0.2~0.4 μm,
The contact zones silicon carbide P+ 8 of a concentration of 8e17~1e19cm-3, as shown in figure 13；
4th step：By processes such as photoetching, ion implantings, phosphonium ion injection is carried out using NSD mask plates, Implantation Energy is about
For 1300~1700keV.Thickness is 0.2~0.4 μm, and width is 0.2~0.3 μm, the formation of a concentration of 2e18~1e19cm-3
Silicon carbide N+source region 9, as shown in figure 14；
5th step：By trench etch process, it is 1~2 μm to etch thickness using Trench mask plates, width is 0.4~
1.5 μm of source groove, as shown in figure 15；
6th step：Al ion implantation is carried out at a temperature of 480 DEG C~580 DEG C by processes such as photoetching, ion implantings, is noted
It is about 1400~1700keV to enter energy, forms silicon carbide P-doped zone 4, as shown in figure 16；The step can also be logical in the 5th step
Over etching forms deeper source groove, and then again through extension, etching technics, it is 1~2 μm to form thickness, and width is 0.5~2 μm,
The silicon carbide p-type doping 4 of a concentration of 1e17~6e17cm-3；
7th step：Al ion implantation is carried out at a temperature of 430 DEG C~580 DEG C by processes such as photoetching, ion implantings, is noted
It is about 1200~1700keV to enter energy, and it is 1~2 μm to form thickness, and width is 0.2~1 μm, a concentration of 1e18~6e18cm-3
Silicon carbide P+ doped regions 5, as shown in figure 17；
8th step：By deposit and etching technics, in source, channel bottom deposits one layer of metal, and it is 1~2 μm to form thickness, wide
Degree is 0.4~1.5 μm of Schottky contact metal 14, and extra metal is removed by etching.As shown in figure 18；
9th step：By trench etch process, it is 0.4~1 μm to etch thickness using Trench mask plates, width 0.4
~1 μm of gate groove, as shown in figure 19；
10th step：At a temperature of about 1000 DEG C~1400 DEG C, the grid that thickness is 50nm are formed by dry-oxygen oxidation technique
Dielectric layer 10, as shown in figure 20；
11st step：By deposit and etching technics, one layer of polysilicon is deposited in gate groove, it is 0.4~1 μ to form thickness
M, the polysilicon gate 11 that width is 0.4~1 μm remove extra polysilicon by etching.As shown in figure 21；
12nd step：It is 0.5 μm~2 μm to form thickness by deposit, photoetching and etching technics, and width is 0.2~0.4 μm
Grid 12, as shown in figure 22.
13rd step：Boron-phosphorosilicate glass BPSG13 is formed by deposit, photoetching and etching technics, as shown in figure 23.
14th step：It is 4 μm~6 μm to form thickness by deposit, photoetching and etching technics respectively, and width is 2~2.5 μm
Source electrode 6, thickness be 0.5 μm~2 μm, width is 2~2.5 μm of drain electrode 1.So far, element manufacturing is completed, as shown in figure 24.
Further, the polysilicon 11 deposited in the 11st step, either N-type polycrystalline silicon, can also be p-type polycrystalline
Silicon；
Further, in the 8th step, the source trench schottky contacting metal 14 deposited also can be replaced 15 material of polysilicon
Material；The polysilicon is same either N-type polycrystalline silicon, can also be p-type polysilicon；
Further, after completing the 9th step and forming deeper gate groove, channel bottom and side wall are aoxidized.And in
Channel bottom deposits split-gate polysilicons 16, through dielectric layer deposited 5, etch media layer 5, depositing polysilicon grid 11, is formed
Split-gate structures, as shown in Figure 4；
Further, after the 6th step forms silicon carbide P-doped zone 4, can make to form thickness to be 1 by high-temperature diffusion process
~2 μm, the silicon carbide P-doped zone 4 that width is 0.6~2.3 μm；
Further, when the 5th step forms source groove, etching dynamics can be increased, to form deeper etching groove.And
It is following technique that 6th, the 7th step, which is substituted,：By deposit, etching technics, it be thickness is 1 that in source, channel bottom, which deposits and to form thickness,
~2 μm of oxide layer.Etched technique forms the dielectric layer 10 that apparent height is less than the areas silicon carbide Pbase 7.
Further, after the 5th step forms source groove, it can be further added by primary etching, formed not in former source channel bottom
Continuous groove.Secondarily etched gash depth is equal to 4 depth of silicon carbide P-doped zone formed in the later stage, i.e. thickness is 1~2 μ
m；
Further, after the 5th step forms source groove, it can be further added by primary etching, formed not in former source channel bottom
Continuous groove.Secondarily etched gash depth is less than 4 depth of silicon carbide P-doped zone formed in the later stage, i.e. thickness is most slight
In 1um, maximum is less than 2um；
Further, after the 5th step forms source groove, it can be further added by primary etching, formed and connected in former source channel bottom
Continuous groove, secondarily etched gash depth are equal to 4 depth of silicon carbide P-doped zone formed in the later stage；
Further, gate groove can also be initially formed, and after completing gate structure, re-form source groove.
Embodiment 10：
The structure cell of a kind of silicon carbide MOSFET device, basic structure is as shown in figure 25.Including from bottom to top successively
The metal-drain 1 of setting, silicon carbide N+Substrate 2 and silicon carbide N-Epitaxial layer 3；The silicon carbide N-3 upper left side of epitaxial layer has the
One gate structure, the silicon carbide N-3 upper right side of epitaxial layer has second grid structure, first, second gate structure equal
Including grid 12, polysilicon gate 11 and gate dielectric layer 10, wherein polysilicon gate 11 is surrounded by gate dielectric layer 10, top by
Grid 12 is drawn, the silicon carbide N-3 top of epitaxial layer has active groove, and the source groove is deposited by Schottky contact metal 14
Filling, Schottky contact metal 14 are in direct contact with silicon carbide N-epitaxial layer 3, form Schottky contacts, source groove and grid knot
The first mesa structure, the second mesa structure are respectively provided between structure, the first mesa structure, the second mesa structure are by silicon carbide
The areas Pbase 7, the contact zones silicon carbide P+ 8 and silicon carbide N+source region 9 are constituted, wherein and the contact zones silicon carbide P+ 8 and silicon carbide N+
Source region 9 is located at 7 top of the areas silicon carbide Pbase, the contact zones silicon carbide P+ 8 and source trench contact, silicon carbide N+source region 9 and grid knot
Structure contacts, and the areas silicon carbide Pbase 7 are then contacted with source groove, gate structure simultaneously, and its depth is shallower than source groove and grid knot
Structure；14 lower section both sides of the Schottky contact metal, 7 lower section of the areas partially carbonized silicon Pbase have P-doped zone, P-doped zone
Middle depth is deeper silicon carbide P-doped zone 4, and depth is more shallow, width is narrower for silicon carbide P+ doped regions 5；Silicon carbide P+
Doped region 5 forms Ohmic contact with Schottky contact metal 14, and the device surface is covered by one layer of source metal 6, source electrode gold
Belong to 6 with grid 12 to be separated by with boron-phosphorosilicate glass BPSG13.Wherein, 1 thickness of drain metal is 0.5 μm~1.6 μm, and width is 4~6
μm, 12 thickness of gate metal is 0.5 μm~1.6 μm, and width is 0.2~0.5 μm, and source metal thickness is 4 μm~6 μm, width
It is 4~6 μm；2 thickness of silicon carbide N+substrate is 1~3 μm, a concentration of 1e18~1e19cm-3；3 thickness of silicon carbide N-extension is 6
~10 μm, a concentration of 1e15~1e16cm-3；4 thickness of silicon carbide P-doped zone is 1~2 μm, and width is 0.5~3 μm, concentration
For 1e17~6e17cm-3；5 thickness of silicon carbide P+ doped regions is 1~2 μm, and width is 0.2~1.5 μm, a concentration of 1e18~
6e18cm-3；7 thickness of the areas silicon carbide Pbase is 0.3~0.8 μm, and width is 0.5~1.1 μm, a concentration of 6e16~5e17cm-
3；8 thickness of the contact zones silicon carbide P+ is 0.2~0.5 μm, and width is 0.2~0.5 μm, a concentration of 8e17~1e19cm-3；Carbonization
9 thickness of silicon N+ source regions is 0.2~0.5 μm, and width is 0.2~0.5 μm, a concentration of 2e18~1e19cm-3；Gate dielectric layer 10 is thick
Degree is 20~70nm；11 thickness of polysilicon gate is 0.4~1 μm, and width is 0.4~1 μm.14 thickness of Schottky contact metal is 1
~2 μm, width is 0.4~3 μm.A kind of silicon carbide MOSFET provided by the invention passes through internal two pole of integrated schottky potential barrier
Pipe, while optimised devices basic performance, optimizes device third quadrant working performance, reduces power conversion system application
Cost.
Embodiment 11：
The present embodiment makes modification to a certain extent for embodiment 10, and structure is said by taking embodiment 10 as an example
It is bright.Difference from Example 9 is that used Schottky contact metal 14 is replaced with polysilicon 15, as shown in figure 26.Together
Sample forms the Si/SiC heterojunction structures with rectifying contact in source channel bottom and silicon carbide N-extension 3.The heterojunction structure
Forward conduction voltage drop Von is about 1.1V, equally has larger castering action for the work of device third quadrant.Simultaneously as
The hetero-junctions belongs to how sub- device so that diode has good Reverse recovery performance.
Embodiment 12：
The present embodiment structure is illustrated by taking embodiment 10 as an example, as shown in figure 27.Difference from Example 10 is,
The gate structure bottom section has split-gate structures.The split-gate structures include split-gate polysilicons
The gate dielectric layer 10 of 16 and encirclement split-gate polysilicons 16 forms.The split-gate polysilicons 16 are in back by gold
Belong to lead to draw, can be grounded, it can also be with source shorted.Which significantly reduces device gate-drain charge, to reduce
Miller capacitance has prodigious optimization function for the promotion of devices switch speed；
Embodiment 13：
The present embodiment difference from Example 10 is that the structure has 14 depth of Schottky contact metal of bigger
And width so that it not only forms rectifying contact in metal bottom and silicon carbide N-epitaxial layer 3, also in source channel bottom side wall with
Silicon carbide N-epitaxial layer 3 contacts, that is, forms rectifying contact, as shown in figure 28；
Embodiment 14：
The present embodiment difference from Example 10 is, the silicon carbide P-doped zone 4 and silicon carbide P+ doped regions 5
It is replaced with dielectric layer 17, as shown in figure 29.The introducing of dielectric layer 10, for device surface structure, including gate structure and Xiao
Special base contact structures, Si/SiC heterojunction structures have good protective effect.
Embodiment 15：
The present embodiment difference from Example 10 is, 14 bottom of the Schottky contact metal and silicon carbide N-extension
There is 15th area of polysilicon below the subregion of 3 contacts, as shown in figure 30.The region forms Si/SiC with silicon carbide N-extension 3
Heterojunction.For the increase situation in rectifying contact face, which increases 50% or so rectifying contact face, to increase
Conducting junction when big diode applications.Since Si/SiC hetero-junctions electric leakage performance is much better than Schottky contacts, while P-type silicon
There is good shielding action for schottky junction face so that the electric leakage of Schottky junction further decreases.
Embodiment 16：
The present embodiment difference from Example 10 is that source beneath trenches have to be distributed in discontinuously arranged groove,
The groove is filled simultaneously when depositing Schottky contact metal 14 or polysilicon 15.The gash depth is mixed with silicon carbide p-type simultaneously
Miscellaneous area 4 or dielectric layer 10 are consistent, as shown in figure 32.10 source beneath trenches structure of embodiment is as shown in figure 31.Relative to embodiment
10, the present embodiment optimizes the on state current density when work of device third quadrant.
Embodiment 17：
The present embodiment and embodiment 16 the difference is that, secondary source etching groove depth is shallower than embodiment 16, such as Figure 33
It is shown.For embodiment 16, the present embodiment has the electric leakage under lower blocking state so that embedded diode has
More preferably reliability.
Embodiment 18：
The present embodiment is equally by taking the silicon carbide MOSFET device production method of 1200V as an example, to above-mentioned 10~17 embodiment
Specific implementation illustrate, according to common sense in the field, the device of different performance parameter can be prepared according to actual demand.
1st step：The silicon carbide plate of suitable resistivity and thickness is chosen, that is, is used as subsequent silicon carbide N+substrate 2, silicon carbide
The areas N- 3, as shown in figure 34.Wherein, 2 thickness of silicon carbide N+substrate is 1~3 μm, a concentration of 1e18~1e19cm-3；Silicon carbide N-
3 thickness of extension is 6~10 μm, a concentration of 1e15~1e16cm-3；
2nd step：By energetic ion injection technology, Implantation Energy is about 1500~2000keV, carries out Al ion implantation,
Form the areas silicon carbide Pbase 7.The step can also by extensional mode formed thickness be 0.3~0.8 μm, width be 0.5~
1.1 μm, a concentration of areas 6e16~5e17cm-3 silicon carbide Pbase 7.Form device such as Figure 35 institutes behind the areas silicon carbide Pbase 7
Show；
3rd step：By processes such as photoetching, ion implantings, using PSD mask plates, at a temperature of 450 DEG C~550 DEG C into
Row Al ion implantation, Implantation Energy are about 1300~1700keV, and it is 0.2~0.5 μm to form thickness, and width is 0.2~0.5 μm,
The contact zones silicon carbide P+ 8 of a concentration of 8e17~1e19cm-3, as shown in figure 36；
4th step：By processes such as photoetching, ion implantings, phosphonium ion injection is carried out using NSD mask plates, Implantation Energy is about
For 1300~1700keV.Thickness is 0.2~0.5 μm, and width is 0.2~0.5 μm, a concentration of 2e18~1e19cm-3Formation carbon
SiClx N+ source regions 9, as shown in figure 37；
5th step：By trench etch process, it is 1~2 μm to etch thickness using Trench mask plates, width is 0.4~
3 μm of source groove, as shown in figure 38；
6th step：By processes such as photoetching, ion implantings at a temperature of 480 DEG C~580 DEG C, carry out at an angle
Al ion implantation, Implantation Energy are about 1400~1700keV, and it is 1~2 μm to form thickness, and width is 0.5~3 μm, a concentration of
The silicon carbide p-type doping 4 of 1e17~6e17cm-3, as shown in figure 39；
7th step：Al ion implantation is carried out at a temperature of 430 DEG C~580 DEG C by processes such as photoetching, ion implantings, is noted
It is about 1200~1700keV to enter energy, and it is 1~2 μm to form thickness, and width is 0.2~1.5 μm, a concentration of 1e18~6e18cm-
3 silicon carbide P+ doped regions 5, as shown in figure 40；
8th step：By deposit and etching technics, in source, channel bottom deposits one layer of metal, and it is 1~2 μm to form thickness, wide
Degree is 0.4~3 μm of Schottky contact metal 14, and extra metal is removed by etching.As shown in figure 41；
9th step：By trench etch process, it is 0.4~1 μm to etch thickness using Trench mask plates, width 0.4
~1 μm of gate groove, as shown in figure 42；
10th step：At a temperature of about 1000 DEG C~1400 DEG C, it is 20~70nm to form thickness by dry-oxygen oxidation technique
Gate dielectric layer 10, as shown in figure 43；
11st step：By deposit and etching technics, one layer of polysilicon is deposited in gate groove, it is 0.4~1 μ to form thickness
M, the polysilicon gate 11 that width is 0.4~1 μm remove extra polysilicon by etching.As shown in figure 44；
12nd step：It is 0.5 μm~1.6 μm to form thickness by deposit, photoetching and etching technics, and width is 0.2~0.5
μm grid 12, as shown in figure 45.
13rd step：Boron-phosphorosilicate glass BPSG13 is formed by deposit, photoetching and etching technics, as shown in figure 46.
14th step：It is 4 μm~6 μm to form thickness by deposit, photoetching and etching technics respectively, and width is 4~6 μm
Source electrode 6, thickness are 0.5 μm~1.6 μm, the drain electrode 1 that width is 4~6 μm.So far, element manufacturing is completed, as shown in figure 47.
Further, the polysilicon 11 deposited in the 11st step, either N-type polycrystalline silicon, can also be p-type polycrystalline
Silicon；
It is further possible to first do gate structure, then complete source groove；
Further, in the 8th step, the source trench schottky contacting metal 14 deposited also can be replaced 15 material of polysilicon
Material；The polysilicon is same either N-type polycrystalline silicon, can also be p-type polysilicon；
Further, after completing the 9th step and forming deeper gate groove, channel bottom and side wall are aoxidized.And in
Channel bottom deposits split-gate polysilicons 16, through depositing gate dielectric layer 10, etching gate dielectric layer 10, depositing polysilicon grid
11, split-gate structures are formed, as shown in figure 27；
Further, in the 5th step source etching groove, etching depth and width can be increased, meanwhile, in the 6th, the 7th step
It when Al ion implantation, injects in vertical manner so that Schottky contacts are not only realized in source channel bottom, while also in Yuan Gou
Slot two side is formed.
Further, when the 5th step forms source groove, etching dynamics can be increased, to form deeper etching groove.And
It is following technique that 6th, the 7th step, which is substituted,：By deposit, etching technics, it be thickness is 1 that in source, channel bottom, which deposits and to form thickness,
~2 μm of oxide layer.Etched technique forms the dielectric layer 10 that apparent height is less than the areas silicon carbide Pbase 7.
Further, secondarily etched in the progress of source channel bottom after the 5th step forms source groove, and before the 6th step,
Polycrystalline silicon deposit filling is carried out to the secondary groove, forms multi-crystal silicon area 15.15 thickness of multi-crystal silicon area is 0.5~0.9um, width
For 0.3~0.7um.
Further, after the 5th step forms source groove, it can be further added by primary etching, formed not in former source channel bottom
Continuous groove.Secondarily etched gash depth is equal to 4 depth of silicon carbide P-doped zone formed in the later stage, i.e. thickness is 1~2 μ
m；
Further, in the 5th step trench etch process, secondarily etched, etching depth etc. can be carried out to device surface
In 4 depth of later stage silicon carbide P-doped zone, and when the 8th step deposits Schottky contact metal 14 or polysilicon 15, also simultaneously
This secondarily etched groove is deposited, to form rectifying contact in the horizontal direction, similar effect is as shown in figure 12；
Further, after the 5th step forms source groove, it can be further added by primary etching, formed not in former source channel bottom
Continuous groove.Secondarily etched gash depth is less than 4 depth of silicon carbide P-doped zone formed in the later stage, i.e. thickness is most slight
In 1um, maximum is less than 2um；
While need to declare is：This field engineers and technicians are according to this field basic knowledge it is recognised that the present invention
In a kind of silicon carbide power MOSFET element structure, p-type polysilicon used can also use N-type polycrystalline silicon to realize,
Also it can be realized by p type single crystal silicon, can also be realized certainly by n type single crystal silicon；Dielectric material used is in addition to may be used two
Silica (SiO2) realize, it also can be by using silicon nitride (Si3N4), hafnium oxide (HfO2), alundum (Al2O3) (Al2O3) contour
K dielectric materials are realized；The carbofrax material can also use gallium nitride, the wide-band gap materials such as diamond to replace.Meanwhile manufacturing work
The specific implementation mode of skill can also be adjusted according to actual needs.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology can all carry out modifications and changes to above-described embodiment without violating the spirit and scope of the present invention.Cause
This, all those of ordinary skill in the art are completed without departing from the spirit and technical ideas disclosed in the present invention
All equivalent modifications or change, should by the present invention claim be covered.
Claims (10)
1. a kind of silicon carbide MOSFET device, it is characterised in that：Including set gradually from bottom to top metal-drain (1), carbonization
Silicon N+Substrate (2) and silicon carbide N-Epitaxial layer (3)；The silicon carbide N-Epitaxial layer (3) upper left side have the first source groove, first
Source beneath trenches have silicon carbide P+ doped regions (5) and silicon carbide P-doped zone (4) from top to bottom；The silicon carbide N-Outside
Prolonging layer (3) upper right side, there is the second source groove, the second source beneath trenches to have silicon carbide P+ doped regions (5) and carbon from top to bottom
SiClx P-doped zone (4)；First, second source groove, which is filled, forms Schottky contact metal (14)；Silicon carbide N-the extension
There is gate groove, depth to be shallower than two source grooves, gate groove inside and surface have gate structure, the grid above layer (3)
Pole structure includes from bottom to top gate dielectric layer (10), polysilicon gate (11) and grid (12), and gate dielectric layer (10) is polysilicon
Grid (11) and silicon carbide body are separated from polysilicon gate (11) top passes through grid (12) and draws；Polysilicon gate (11) is in gate groove
Inside, grid (12) is on gate groove surface；The first mesa structure, the second table top knot are respectively provided between source groove and gate groove
Structure, the first mesa structure, the second mesa structure are by the areas silicon carbide Pbase (7), the contact zones silicon carbide P+ (8) and silicon carbide N
+ source region (9) is constituted, wherein and the contact zones silicon carbide P+ (8) and silicon carbide N+source region (9) are located above the areas silicon carbide Pbase (7),
The contact zones silicon carbide P+ (8) are contacted with source trench contact, silicon carbide N+source region (9) with gate groove, and the areas silicon carbide Pbase (7)
It is then contacted simultaneously with source groove, gate groove, and its depth is shallower than source groove and gate groove；Source trench metal and silicon carbide N-extension
Layer (3) is in direct contact to form the Schottky contacts with rectification characteristic in source trenched side-wall bottom；Device surface is by one layer of source electrode
Metal (6) covers, and source metal (6) is mutually isolated by boron-phosphorosilicate glass BPSG (13) with grid (12).
2. a kind of silicon carbide MOSFET device, it is characterised in that：Including set gradually from bottom to top metal-drain (1), carbonization
Silicon N+Substrate (2) and silicon carbide N-Epitaxial layer (3)；The silicon carbide N-Epitaxial layer (3) upper left side has first grid structure, institute
State silicon carbide N-It includes grid that epitaxial layer (3) upper right side, which has second grid structure, first, second gate structure,
(12), polysilicon gate (11) and gate dielectric layer (10), wherein polysilicon gate (11) is surrounded by gate dielectric layer (10), top
It is drawn by grid (12), the silicon carbide N-Has active groove above epitaxial layer (3), the source groove is by Schottky contact metal
(14) deposit filling, Schottky contact metal (14) are in direct contact with silicon carbide N-epitaxial layer (3), form Schottky contacts, source
The first mesa structure, the second mesa structure, the first mesa structure, the second mesa structure are respectively provided between groove and gate structure
It is made of the areas silicon carbide Pbase (7), the contact zones silicon carbide P+ (8) and silicon carbide N+source region (9), wherein silicon carbide P+ connects
It touches area (8) and silicon carbide N+source region (9) is located above the areas silicon carbide Pbase (7), the contact zones silicon carbide P+ (8) connect with source groove
Tactile, silicon carbide N+source region (9) is contacted with gate structure, and the areas silicon carbide Pbase (7) then connect with source groove, gate structure simultaneously
It touches, and its depth is shallower than source groove and gate structure；Both sides, partially carbonized silicon below the Schottky contact metal (14)
There is P-doped zone, depth is deeper silicon carbide P-doped zone (4) in P-doped zone, and depth is more below the areas Pbase (7)
It is shallow, width is narrower for silicon carbide P+ doped regions (5)；Silicon carbide P+ doped regions (5) form Europe with Schottky contact metal (14)
Nurse contacts, and the device surface is covered by one layer of source metal (6), and source metal (6) is with grid (12) with boron-phosphorosilicate glass
BPSG (13) is separated by.
3. a kind of silicon carbide MOSFET device according to claim 1 or claim 2, it is characterised in that：Silicon carbide material
Material is replaced with Si, Ge, GaAs, GaN, diamond, SiGe, gallium oxide semi-conducting material；Schottky contact metal (14) area
Domain is polysilicon (15).
4. a kind of silicon carbide MOSFET device according to claims 1 to 3 any one, it is characterised in that：The grid
There is split-gate polysilicons (16) below structure.
5. a kind of silicon carbide MOSFET device according to any one of claims 1 to 4, it is characterised in that：The Xiao Te
The bottom of base contacting metal (14) or polysilicon (15) extends to silicon carbide P-doped zone (4) and silicon carbide P+ doped regions (5)
Middle part is contacted with silicon carbide N-epitaxial layer (3).
6. a kind of silicon carbide MOSFET device according to claim 2, it is characterised in that：Schottky contact metal (14) with
The silicon carbide N of the areas silicon carbide Pbase (7) lower part-Epitaxial layer (3) is in direct contact so that it is not only in metal bottom and silicon carbide
N- epitaxial layers (3) form rectifying contact, are also contacted with silicon carbide N-epitaxial layer (3) in source channel bottom side wall, form rectification and connect
It touches.
7. a kind of silicon carbide MOSFET device according to claim 1 to 6 any one, it is characterised in that：Under the groove of source
Side in Z-direction there is discontinuous groove, gash depth to be less than or equal to silicon carbide P-doped zone (4) depth, wherein institute
It states trench interiors to deposit with Schottky contact metal (14) or polysilicon (15), channel bottom is silicon carbide N-epitaxial layer 3.
8. a kind of silicon carbide MOSFET device according to claim 2, it is characterised in that：The Schottky contact metal
(14) there is polysilicon (15) area, the region and silicon carbide below the subregion that bottom is contacted with silicon carbide N-epitaxial layer (3)
N- epitaxial layers (3) form Si/SiC heterojunctions.
9. a kind of manufacturing method of silicon carbide MOSFET device according to claim 1, which is characterized in that including following step
Suddenly：
1st step：Silicon carbide plate is chosen, as subsequent silicon carbide N+substrate (2), silicon carbide N-epi region (3)；
2nd step：By energetic ion injection technology, Al ion implantation is carried out, is formed the areas Tan Gui Pbase (7), or pass through extension side
Formula forms the areas silicon carbide Pbase (7), then forms the device after the areas silicon carbide Pbase (7)；
3rd step：By photoetching, ion injecting process, Al ion implantation is carried out using PSD mask plates, forms silicon carbide P+ contacts
Area (8)；
4th step：By processes such as photoetching, ion implantings, phosphonium ion injection is carried out using NSD mask plates, forms silicon carbide N+source
Area (9)；
5th step：By trench etch process, the source groove of specified size is etched using Trench mask plates；
6th step：Al ion implantation is carried out by photoetching, ion injecting process, forms silicon carbide P-doped zone (4)；The step or
Person forms deeper source groove in the 5th step by etching, then forms silicon carbide P-doped zone through extension, etching technics again
(4)；
7th step：Al ion implantation is carried out by photoetching, ion injecting process, forms silicon carbide P+ doped regions (5)；
8th step：By deposit and etching technics, in source, channel bottom deposits one layer of metal, forms Schottky contact metal (14),
Extra metal is removed by etching；
9th step：By trench etch process, the gate groove of specified size is etched using Trench mask plates；
10th step：Gate dielectric layer (10) is formed by dry-oxygen oxidation technique；
11st step：By deposit and etching technics, one layer of polysilicon is deposited in gate groove, is formed polysilicon gate (11), is passed through
Etching removes extra polysilicon；
12nd step：Grid (12) is formed by deposit, photoetching and etching technics；
13rd step：Boron-phosphorosilicate glass BPSG (13) is formed by deposit, photoetching and etching technics；
14th step：Source metal (6), metal-drain (1), so far, device are formed by deposit, photoetching and etching technics respectively
It completes.
10. a kind of manufacturing method of silicon carbide MOSFET device according to claim 2, which is characterized in that including following
Step：
1st step：Silicon carbide plate is chosen, that is, is used as subsequent silicon carbide N+substrate (2), silicon carbide N-epitaxial layer (3)；
2nd step：By energetic ion injection technology, Al ion implantation is carried out, is formed the areas silicon carbide Pbase (7), the step or logical
It crosses extensional mode and forms the areas silicon carbide Pbase (7)；
3rd step：By photoetching, ion injecting process, Al ion implantation is carried out using PSD mask plates, forms silicon carbide P+ contacts
Area (8)；
4th step：By photoetching, ion injecting process, phosphonium ion injection is carried out using NSD mask plates, forms silicon carbide N+source region
(9)；
5th step：By trench etch process, the source groove of specified size is etched using Trench mask plates；
6th step：By processes such as photoetching, ion implantings, Al ion implantation is carried out at an angle, forms the doping of silicon carbide p-type
Area (4)；
7th step：By processes such as photoetching, ion implantings, Al ion implantation is carried out, forms silicon carbide P+ doped regions (5)；
8th step：By deposit and etching technics, in source, channel bottom deposits one layer of metal, forms Schottky contact metal (14),
Extra metal is removed by etching；
9th step：By trench etch process, the gate groove of specified size is etched using Trench mask plates；
10th step：Gate dielectric layer (10) is formed by dry-oxygen oxidation technique；
11st step：By deposit and etching technics, one layer of polysilicon is deposited in gate groove, is formed polysilicon gate (11), is passed through
Etching removes extra polysilicon；
12nd step：Grid (12) is formed by deposit, photoetching and etching technics；
13rd step：Boron-phosphorosilicate glass BPSG (13) is formed by deposit, photoetching and etching technics；
14th step：Source metal (6), metal-drain (1) are formed by deposit, photoetching and etching technics respectively；So far, device
It completes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810990494.0A CN108807504B (en) | 2018-08-28 | 2018-08-28 | Silicon carbide MOSFET device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810990494.0A CN108807504B (en) | 2018-08-28 | 2018-08-28 | Silicon carbide MOSFET device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108807504A true CN108807504A (en) | 2018-11-13 |
| CN108807504B CN108807504B (en) | 2022-01-25 |
Family
ID=64081093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810990494.0A Active CN108807504B (en) | 2018-08-28 | 2018-08-28 | Silicon carbide MOSFET device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108807504B (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110473914A (en) * | 2019-09-18 | 2019-11-19 | 深圳爱仕特科技有限公司 | A kind of preparation method of SiC-MOS device |
| CN111029398A (en) * | 2019-11-24 | 2020-04-17 | 中电国基南方集团有限公司 | Groove type MOSFET power device and preparation method thereof |
| CN111081778A (en) * | 2019-11-28 | 2020-04-28 | 深圳第三代半导体研究院 | Silicon carbide groove type MOSFET device and manufacturing method thereof |
| CN111276545A (en) * | 2020-02-12 | 2020-06-12 | 重庆伟特森电子科技有限公司 | Novel groove silicon carbide transistor device and manufacturing method thereof |
| CN112086507A (en) * | 2020-10-22 | 2020-12-15 | 电子科技大学 | SiC MOSFET device cell and manufacturing method thereof |
| CN112397592A (en) * | 2020-11-18 | 2021-02-23 | 江西万年芯微电子有限公司 | Silicon carbide MOS device |
| CN113540212A (en) * | 2021-07-16 | 2021-10-22 | 威星国际半导体(深圳)有限公司 | Silicon carbide power device and manufacturing method thereof |
| CN113972261A (en) * | 2021-10-11 | 2022-01-25 | 松山湖材料实验室 | Silicon carbide semiconductor device and preparation method |
| CN114171597A (en) * | 2021-10-18 | 2022-03-11 | 浙江芯科半导体有限公司 | SiC MOSFET device with low source contact resistance and preparation method thereof |
| CN115602730A (en) * | 2022-12-15 | 2023-01-13 | 深圳市森国科科技股份有限公司（Cn） | Semiconductor field effect transistor and preparation method thereof, circuit board and equipment |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102683390A (en) * | 2011-03-16 | 2012-09-19 | 飞兆半导体公司 | Inter-poly dielectric in shielded gate mosfet device |
| KR20140138416A (en) * | 2013-05-23 | 2014-12-04 | 매그나칩 반도체 유한회사 | Semiconductor device with embedded schottky diode and manufacture method thereof |
| CN105047721A (en) * | 2015-08-26 | 2015-11-11 | 国网智能电网研究院 | Silicon carbide trench gate power metal-oxide-semiconductor field effect transistors (MOSFETs) device and manufacturing method thereof |
| CN105576032A (en) * | 2015-08-26 | 2016-05-11 | 上海晶亮电子科技有限公司 | SiC MOSFET (Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor) device unit and manufacturing method thereof |
| CN105633168A (en) * | 2015-12-31 | 2016-06-01 | 国网智能电网研究院 | SiC grooved metal oxide semiconductor field effect transistor (MOSFET) with integration of Schottky diode and fabrication method of SiC grooved MOSFET |
| US20170133503A1 (en) * | 2015-02-11 | 2017-05-11 | Monolith Semiconductor Inc. | High voltage semiconductor devices and methods of making the devices |
| CN106876485A (en) * | 2017-03-06 | 2017-06-20 | 北京世纪金光半导体有限公司 | Double trench MOSFET devices of a kind of SiC of integrated schottky diode and preparation method thereof |
| CN107256864A (en) * | 2017-06-09 | 2017-10-17 | 电子科技大学 | A kind of carborundum TrenchMOS devices and preparation method thereof |
| CN107863341A (en) * | 2017-07-13 | 2018-03-30 | 西安华羿微电子股份有限公司 | Compound groove MOS device and its manufacture method |
-
2018
- 2018-08-28 CN CN201810990494.0A patent/CN108807504B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102683390A (en) * | 2011-03-16 | 2012-09-19 | 飞兆半导体公司 | Inter-poly dielectric in shielded gate mosfet device |
| KR20140138416A (en) * | 2013-05-23 | 2014-12-04 | 매그나칩 반도체 유한회사 | Semiconductor device with embedded schottky diode and manufacture method thereof |
| US20170133503A1 (en) * | 2015-02-11 | 2017-05-11 | Monolith Semiconductor Inc. | High voltage semiconductor devices and methods of making the devices |
| CN105047721A (en) * | 2015-08-26 | 2015-11-11 | 国网智能电网研究院 | Silicon carbide trench gate power metal-oxide-semiconductor field effect transistors (MOSFETs) device and manufacturing method thereof |
| CN105576032A (en) * | 2015-08-26 | 2016-05-11 | 上海晶亮电子科技有限公司 | SiC MOSFET (Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor) device unit and manufacturing method thereof |
| CN105633168A (en) * | 2015-12-31 | 2016-06-01 | 国网智能电网研究院 | SiC grooved metal oxide semiconductor field effect transistor (MOSFET) with integration of Schottky diode and fabrication method of SiC grooved MOSFET |
| CN106876485A (en) * | 2017-03-06 | 2017-06-20 | 北京世纪金光半导体有限公司 | Double trench MOSFET devices of a kind of SiC of integrated schottky diode and preparation method thereof |
| CN107256864A (en) * | 2017-06-09 | 2017-10-17 | 电子科技大学 | A kind of carborundum TrenchMOS devices and preparation method thereof |
| CN107863341A (en) * | 2017-07-13 | 2018-03-30 | 西安华羿微电子股份有限公司 | Compound groove MOS device and its manufacture method |
Non-Patent Citations (1)
| Title |
|---|
| 李轩: ""SiC MOSFET开关损耗模型与新结构研究"", 《中国优秀博硕士学位论文全文数据库(博士)基础科学辑》 * |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110473914B (en) * | 2019-09-18 | 2024-03-29 | 深圳爱仕特科技有限公司 | Preparation method of SiC-MOS device |
| CN110473914A (en) * | 2019-09-18 | 2019-11-19 | 深圳爱仕特科技有限公司 | A kind of preparation method of SiC-MOS device |
| CN111029398A (en) * | 2019-11-24 | 2020-04-17 | 中电国基南方集团有限公司 | Groove type MOSFET power device and preparation method thereof |
| CN111081778A (en) * | 2019-11-28 | 2020-04-28 | 深圳第三代半导体研究院 | Silicon carbide groove type MOSFET device and manufacturing method thereof |
| CN111276545A (en) * | 2020-02-12 | 2020-06-12 | 重庆伟特森电子科技有限公司 | Novel groove silicon carbide transistor device and manufacturing method thereof |
| CN112086507A (en) * | 2020-10-22 | 2020-12-15 | 电子科技大学 | SiC MOSFET device cell and manufacturing method thereof |
| CN112397592A (en) * | 2020-11-18 | 2021-02-23 | 江西万年芯微电子有限公司 | Silicon carbide MOS device |
| CN113540212A (en) * | 2021-07-16 | 2021-10-22 | 威星国际半导体(深圳)有限公司 | Silicon carbide power device and manufacturing method thereof |
| CN113540212B (en) * | 2021-07-16 | 2023-07-25 | 威星国际半导体(深圳)有限公司 | Silicon carbide power device and manufacturing method thereof |
| CN113972261A (en) * | 2021-10-11 | 2022-01-25 | 松山湖材料实验室 | Silicon carbide semiconductor device and preparation method |
| CN114171597A (en) * | 2021-10-18 | 2022-03-11 | 浙江芯科半导体有限公司 | SiC MOSFET device with low source contact resistance and preparation method thereof |
| CN114171597B (en) * | 2021-10-18 | 2023-03-21 | 浙江芯科半导体有限公司 | SiC MOSFET device with low source contact resistance and preparation method thereof |
| CN115602730A (en) * | 2022-12-15 | 2023-01-13 | 深圳市森国科科技股份有限公司（Cn） | Semiconductor field effect transistor and preparation method thereof, circuit board and equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108807504B (en) | 2022-01-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108807504A (en) | Silicon carbide MOSFET device and its manufacturing method | |
| CN109192779B (en) | Silicon carbide MOSFET device and manufacturing method thereof | |
| CN107275407B (en) | Silicon carbide VDMOS device and manufacturing method thereof | |
| CN104538446B (en) | A kind of bi-directional MOS type device and its manufacture method | |
| CN108807505B (en) | Silicon carbide MOSFET device and manufacturing method thereof | |
| CN107248533B (en) | Silicon carbide VDMOS device and manufacturing method thereof | |
| CN110148629B (en) | Groove type silicon carbide MOSFET device and preparation method thereof | |
| CN109065621B (en) | Insulated gate bipolar transistor and preparation method thereof | |
| CN104701380B (en) | Dual-direction MOS-type device and manufacturing method thereof | |
| CN107256864A (en) | A kind of carborundum TrenchMOS devices and preparation method thereof | |
| CN110047910A (en) | A kind of heterojunction semiconductor device of high voltage ability | |
| CN109742135B (en) | Silicon carbide MOSFET device and preparation method thereof | |
| CN109119463B (en) | Transverse groove type MOSFET device and preparation method thereof | |
| CN107425068B (en) | Silicon carbide Trench MOS device and manufacturing method thereof | |
| CN105993076A (en) | Bi-directional MOS device and manufacturing method thereof | |
| CN110518058A (en) | A kind of lateral trench type insulated gate bipolar transistor and preparation method thereof | |
| CN210805778U (en) | SiC-MOS device structure | |
| CN109148566B (en) | Silicon carbide MOSFET device and method of manufacturing the same | |
| CN106024876A (en) | Reverse conducting lateral insulated gate bipolar transistor device for eliminating hysteresis phenomenon | |
| CN116110796A (en) | SBD integrated silicon carbide SGT-MOSFET and preparation method thereof | |
| CN107768435A (en) | A kind of two-way IGBT and its manufacture method | |
| CN108155230A (en) | A kind of transverse direction RC-IGBT devices and preparation method thereof | |
| CN109920838B (en) | Groove type silicon carbide MOSFET device and preparation method thereof | |
| CN107256884A (en) | A kind of silicon carbide power diode component and preparation method thereof | |
| CN110473914A (en) | A kind of preparation method of SiC-MOS device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20230518 Address after: 310051 1-1201, No. 6, Lianhui street, Xixing street, Binjiang District, Hangzhou City, Zhejiang Province Patentee after: Hangzhou Xinmai Semiconductor Technology Co.,Ltd. Address before: 611731, No. 2006, West Avenue, Chengdu hi tech Zone (West District, Sichuan) Patentee before: University of Electronic Science and Technology of China |