CN210805778U

CN210805778U - SiC-MOS device structure

Info

Publication number: CN210805778U
Application number: CN201921548037.2U
Authority: CN
Inventors: 姚金才; 陈宇; 朱超群
Original assignee: Shenzhen Hester Technology Co ltd
Current assignee: Shenzhen Hester Technology Co ltd
Priority date: 2019-09-18
Filing date: 2019-09-18
Publication date: 2020-06-19
Anticipated expiration: 2029-09-18

Abstract

The utility model discloses a SiC-MOS device structure, include metal drain electrode, carborundum N + substrate and carborundum N-epitaxial layer that sets gradually from bottom to top, carborundum N-epitaxial layer upper left side and upper right side all have the source electrode slot, source electrode slot below top-down has carborundum P + doped region and carborundum P type doped region, the source electrode slot intussuseption is all filled with schottky contact metal, grid ditch inslot portion and surface have the grid structure, first mesa structure and second mesa structure constitute by carborundum N-epitaxial layer, carborundum P type doped region and carborundum N + source region. The utility model discloses can regulate and control schottky barrier height to form the schottky contact of lower turn-on voltage drop, showing and having reduced the power electronic system volume, reduced the encapsulation cost, improved system application reliability, also have the great promotion to basic performance and permanent application reliability, have lower specific on-resistance, have the characteristics that the electric leakage is low.

Description

SiC-MOS device structure

Technical Field

The utility model relates to the field of semiconductor technology, specifically a SiC-MOS device structure.

Background

Silicon carbide MOSFET devices are the next generation of semiconductor devices fabricated with the wide bandgap semiconductor material silicon carbide. The silicon carbide material has many attractive properties, such as critical breakdown electric field strength 10 times that of the silicon material, high thermal conductivity, large forbidden band width, high electron saturation drift velocity and the like, so that the SiC material becomes a research hotspot of international power semiconductor devices, and the silicon carbide devices are highly expected in high-power application occasions, such as high-speed railways, hybrid electric vehicles, intelligent high-voltage direct-current transmission and the like. Meanwhile, the silicon carbide power device has a remarkable effect of reducing power loss, so that the silicon carbide power device is known as a green energy device driving 'new energy revolution'. However, the on-state current density of silicon carbide MOSFETs is greatly limited by the low MOS channel mobility due to non-idealities in the MOS channel. Thus, silicon carbide UMOSFETs having higher channel densities, and thus greater on-state current densities, have received extensive attention and research. Although the silicon carbide UMOSFET has lower on-state resistance and more compact cell layout, the problem of too high electric field of the bottom gate oxide layer brings reliability problem to the long-term use of the silicon carbide UMOSFET, resulting in poor long-term stability of the device. A conventional silicon carbide UMOSFET structure is shown in fig. 1.

Silicon carbide UMOSFETs generally need to function together with an anti-parallel diode in circuit applications such as traditional inverter circuits and chopper circuits, and generally have two modes: one is to directly use the P well region of the device, N^－Drift region and N⁺A parasitic PIN diode formed in the substrate. However, the parasitic silicon carbide diode obtained in this way has a large conduction voltage drop (the conduction voltage drop of the silicon carbide PN junction is about 3V), and has poor reverse recovery characteristics (the drift region conductance modulation injects a large amount of excess load when conducting in the forward directionCurrent), resulting in high power loss, which is contrary to the application concept of underlining green; meanwhile, the low working efficiency caused by the low working speed is very unfavorable for the application of the silicon carbide UMOSFET in an inverter circuit, a chopper circuit and the like; however, the method causes the increase of system cost, the increase of volume and the reduction of reliability caused by the increase of metal connecting wires, and finally, the popularization of the silicon carbide VDMOS device in the application of circuits such as a traditional inverter circuit, a chopper circuit and the like is hindered to a certain extent.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a SiC-MOS device structure can regulate and control schottky barrier height to form the lower schottky contact that switches on the pressure drop, showing and having reduced the power electronic system volume, reduced the encapsulation cost, improved system application reliability, also have a big promotion to basic performance and permanent application reliability, have lower specific on-resistance, have the characteristics that the electric leakage is low, in order to solve the problem of proposing among the above-mentioned background art.

In order to achieve the above object, the utility model provides a following technical scheme:

a SiC-MOS device structure comprises a metal drain electrode, a silicon carbide N + substrate and a silicon carbide N-epitaxial layer which are sequentially arranged from bottom to top, wherein source electrode grooves are formed in the upper left side and the upper right side of the silicon carbide N-epitaxial layer, a silicon carbide P + doped region and a silicon carbide P-type doped region are formed in the lower portion of the source electrode groove from top to bottom, the depth of the silicon carbide P-type doped region is 0.6 mu m, and the doping concentration is 3 multiplied by 10¹⁸cm^-3The depth of the silicon carbide P + doped region is 0.3 mu m, and the doping concentration is 1 multiplied by 10¹⁹cm^-3Schottky contact metal is filled in the source electrode grooves, grid electrode grooves are formed in the silicon carbide N-epitaxial layer, and grid electrode structures are arranged in the grid electrode grooves and on the surface of the grid electrode grooves;

the gate structure comprises an insulated gate dielectric layer, a polysilicon gate and gate metal from bottom to top, wherein the insulated gate dielectric layer isolates the polysilicon gate from a silicon carbide N + substrate, the upper part of the polysilicon gate is led out through the gate metal, the polysilicon gate is arranged in a gate groove, and the gate metal is arranged on the surface of the gate groove;

a first table structure and a second table structure are respectively arranged between the source electrode groove and the grid electrode groove, the first table structure and the second table structure are respectively composed of a silicon carbide N-epitaxial layer, a silicon carbide P-type doped region and a silicon carbide N + source region, the silicon carbide P-type doped region and the silicon carbide N + source region are both arranged inside the silicon carbide N-epitaxial layer, the silicon carbide N + source region is positioned above the silicon carbide P-type doped region, one side of the silicon carbide N + source region is in contact with Schottky contact metal, the other side of the silicon carbide N + source region is in contact with the grid electrode groove, the depth of the silicon carbide N + source region is 0.3 mu m, and the doping concentration is 1 multiplied by 10¹⁹cm^-3；

Schottky contact metal in the source electrode groove is in direct contact with the silicon carbide N-epitaxial layer at the bottom of the side wall of the source electrode groove to form Schottky contact with rectification characteristics, source electrode metal covers the silicon carbide N + source region and the Schottky contact metal, and the source electrode metal and the grid electrode metal are isolated from each other through an insulating medium layer.

Preferably, the insulating medium layer is a borophosphosilicate glass layer.

Preferably, the gate metal is a deposition layer formed by combining one or more of metal materials of Al, Pt, Au, TiN and TiNiAg.

Preferably, the total thickness of the metal drain electrode is more than 1 μm, and the metal drain electrode is a deposition layer formed by combining one or more of TiNiAg, VNiAg, TiNiAu and VNiAu.

Compared with the prior art, the beneficial effects of the utility model are that:

the utility model discloses an on the basis of traditional carborundum UMOSFET structure, source electrode region adopts the slot structure to do the dark P of carborundum and pour into bottom the slot, source electrode ditch inslot uses schottky contact metal, and schottky contact metal and carborundum N-epitaxial layer form the schottky diode that has the rectification characteristic in source electrode ditch groove lateral wall bottom direct contact. The Schottky barrier height can be regulated and controlled by changing the metal material, process control and the concentration of the silicon carbide N-epitaxial layer to form a Schottky contact with lower conduction voltage drop (Von), generally the contact Von is in the range of 0.8V-2V, so that the in-vivo integration of the Schottky diode with the forward working performance superior to that of a parasitic diode is realized. Meanwhile, because the metal lead wire between the diode and the diode is not arranged, the parasitic effect caused by the metal lead wire is avoided, and the application reliability of the system is improved. Simultaneously, for the mode of numerous internal monolithic integrated diodes, the utility model discloses the structure has more compact cellular area. And simultaneously, the utility model discloses a two dark carborundum P type doped regions of design help promoting the withstand voltage level of device to and reduce device grid dielectric layer electric field, thereby also have a big promotion to the basic capability and the permanent application reliability of traditional UMOSFET device. Simultaneously, because two dark carborundum P type doping regions are to the withstand voltage's of device promotion for JFET district's doping can effectively improve, so the utility model discloses a SiC-MOS device has lower specific on resistance, and in addition, the many son rectifier devices of integration have the characteristics that the electric leakage is low.

Drawings

FIG. 1 is a schematic cross-sectional structure diagram of a conventional SiC-MOS device;

fig. 2 is a schematic cross-sectional structure diagram of the present invention;

fig. 3 is a schematic diagram of the gate trench and the source trench according to the present invention.

In the figure: 101. a silicon carbide N + substrate; 102. a silicon carbide N-epitaxial layer; 103. a gate trench; 104. A source electrode trench; 105. a silicon carbide P-type doped region; 106. a silicon carbide P + doped region; 107. a silicon carbide N + source region; 108. SiO 2₂An insulated gate dielectric layer; 109. a polysilicon gate; 110. a gate metal; 111. a metal drain electrode; 112. a Schottky contact metal; 113.a borophosphosilicate glass insulating dielectric layer; 114. and a source metal.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 2-3, the present invention provides a technical solution:

a SiC-MOS device structure comprises a metal drain 111, a silicon carbide N + substrate 101 and a silicon carbide N-epitaxial layer 102 which are sequentially arranged from bottom to top, wherein the total thickness of the metal drain 111 is more than 1 mu m, the metal drain 111 is a deposition layer formed by one or any combination of TiNiAg, VNiAg, TiNiAu and VNiAu metal materials, source trenches 104 are respectively arranged at the upper left and the upper right of the silicon carbide N-epitaxial layer 102, a silicon carbide P + doped region 106 and a silicon carbide P-type doped region 105 are arranged below the source trenches 104 from top to bottom, the depth of the silicon carbide P + doped region 106 is 0.3 mu m, and the doping concentration is 1 multiplied by 10¹⁹cm^-3The silicon carbide P-type doped region 105 has a depth of 0.6 μm and a doping concentration of 3X 10¹⁸cm^-3The source trenches 104 are filled with schottky contact metal 112, and the silicon carbide N-epitaxial layer 102 has gate trenches 103 therein.

The gate trench 103 is internally and externally provided with a gate structure, the gate structure comprises an insulated gate dielectric layer 108, a polysilicon gate 109 and gate metal 110 from bottom to top, the insulated gate dielectric layer 108 isolates the polysilicon gate 109 from the silicon carbide N + substrate 101, the upper part of the polysilicon gate 109 is led out through the gate metal 110, the polysilicon gate 109 is arranged inside the gate trench 103, the gate metal 110 is arranged on the surface of the gate trench 103, and the gate metal 110 is a deposition layer formed by combining one or more of metal materials Al, Pt, Au, TiN and TiNiAg.

Between source trench 104 and gate trench 103A first mesa structure and a second mesa structure are respectively arranged, the first mesa structure and the second mesa structure are respectively composed of a silicon carbide N-epitaxial layer 102, a silicon carbide P-type doped region 105 and a silicon carbide N + source region 107, the silicon carbide P-type doped region 105 and the silicon carbide N + source region 107 are both arranged in the silicon carbide N-epitaxial layer 102, the silicon carbide N + source region 107 is positioned above the silicon carbide P-type doped region 105, the upper part of one side of the silicon carbide N + source region 107 is contacted with a Schottky contact metal 112, the other side of the silicon carbide N + source region is contacted with a grid trench 103, the depth of the silicon carbide N + source region 107 is 0.3 mu m, the doping concentration is 1 multiplied by 10¹⁹cm^-3。

The schottky contact metal 112 in the source trench 104 directly contacts the silicon carbide N-epitaxial layer 102 at the bottom of the sidewall of the source trench 104 to form a schottky contact with rectification characteristic, the source metal 114 covers the silicon carbide N + source region 107 and the schottky contact metal 112, the source metal 114 and the gate metal 110 are isolated from each other by an insulating dielectric layer 113, and the insulating dielectric layer 113 is a borophosphosilicate glass layer.

The structure principle is as follows: the utility model discloses an on the basis of traditional carborundum UMOSFET structure, source region adopts the groove structure to do the dark P of carborundum and pour into bottom the slot, use Schottky contact metal 112 in the source slot 104, and Schottky contact metal 112 and carborundum N-epitaxial layer 102 form the Schottky diode that has the rectification characteristic in source slot 104 lateral wall bottom direct contact. The Schottky barrier height can be regulated and controlled by changing the metal material, process control and the concentration of the silicon carbide N-epitaxial layer 102 to form a Schottky contact with lower conduction voltage drop (Von), generally the contact Von is in the range of 0.8V-2V, so that the in-vivo integration of the Schottky diode with the forward working performance superior to that of a parasitic diode is realized. Meanwhile, because the metal lead wire between the diode and the diode is not arranged, the parasitic effect caused by the metal lead wire is avoided, and the application reliability of the system is improved. Simultaneously, for the mode of numerous internal monolithic integrated diodes, the utility model discloses the structure has more compact cellular area. And simultaneously, the utility model discloses a two dark carborundum P type doped region 105 of design help promoting the withstand voltage level of device to and reduce device grid dielectric layer electric field, thereby also have a big promotion to the basic capability and the permanent application reliability of traditional UMOSFET device. Simultaneously, because two dark carborundum P type doping regions 105 are to the withstand voltage's of device promotion for JFET district's doping can effectively improve, so the utility model discloses a SiC-MOS device has lower specific on-resistance, and in addition, the many son rectifier devices of integration have the characteristics that the electric leakage is low.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. The utility model provides a SiC-MOS device structure, includes metal drain (111), carborundum N + substrate (101) and carborundum N-epitaxial layer (102) that set gradually from bottom to top, its characterized in that: the silicon carbide N-epitaxial layer (102) is provided with source trenches (104) at the upper left and the upper right, a silicon carbide P + doped region (106) and a silicon carbide P-type doped region (105) are arranged below the source trenches (104) from top to bottom, the depth of the silicon carbide P-type doped region (105) is 0.6 mu m, and the doping concentration is 3 multiplied by 10¹⁸cm^-3The depth of the silicon carbide P + doped region (106) is 0.3 mu m, and the doping concentration is 1 multiplied by 10¹⁹cm^-3The source trenches (104) are filled with Schottky contact metal (112), the silicon carbide N-epitaxial layer (102) is provided with gate trenches (103) inside, and the gate trenches (103) are provided with gate structures inside and on the surface;

the gate structure comprises an insulated gate dielectric layer (108), a polysilicon gate (109) and gate metal (110) from bottom to top, wherein the insulated gate dielectric layer (108) isolates the polysilicon gate (109) from a silicon carbide N + substrate (101), the upper part of the polysilicon gate (109) is led out through the gate metal (110), the polysilicon gate (109) is arranged in a gate groove (103), and the gate metal (110) is arranged on the surface of the gate groove (103);

a first mesa structure and a second mesa structure are respectively arranged between the source trench (104) and the gate trench (103), the first mesa structure and the second mesa structure are respectively formed by a silicon carbide N-epitaxial layer (102), a silicon carbide P-type doped region (105) and a silicon carbide N + source region (107), the silicon carbide P-type doped region (105) and the silicon carbide N + source region (107) are both arranged inside the silicon carbide N-epitaxial layer (102), the silicon carbide N + source region (107) is positioned above the silicon carbide P-type doped region (105), one side of the silicon carbide N + source region (107) is contacted with Schottky contact metal (112) and the other side is contacted with the gate trench (103), the depth of the silicon carbide N + source region (107) is 0.3 mu m, and the doping concentration is 1 multiplied by 10¹⁹cm^-3；

The Schottky contact metal (112) in the source trench (104) is in direct contact with the silicon carbide N-epitaxial layer (102) at the bottom of the side wall of the source trench (104) to form a Schottky contact with rectification characteristics, the silicon carbide N + source region (107) and the Schottky contact metal (112) are covered with source metal (114), and the source metal (114) and the gate metal (110) are isolated from each other through an insulating medium layer (113).

2. The SiC-MOS device structure of claim 1, wherein: the insulating medium layer (113) is a boron-phosphorus-silicon glass layer.

3. The SiC-MOS device structure of claim 2, wherein: the grid metal (110) is a deposition layer formed by one or any combination of metal materials of Al, Pt, Au, TiN and TiNiAg.

4. The SiC-MOS device structure of claim 1, wherein: the total thickness of the metal drain electrode (111) is larger than 1 mu m, and the metal drain electrode (111) is a deposition layer formed by combining one or more of TiNiAg, VNiAg, TiNiAu and VNiAu serving as a metal material.