CN111799322A - Double-groove type SiC MOSFET structure for high-frequency application and manufacturing method - Google Patents
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Abstract
The invention discloses a double-groove type SiC MOSFET structure for high-frequency application and a manufacturing method thereof, wherein the double-groove type SiC MOSFET structure is constructed on N++N on type SiC substrate‑A type SiC epitaxial layer comprising: gate trench, source trench, N+Source region, P-type base region, P+Shielding region, N-type current spreading region and N‑Epitaxial layer of type wherein N+The source region and the P-type base region are arranged from top to bottom, P+The shielding region is arranged below the P-type base region and the source electrode trench, and the N-type current expansion region is arranged below the P-type base region and the source electrode trench+Outside of the shielded region，N‑The type epitaxial layer is positioned below the middle area of the groove bottom of the grid groove and the N-type current expansion area. The structure not only has the excellent static quality factor of the traditional double-groove SiC MOSFET, but also can obviously reduce the switching loss and improve the short-circuit tolerance capability.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a double-groove SiC MOSFET structure for high-frequency application and a manufacturing method thereof.
Background
SiC is a typical third-generation semiconductor material, and has a large forbidden band width, a high critical breakdown field strength, and a high thermal conductivity compared to Si. Therefore, compared with the traditional Si-based power semiconductor device, the SiC-based power semiconductor device can realize high-temperature, high-voltage and high-frequency work, and obviously improves the energy conversion efficiency of the system, reduces the volume of the system and improves the reliability of the system.
Although Si-based IGBT power devices have been widely used in industrial production and living equipment, they have significant tail currents, increasing switching losses on the one hand and also limiting the maximum operating frequency on the other hand. Therefore, the Si-based IGBT may be difficult to meet the high frequency and high efficiency requirements of advanced power electronic systems. The SiC-based power MOSFET device can avoid the trailing current phenomenon of the Si-based IGBT, greatly improves the working frequency, and is expected to replace the Si-based IGBT device with the same voltage level in the future.
One major bottleneck in the current development of SiC MOSFETs is the extremely low channel inversion layer mobility, primarily due to the presence of SiO2Interface states at the/SiC interface and scattering by trapped charges. In order to solve the problem, the trench SiC MOSFET structure can reduce the cell width and increase the cell density, and can realize high mobility in different crystal directions. However, at high voltages, the electric field concentration effect at the bottom of the SiC trench can cause premature breakdown of the device, thereby reducing the device breakdown voltage.
In order to suppress the problem of electric field concentration at the bottom of the trench SiC MOSFET, two solutions are mainly used at present. One is to directly add a layer of P with high doping concentration at the bottom of the SiC groove+And a region for transferring a position where the electric field is concentrated. However, this approach can introduce JFET effects, limiting the width of the flow path for electrons from the channel to the epitaxial layer, resulting in higher device resistance. Another solution is the double trench type SiC MOSFET structure proposed by Rohm corporation. Although this double trench structure can achieve a better compromise between breakdown voltage and on-resistance, the electric field at the bottom of the trench is still high and the gate still remainsOxygen reliability issues. Meanwhile, the gate-drain capacitance is high, the switching speed of the device is reduced, the switching loss is increased, and the high-frequency application is not facilitated. The current focus of research on trench SiC MOSFETs is how to make a better compromise between reducing the oxide field and reducing the device resistance.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art.
To this end, an object of the present invention is to propose a double trench SiC MOSFET structure for high frequency applications.
Another object of the present invention is to propose a method for manufacturing a double trench SiC MOSFET for high frequency applications.
In order to achieve the above object, an embodiment of an aspect of the present invention provides a dual trench SiC MOSFET structure for high frequency applications, where the dual trench SiC MOSFET structure is constructed on N++N on type SiC substrate-A type SiC epitaxial layer comprising: gate trench, source trench, N+Source region, P-type base region, P+Shielding region, N-type current spreading region and N-Epitaxial layer of type wherein said N+The source region and the P-type base region are arranged from top to bottom, and the P is arranged+A shielding region below the P-type base region and the source trench, and an N-type current extension region below the P-type base region+Outside of the shielded region, N-The type epitaxial layer is located in the middle area of the groove bottom of the grid groove and below the N-type current expansion area.
The double-groove SiC MOSFET structure for high-frequency application provided by the embodiment of the invention can effectively reduce an oxide layer electric field and the on-resistance of a device, and can realize smaller gate-drain capacitance and switching loss, and the short circuit tolerance of the device is further enhanced, so that the double-groove SiC MOSFET structure is more suitable for high-frequency application.
In addition, the double trench type SiC MOSFET structure for high frequency applications according to the above embodiments of the present invention may also have the following additional technical features:
further, in an embodiment of the present invention, the gate trench is smaller than the source trench in depth, wherein the trench depth of the gate trench is 0.3 to 1.5 μm.
Further, in one embodiment of the present invention, a surface of the gate trench is covered with a gate dielectric layer, and an interior of the gate trench is filled with a gate electrode material.
Further, in an embodiment of the present invention, wherein the gate dielectric layer is a thermal oxide layer, and the gate electrode material is formed by metal or polysilicon deposition.
Further, in one embodiment of the present invention, the N is+The width of the source region is the same as that of the P-type base region, and the sum of the depths of the two regions is not less than the depth of the grid groove.
Further, in one embodiment of the present invention, the N-type current spreading layer is larger than the N-The doping concentration of the drift layer is at least half order of magnitude greater than that of P+The doping concentration of the screening region is at least an order of magnitude smaller.
In order to achieve the above object, another embodiment of the present invention provides a method for manufacturing a dual trench SiCMOSFET for high frequency applications, including the following steps: s101, at N++The doping concentration of the growth on the type SiC substrate is 5e13～3e17cm-3First layer N of–A type epitaxial layer; s102, adopting a local ion implantation method to form the first layer N-Preparing an N-type current expansion region on the epitaxial layer; s103, preparing P in the N-type current expansion region by changing the species, the dosage and the energy of implanted ions by adopting the local ion implantation method+A shielding region; s104, in the first layer N-Epitaxially growing a doping concentration of 5e above the epitaxial layer13～3e17cm-3Second layer N of-A type epitaxial layer; s105, adopting a local etching method to etch the first layer N-Preparing a grid groove above the type epitaxial layer and the N type current expansion region; s106, adopting the local ion implantation method to change the species, dosage and energy of implanted ions in the second layer N-Epitaxial layer of type or/and N in the first layer-Preparing N in epitaxial layer+Source regionAnd a P-type base region; s107, forming a second N layer by using the local etching method-Epitaxial layer and deep into the P+A source trench of the shield region; s108, forming a gate dielectric layer through a thermal oxidation or dielectric layer deposition process, and forming a gate electrode through a metal or polysilicon deposition process; s109, depositing an interlayer isolation medium above the device and patterning the interlayer isolation medium; and S110, depositing thickened metal above the grid electrode and the source electrode of the device.
The method for manufacturing the double-groove type SiC MOSFET facing the high-frequency application can be used for preparing the double-groove type SiC MOSFET structure with high quality, has high process maturity, strong controllability, good repeatability and consistency and low manufacturing cost, and is particularly suitable for automatic batch production.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic diagram of a dual trench SiC MOSFET structure for high frequency applications in accordance with an embodiment of the present invention;
FIG. 2 is a schematic view showing an exemplary structure of a conventional single-trench type SiC MOSFET in an embodiment of the present invention;
fig. 3 is a schematic view showing an exemplary structure of a conventional double-trench type SiC MOSFET in an embodiment of the present invention;
FIG. 4 is a graph showing a comparison of static performance of the three SiC MOSFET structures of FIGS. 1-3, as simulated in an embodiment of the present invention;
FIG. 5 is a graph of the distribution topology of the blocking electric field strength of the three SiC MOSFET structures of FIGS. 1-3 obtained by simulation in an embodiment of the present invention;
FIG. 6 is a graph showing a comparison of gate charge characteristics of the three SiC MOSFETs of FIGS. 1-3 obtained by simulation in accordance with an embodiment of the present invention;
FIG. 7 is a graph showing a comparison of gate-to-drain capacitance values obtained by simulation for the three SiC MOSFET structures of FIGS. 1-3, in accordance with an embodiment of the present invention;
FIG. 8 is a graph showing a comparison of the short circuit performance of the three SiC MOSFET structures of FIGS. 1-3, as simulated in an embodiment of the present invention;
fig. 9 is a flowchart of a method of fabricating a dual trench SiC MOSFET structure for high frequency applications in accordance with an embodiment of the present invention;
fig. 10 is a flow chart of a method for fabricating a double trench SiC MOSFET structure for high frequency applications in accordance with an embodiment of the present invention.
Description of reference numerals:
100-double trench type SiC MOSFET structure for high frequency applications; 1-N++A type SiC substrate; 2-N-Type SiC epitaxial layers/drift layers; 3-gate trench/gate oxide; 4-source trenches; 5-N+A source region; 6-P type base region; 7-P+A shielding region; an 8-N type current spreading region; 9-gate electrode/polysilicon gate; 10-an interlayer dielectric; 11-source metal.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
The high-frequency application-oriented double-trench SiC MOSFET structure and the preparation method thereof according to the embodiments of the present invention will be described below with reference to the accompanying drawings, and first, the high-frequency application-oriented double-trench SiC MOSFET structure according to the embodiments of the present invention will be described with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a double trench SiC MOSFET structure for high frequency applications in an embodiment of the invention.
As shown in FIG. 1, the double trench type SiC MOSFET structure 100 is built at N++N on type SiC substrate 1-Type SiC epitaxial layer 2, comprising: gate trench 3, source trench 4, N+Source region 5, P-type base region 6, P+Shielding region 7, N-type current spreading region 8 and N-Type epitaxial layer 2, wherein N+The source region 5 and the P-type base region 6 are arranged from top to bottom, P+A shielding region 7 is positioned below the P-type base region 6 and the source trench 4, and an N-type current expansion region 8 is positioned below the P-type base region 6+Outside of the shielded region 7, N-The type epitaxial layer 2 is located under the bottom middle region of the gate trench 3 and the N-type current extension region 8.
Furthermore, the groove depth of the gate trench 3 is 0.3-1.5 microns, which is smaller than the depth of the source trench 4, and the surface of the gate trench 3 is covered with a thin gate dielectric layer 3. The gate dielectric layer 3 can be made of various dielectric materials, preferably, the gate dielectric layer 3 is made of N-The thickness of the thermal oxidation layer 3 grown in the type SiC epitaxial layer 2 is usually selected to be 1-100 nanometers. The surface of the gate dielectric within the gate trench 3 is covered with a gate electrode material 9. preferably, the filled gate electrode material 9 is doped polysilicon, typically formed by metal or polysilicon deposition.
Further, N+The source region 5 and the P-type base region 6 are arranged from top to bottom, have the same width, and the sum of the depths of the two regions is greater than or equal to the depth of the gate trench 3. In general, the N-type current spreading layer ratio N in the embodiments of the present invention-The doping concentration of the drift layer is at least half order of magnitude greater than that of P+The doping concentration of the screening region is at least an order of magnitude smaller.
The innovations and advantages of the dual trench silicon carbide MOSFET structure for high frequency applications proposed by the embodiments of the present invention will be described in detail below with reference to the accompanying fig. 1-8 by comparing the performance simulation results of the existing typical single trench type and dual trench type SiC MOSFET structures.
The embodiment of the invention is based on
TCAD software, following simulation comparative analysis of three exemplary device structures in fig. 1-3. In the simulation, the structural parameters of three typical devices are optimized.
FIG. 1 shows a double trench type SiC MOSFET structure according to an embodiment of the present invention, in which the cell width (lateral length in the drawing) is 2.1 μm and the gate trench depth(longitudinal length in the drawing) was 0.7. mu.m. In FIG. 2, the cell width of the conventional single trench type SiC MOSFET device is 2.1 μm, and the trench depth is 1.5 μm. In fig. 3, the cell width of the conventional double-trench SiC MOSFET device is 2.2 μm, and the trench depth is 1.5 μm. In the simulation, the doping concentration of the P + shielding region is 1e18cm-3. The thickness of the epitaxial drift layer of each of the three devices is 10 μm, and the doping concentration is 8e15cm-3. The following table 1 gives the main structural parameters used in the simulation verification.
TABLE 1
| Item | Numerical value | Unit of |
| Thickness of |
10 | μm |
| Doping concentration of epitaxial layer | 8e15 | cm-3 |
| P+Doping concentration of the shielding region | 2e18 | cm-3 |
| Doping concentration of P-type base region | 2e17 | cm-3 |
| Channel length | 0.5 | μm |
| Thickness of gate oxide | 0.05 | μm |
As shown in fig. 4, the static on characteristics of the three device structures obtained by the simulation were obtained. As can be seen from fig. 4, the SiC MOSFET structure of the embodiment of the present invention can achieve a smaller saturation current than the conventional single trench and conventional double trench SiC MOSFET structures. The small saturation current value means that the short circuit endurance of the device and the robust characteristic of the device can be greatly improved. Meanwhile, the specific on-resistance of the SiC MOSFET is smaller than that of the other two devices, so that the on-loss of the devices can be reduced.
As shown in fig. 5, the electric field distribution topology of the three device structures obtained by simulation. The electric field distribution in fig. 5 is taken at Vds of 1200V. Compared with other two device structures, the SiC MOSFET provided by the embodiment of the invention has the advantages that the electric field intensity of the maximum oxide layer is remarkably reduced, and therefore, the gate oxide reliability of the device can be improved. In addition, the SiC MOSFET provided by the embodiment of the invention has low oxide layer electric field intensity and low on-resistance, and realizes better compromise between the on-resistance and the gate oxide electric field intensity.
As shown in fig. 6, gate charge characteristics of the three device structures obtained were simulated. It can be seen that the gate charge Qgd of the SiC MOSFET of the embodiments of the present invention is significantly reduced compared to the other two device structures. As shown in fig. 7, the gate-to-drain capacitance of the three device structures obtained by the simulation varies with the drain voltage. The smaller gate-drain capacitance can greatly reduce the time of the miller voltage in the switching process, thereby reducing the switching time and the switching loss. In power electronic systems, most of the losses result from switching losses when SiC MOSFETs are operated at high frequencies. Therefore, the SiC MOSFET of the embodiment of the present invention has a greater advantage in high frequency applications.
Fig. 8 shows the results of simulation of the short-circuit characteristics of three devices. In power electronics applications, during the turn-on of a SiC MOSFET, the high supply voltage will directly bias the drain of the SiC MOSFET due to a short circuit of the load. At this time, high voltage and large current cause excessive loss, which causes junction temperature rise of the SiC MOSFET, thereby damaging the device. As can be seen from fig. 8, the SiC MOSFET of the embodiment of the present invention has smaller short-circuit current and maximum junction temperature under the same circuit parameters, which benefits from P mainly+Pinch-off of the shielded area.
In summary, the double-trench SiC MOSFET structure for high-frequency applications provided in the embodiments of the present invention can effectively reduce an oxide electric field and on-resistance of a device, and can also realize smaller gate-drain capacitance and switching loss, and the short-circuit endurance of the device is further enhanced, so that the structure is more suitable for high-frequency applications.
Next, a method for manufacturing a double trench type SiCMOSFET structure for high frequency applications according to an embodiment of the present invention will be described with reference to the accompanying drawings.
Fig. 9 is a flowchart of a method of fabricating a double trench SiC MOSFET structure for high frequency applications in accordance with an embodiment of the present invention.
As shown in fig. 9, the method for manufacturing a double trench type SiC MOSFET for high frequency applications includes the steps of:
in step S901, in N++The doping concentration of the growth on the type SiC substrate is 5e13～3e17cm-3First layer N of–And (3) a type epitaxial layer.
In step S902, a local ion implantation method is used to form a first layer N-And preparing an N-type current expansion region on the epitaxial layer.
In step S903, P is formed in the N-type current spreading region by changing the type, dose and energy of the implanted ions by local ion implantation+And a shielding region.
In step S904, in the first layer N-Epitaxially growing a doping concentration of 5e above the epitaxial layer13～3e17cm-3Second layer N of-And (3) a type epitaxial layer.
In step S905, a partial etching method is used to form a first layer N-And preparing a grid groove above the type epitaxial layer and the N type current expansion region.
In step S906, the second layer N is implanted by changing the type, dose and energy of the implanted ions by using a local ion implantation method-Epitaxial layer of type or/and N in the first layer-Preparing N in epitaxial layer+A source region and a P-type base region.
In step S907, a partial etching method is used to form a through second layer N-Type epitaxial layer and deep into P+A source trench of the shield region.
In step S908, a gate dielectric layer is formed by thermal oxidation or dielectric layer deposition process, and a gate electrode is formed by metal or polysilicon deposition process.
In step S909, an interlayer isolation dielectric is deposited over the device and patterned.
In step S910, metal electrodes on the gate and source are formed using a metal deposition process.
A method for fabricating a double trench type SiC MOSFET structure for high frequency applications according to an embodiment of the present invention will be described in detail with reference to specific embodiments, as shown in fig. 10.
And 8, as shown in fig. 13(i), forming an ohmic contact metal electrode on the source electrode by adopting a metal deposition process, depositing an interlayer isolation medium above the device, and patterning the interlayer isolation medium by photoetching and etching. The interlayer isolation medium is generally SiO2 and Si3N4Or a combination of both.
It should be noted that, as known to those skilled in the art, the embodiments of the present invention may be manufactured by using the existing semiconductor process, and are not described in detail for reducing redundancy.
According to the preparation method of the high-frequency application-oriented double-groove type SiC MOSFET structure, the double-groove type SiC MOSFET structure can be prepared with high quality, the process maturity is high, the controllability is strong, the repeatability and the consistency are good, the manufacturing cost is low, and the preparation method is particularly suitable for automatic batch production.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (7)
1. A double-groove type SiC MOSFET structure for high-frequency application is characterized in that the double-groove type SiC MOSFET structure is constructed on N++N on type SiC substrate-A type SiC epitaxial layer comprising: gate trench, source trench, N+Source region, P-type base region, P+Shielding region, N-type current spreading region and N-Epitaxial layer of type wherein said N+The source region and the P-type base region are arranged from top to bottom, and the P is arranged+A shielding region below the P-type base region and the source trench, and an N-type current extension region below the P-type base region+Outside of the shielded region, N-The type epitaxial layer is located in the middle area of the groove bottom of the grid groove and below the N-type current expansion area.
2. The double trench SiC MOSFET structure for high frequency applications of claim 1, wherein the gate trench is smaller than the source trench in depth, wherein the gate trench has a trench depth of 0.3 to 1.5 microns.
3. The double trench SiC MOSFET structure for high frequency applications of claim 1, wherein the gate trench is covered at a surface with a gate dielectric layer and filled at an inside with a gate electrode material.
4. The double trench SiC MOSFET structure for high frequency applications of claim 3, wherein the gate dielectric layer is a thermal oxide layer and the gate electrode material is formed by metal or polysilicon deposition.
5. Double trench SiC MOSFET structure for high frequency applications according to claim 1, characterized in that the N is+The width of the source region is the same as that of the P-type base region, and the sum of the depths of the two regions is not less than the depth of the grid groove.
6. The double trench SiC MOSFET structure for high frequency applications of claim 1, wherein the N-type current spreading layer is larger than the N-The doping concentration of the drift layer is at least half order of magnitude greater than that of P+The doping concentration of the screening region is at least an order of magnitude smaller.
7. A manufacturing method of a double-groove type SiC MOSFET for high-frequency application is characterized by comprising the following steps:
in N++The doping concentration of the growth on the type SiC substrate is 5e13～3e17cm-3First layer N of–A type epitaxial layer;
forming the first layer N by local ion implantation-Preparing an N-type current expansion region on the epitaxial layer;
preparing P in the N-type current expansion region by changing the species, dosage and energy of implanted ions by adopting the local ion implantation method+A shielding region;
in the first layer N-Epitaxially growing a doping concentration of 5e above the epitaxial layer13～3e17cm-3Second layer N of-A type epitaxial layer;
applying a local etching method to the first layer N-Preparing a grid groove above the type epitaxial layer and the N type current expansion region;
using the local ion implantation method to implant ions in the second layer N by changing the species, dose and energy of the implanted ions-Epitaxial layer of type or/and N in the first layer-Preparing N in epitaxial layer+A source region and a P-type base region;
forming a via through the second layer N using the partial etch process-Epitaxial layer and deep into the P+A source trench of the shield region;
forming a gate dielectric layer by a thermal oxidation or dielectric layer deposition process, and forming a gate electrode by a metal or polysilicon deposition process;
depositing an interlayer isolation medium above the device and patterning the interlayer isolation medium;
a thickened metal is deposited over the gate and source of the device.
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