CN107464837B - Super junction power device - Google Patents
Super junction power device Download PDFInfo
- Publication number
- CN107464837B CN107464837B CN201710665471.8A CN201710665471A CN107464837B CN 107464837 B CN107464837 B CN 107464837B CN 201710665471 A CN201710665471 A CN 201710665471A CN 107464837 B CN107464837 B CN 107464837B
- Authority
- CN
- China
- Prior art keywords
- type semiconductor
- conductive type
- conductivity
- region
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 91
- 210000000746 body region Anatomy 0.000 claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 239000011810 insulating material Substances 0.000 claims 1
- 229910000464 lead oxide Inorganic materials 0.000 claims 1
- YEXPOXQUZXUXJW-UHFFFAOYSA-N oxolead Chemical compound [Pb]=O YEXPOXQUZXUXJW-UHFFFAOYSA-N 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 230000010355 oscillation Effects 0.000 abstract description 5
- 238000000034 method Methods 0.000 description 12
- 239000003292 glue Substances 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 238000004140 cleaning Methods 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 7
- 230000008859 change Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 150000008040 ionic compounds Chemical class 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000035772 mutation Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to the technical field of power semiconductor devices, in particular to a super junction power device. The second conduction type semiconductor columns in the first conduction type semiconductor drift region of the super junction power device have two or more different widths (a1, a2 … …, an; n is more than or equal to 2), the space between two adjacent second conduction type semiconductor columns has two or more different widths (b1, b2 … …, bm; m is more than or equal to 2), and due to the fact that drain-source voltage points corresponding to depletion of the super junction columns with different widths and spaces are different, source-drain voltage spans of sudden drop of Miller capacitance Cgd and drain-source capacitance Cds are increased, the sudden drop of Cgd and Coss is relieved, and current-voltage oscillation is reduced.
Description
Technical Field
The invention relates to the technical field of power semiconductor devices, in particular to a super junction power device.
Background
The capacitance characteristics are critical to the turn-on and turn-off process of the power DMOS device, and affect the switching speed and emi (electrical interference) characteristics of the device. The super junction VDMOS also has a difference in capacitance characteristics due to a difference in drift region structure from the conventional VDMOS: the output capacitance (Coss) and miller capacitance (Cgd) curves of a superjunction VDMOS exhibit a highly non-linear relationship as the drain-source voltage increases. Because of the higher cell density, the Coss initial value of the super junction VDMOS is higher and Coss and Cgd will exhibit a steep drop around a certain drain-source voltage, as shown in fig. 1, due to the fact that at this voltage the N column is fully depleted and the area equivalent to Coss and Cgd is reduced. When the super junction VDMOS is applied to the PFC or DC/DC converter, a steep drop phenomenon of capacitance may cause voltage and current oscillation, generating EMI noise.
Patent CN 104952928 provides a super junction power device with gradually varied gate-drain capacitance, which is characterized in that the body regions have two or more unequal widths, and two or more unequal distances are provided between adjacent body regions, so that the sudden change of gate-drain capacitance of the super junction power device during turning on or off is distributed to multiple voltage nodes, thereby reducing the electromagnetic interference caused by the sudden change of gate-drain capacitance. However, the steep drop of the super junction device Cgd is mainly caused by mutual depletion of PN columns, but not by depletion of JFET regions between adjacent body regions, so that the scheme only changes the spacing of the body regions, and cannot well achieve the effect of slowing down Cgd.
Disclosure of Invention
Aiming at the problems, the invention provides the super-junction power VDMOS device, which solves the problem of steep drop of Cgd and Coss of the super-junction VDMOS along with the increase of drain-source voltage on the premise of not influencing the withstand voltage of the device, and improves the capacitance characteristic of the device.
The technical scheme adopted by the invention is as follows: a super junction power device is provided with a metalized drain electrode 1, a first conductive type semiconductor substrate 2, a first conductive type lightly doped epitaxial layer 3 and a metalized source electrode 10 which are sequentially stacked from bottom to top; the first conductive type lightly doped epitaxial layer 3 is provided with a second conductive type semiconductor column 4; the top of the second conductivity type semiconductor pillar 4 has a second conductivity type semiconductor body region 5; the second conductive type semiconductor body region 5 is provided with a first conductive type semiconductor source region 6 and a second conductive type semiconductor heavily-doped contact region 11, and the second conductive type semiconductor body region 5 between the first conductive type semiconductor 6 and the adjacent first conductive type lightly-doped epitaxial layer 3 is a channel region; the gate oxide layer 7 covers the channel region and the first conductive type lightly doped epitaxial layer 3; the polysilicon gate 8 covers the gate oxide layer 7, and the dielectric layer 9 surrounds the polysilicon gate 8 and the gate oxide layer 7, so that the polysilicon gate 8 is electrically isolated from the metalized source electrode 10. The upper surface of the second conductive type semiconductor heavily doped contact region 11 and part of the upper surface of the first conductive type semiconductor source region 6 are in direct contact with the metalized source 10. The second conductive type semiconductor columns 4 have two or more different widths (a1, a2 … …, an; n is more than or equal to 2), the space between two adjacent second conductive type semiconductor columns 4 has two or more different widths (b1, b2 … …, bm; m is more than or equal to 2), and the second conductive type semiconductor columns 4 and the adjacent first conductive type lightly doped regions meet the charge balance.
The invention has the beneficial effects that: super junction VDMOS is near a certain drain-source voltage, Coss and Cgd drop rapidly, possibly causing voltage and current oscillations. This oscillation may cause gate-source breakdown, poor EMI, large switching losses, gate control failures, and may even cause device failure. By changing the width and the spacing of the super junction column, the shield voltage point of the super junction column depletion to Cgd is dispersed, the mutation of Coss and Cgd can be relieved, and the current and voltage oscillation is reduced.
Drawings
Fig. 1 is a graph showing the variation curve of capacitance Cgd of a common super junction VDMOS with Vds;
fig. 2 is a schematic structural diagram of the super junction power device of embodiment 1;
fig. 3 is a schematic structural diagram of the super junction power device of embodiment 2;
FIGS. 4 to 12 are schematic views of the process flow of the manufacturing method of example 1
The structure comprises a metalized drain 1, a first conductive type semiconductor substrate 2, a first conductive type semiconductor lightly doped region 3, a columnar second conductive type semiconductor 4, a second conductive type semiconductor body region 5, a first conductive type semiconductor 6, a gate oxide layer 7, a polysilicon gate electrode 8, a dielectric layer 9, a metalized source 10 and a second conductive type semiconductor heavily doped contact region 11.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
A super junction power device comprises a metalized drain electrode 1, a first conductive type heavily doped substrate 2, a first conductive type lightly doped epitaxial layer 3 and a metalized source electrode 10 which are sequentially stacked from bottom to top as shown in figure 2; a second conductive type semiconductor column 4 is arranged in the first conductive type lightly doped epitaxial layer 3; a second conductive type semiconductor body region 5 is arranged between the second conductive type semiconductor column 4 and the lower surface of the metalized source electrode 11, a first conductive type semiconductor source region 6 and a second conductive type semiconductor heavily-doped contact region 11 which are mutually independent and contacted are arranged on the upper layer of the second conductive type semiconductor body region 5, the second conductive type semiconductor heavily-doped contact region 11 is positioned between the first conductive type semiconductor source regions 6 at two sides, and the upper surfaces of the first conductive type semiconductor source region 6 and the second conductive type semiconductor heavily-doped contact region 11 are contacted with the metalized source electrode 10; the second conductive type semiconductor body region 5 positioned between the first conductive type semiconductor source region 6 and the first conductive type lightly doped epitaxial layer 3 adjacent to the first conductive type semiconductor source region is a channel region; the upper surface of the first-conductivity-type lightly doped epitaxial layer 3 between two adjacent second-conductivity-type semiconductor columns 4 is provided with a gate structure embedded in the metalized source 11, the gate structure comprises a gate oxide layer 7 and a polysilicon gate 8 positioned on the upper surface of the gate oxide layer 7, and the gate structure extends towards two sides to the upper surfaces of a part of the second-conductivity-type semiconductor body region 5 and a part of the first-conductivity-type semiconductor source region 6; the grid structure is isolated from the metalized source 11 through a dielectric layer 9; the second-conductivity-type semiconductor pillars 4 have at least two different widths, and the spacing between adjacent second-conductivity-type semiconductor pillars 4 has at least two different widths, and the second-conductivity-type semiconductor pillars 4 and the adjacent lightly doped regions of the first conductivity type satisfy the charge balance. The device has two or more of the above-described repeating units.
Fig. 4-12 are schematic process flow diagrams of a method for manufacturing a VDMOS with gradually-changed gate-drain capacitance and super-junction power according to an embodiment of the present invention.
Firstly, as shown in fig. 4, a lightly doped epitaxial layer 3 of the first conductivity type is grown on a heavily doped semiconductor substrate 2 of the first conductivity type by an epitaxial process, and the substrate and the outer oxygen layer are usually made of silicon (Si), wherein the lightly doped epitaxial layer 3 of the first conductivity type has a certain thickness and meets the specific voltage endurance requirement;
a hard mask, typically of silicon nitride (Si), is then formed by chemical vapour deposition on the lightly doped epitaxial layer 3 of the first conductivity type3N4) Then forming a bottom film in a gas phase, rotationally coating photoresist, etching after exposure and development to form a deep groove, and then removing the photoresist and the hard mask through plasma etching, as shown in FIG. 5;
as shown in fig. 6, a P-type epitaxy is grown by an epitaxy process, and a flat silicon wafer with uniform thickness is obtained by a planarization process after the epitaxy growth is completed;
next, as shown in fig. 7, after cleaning, sending the silicon wafer into a high-temperature furnace for field oxidation, rotating to glue, exposing and developing, etching an active region by a dry method, after cleaning, sending the silicon wafer into the high-temperature furnace for dry oxidation to form gate oxide 7, and depositing a polysilicon gate 8 layer with a certain thickness by a chemical vapor deposition process;
as shown in fig. 8, the purpose of this step is to have a second conductivity type semiconductor body region 5 on top of a second conductivity type semiconductor pillar 4, after depositing polysilicon, first cleaning the silicon wafer, then spin-coating, exposing and developing, after developing, etching the polysilicon 8 and the gate oxide layer 7 by a dry method, then injecting second conductivity type ions or such an ionic compound with glue, removing the glue, after cleaning, pushing the junction by high temperature diffusion in a diffusion furnace, activating impurities, and forming the body region 5;
as shown in fig. 9, spin coating, photo-etching, injecting second conductive type ions or the ionic compound with glue, removing glue, cleaning, and then entering a diffusion furnace for high temperature junction-push diffusion to form a second conductive type semiconductor heavily doped region 11;
as shown in fig. 10, spin coating, photo-etching, injecting first conductive type ions or the ionic compound with glue, removing glue, cleaning, and then putting into a diffusion furnace to push junction diffusion at high temperature to form a first conductive type semiconductor heavily doped region 6;
cleaning a silicon wafer, depositing a dielectric layer 9 by chemical vapor deposition, rotationally coating glue, exposing and developing, etching the dielectric layer 9, and refluxing and densifying in a diffusion furnace to form a source contact hole, as shown in fig. 11.
Finally, as shown in fig. 12, the source metal and the cathode metal are formed by metallization through metal sputtering and silicon wafer back thinning processes.
The working principle of the present invention is explained by taking the embodiment 1 as an example.
For the traditional super junction device, because the super junction structure exists in the voltage-proof layer, the pn junction surface in the super junction device is larger. Therefore, when the drain-source voltage Vds is small, the source-drain capacitance value of the super junction VDMOS is large. Since the depletion layer of the super junction column expands in the transverse direction in addition to the longitudinal expansion, the whole column region is completely depleted under a small drain-source voltage Vds, and the space charge region has a shielding effect on the miller capacitance Cgd and the drain-source capacitance Cds at the moment. Due to the traditional super-junction VDMOS, column regions at the same voltage node are completely depleted, so that the phenomenon that the Miller capacitance Cgd and the drain-source capacitance Cds drop suddenly occurs.
The invention introduces a plurality of different PN column widths and intervals, so that the super junction column region is completely depleted at a plurality of different source-drain voltage Vds nodes respectively. Because the super-junction column regions with different widths and different intervals have different depletion degrees under different source-drain voltages Vds, the shielding areas of the depletion regions for the Miller capacitance Cgd and the drain-source capacitance Cds are reduced under a certain source-drain voltage Vds, and the reduction amplitude of the total Miller capacitance Cgd and the total drain-source capacitance Cds of the chip is reduced, so that compared with the traditional super-junction VDMOS, the super-junction column structure can increase the source-drain voltage span of the sudden drop of the Miller capacitance Cgd and the drain-source capacitance Cds, namely reduce the change slope of the Miller capacitance Cgd and the drain-source capacitance Cds. Therefore, the phenomenon that the Miller capacitance Cgd and the drain-source capacitance Cds drop steeply can be effectively relieved by the method. Meanwhile, the second conductive type semiconductor column 4 and the adjacent first conductive type lightly doped region meet the charge balance, so that the withstand voltage of the device is not influenced by the size and the space change of the super junction column.
Example 2
A super junction power device is provided, as shown in FIG. 3, a metalized drain 1, a first conductive type semiconductor substrate 2, a first conductive type lightly doped epitaxial layer 3 and a metalized source 10 are sequentially stacked from bottom to top; the first conductive type lightly doped epitaxial layer 3 is provided with a second conductive type semiconductor column 4; the top of the second conductivity type semiconductor pillar 4 has a second conductivity type semiconductor body region 5; the second conductive type semiconductor body region 5 is provided with a first conductive type semiconductor source region 6 and a second conductive type semiconductor heavily-doped contact region 11, and the second conductive type semiconductor body region 5 between the first conductive type semiconductor 6 and the adjacent first conductive type lightly-doped epitaxial layer 3 is a channel region; the gate oxide layer 7 covers the channel region and the first conductive type lightly doped epitaxial layer 3; the polysilicon gate 8 covers the gate oxide layer 7, and the dielectric layer 9 surrounds the polysilicon gate 8 and the gate oxide layer 7, so that the polysilicon gate 8 is electrically isolated from the metalized source electrode 10. The upper surface of the second conductive type semiconductor heavily doped contact region 11 and part of the upper surface of the first conductive type semiconductor source region 6 are in direct contact with the metalized source 10. The second-conductivity-type semiconductor pillars 4 have two or more different widths (a1, a2 … …, an; n ≧ 2), and the spacing between two adjacent second-conductivity-type semiconductor pillars 4 has two or more different widths (b1, b2 … …, bn; n ≧ 2), the second-conductivity-type semiconductor pillars 4 and the spacing thereof are arranged in a manner of a1, b1, a1, b1.
Claims (3)
1. A super junction power device comprises a metalized drain electrode (1), a first conductive type heavily doped substrate (2), a first conductive type lightly doped epitaxial layer (3) and a metalized source electrode (10) which are sequentially stacked from bottom to top; the first conductive type lightly doped epitaxial layer (3) is provided with a second conductive type semiconductor column (4); a second conductive type semiconductor body region (5) is arranged between the second conductive type semiconductor column (4) and the lower surface of the metalized source electrode (11), a first conductive type semiconductor source region (6) and a second conductive type semiconductor heavily-doped contact region (11) which are independent from and contact with each other are arranged on the upper layer of the second conductive type semiconductor body region (5), the second conductive type semiconductor heavily-doped contact region (11) is positioned between the first conductive type semiconductor source regions (6) on two sides, and the upper surfaces of the first conductive type semiconductor source region (6) and the second conductive type semiconductor heavily-doped contact region (11) are in contact with the metalized source electrode (10); a second conductive type semiconductor body region (5) positioned between the first conductive type semiconductor source region (6) and the first conductive type lightly doped epitaxial layer (3) adjacent to the first conductive type semiconductor source region is a channel region; the upper surface of the first-conductivity-type lightly-doped epitaxial layer (3) between two adjacent second-conductivity-type semiconductor columns (4) is provided with a gate structure embedded in a metalized source electrode (11), the gate structure comprises a gate oxide layer (7) and a polysilicon gate (8) positioned on the upper surface of the gate oxide layer (7), and the gate structure extends towards two sides to the upper surfaces of a part of the second-conductivity-type semiconductor body region (5) and a part of the first-conductivity-type semiconductor source region (6); the grid structure is isolated from the metalized source electrode (11) through a dielectric layer (9); the second-conductivity-type semiconductor columns (4) have at least two different widths, the spacing between adjacent second-conductivity-type semiconductor columns (4) has at least two different widths, and the second-conductivity-type semiconductor columns (4) and the adjacent first-conductivity-type lightly doped regions meet the charge balance.
2. The super junction power device according to claim 1, wherein said first conductivity type semiconductor is an n-type semiconductor, and said second conductivity type semiconductor is a p-type semiconductor; or the first conductivity type semiconductor is a P-type semiconductor and the second conductivity type semiconductor is an n-type semiconductor.
3. The super junction power device according to claim 1, wherein the gate oxide layer (7) is made of silicon oxide, silicon nitride, silicon oxynitride, lead oxide or high dielectric constant insulating material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710665471.8A CN107464837B (en) | 2017-08-07 | 2017-08-07 | Super junction power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710665471.8A CN107464837B (en) | 2017-08-07 | 2017-08-07 | Super junction power device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107464837A CN107464837A (en) | 2017-12-12 |
| CN107464837B true CN107464837B (en) | 2020-07-31 |
Family
ID=60547352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710665471.8A Active CN107464837B (en) | 2017-08-07 | 2017-08-07 | Super junction power device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107464837B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019204829A1 (en) * | 2018-04-20 | 2019-10-24 | Hamza Yilmaz | Small pitch super junction mosfet structure and method |
| CN115513275A (en) * | 2021-06-07 | 2022-12-23 | 华润微电子（重庆）有限公司 | Super junction MOSFET device |
| CN115881791A (en) * | 2021-09-26 | 2023-03-31 | 苏州东微半导体股份有限公司 | Semiconductor super junction power device |
| CN116137283A (en) * | 2021-11-17 | 2023-05-19 | 苏州东微半导体股份有限公司 | Semiconductor super junction power device |
| CN116137289A (en) * | 2021-11-17 | 2023-05-19 | 苏州东微半导体股份有限公司 | Semiconductor super junction power device |
| CN116137282A (en) * | 2021-11-17 | 2023-05-19 | 苏州东微半导体股份有限公司 | Semiconductor super junction power device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5438215A (en) * | 1993-03-25 | 1995-08-01 | Siemens Aktiengesellschaft | Power MOSFET |
| JP2004146689A (en) * | 2002-10-25 | 2004-05-20 | Fuji Electric Device Technology Co Ltd | Super junction semiconductor element |
| CN102468337A (en) * | 2010-11-09 | 2012-05-23 | 富士电机株式会社 | Semiconductor device |
| CN104638004A (en) * | 2013-11-15 | 2015-05-20 | 上海华虹宏力半导体制造有限公司 | Super-junction MOSFET (metal-oxide-semiconductor field-effect transistor) device structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4645705B2 (en) * | 2008-08-29 | 2011-03-09 | ソニー株式会社 | Semiconductor device and manufacturing method of semiconductor device |
-
2017
- 2017-08-07 CN CN201710665471.8A patent/CN107464837B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5438215A (en) * | 1993-03-25 | 1995-08-01 | Siemens Aktiengesellschaft | Power MOSFET |
| JP2004146689A (en) * | 2002-10-25 | 2004-05-20 | Fuji Electric Device Technology Co Ltd | Super junction semiconductor element |
| CN102468337A (en) * | 2010-11-09 | 2012-05-23 | 富士电机株式会社 | Semiconductor device |
| CN104638004A (en) * | 2013-11-15 | 2015-05-20 | 上海华虹宏力半导体制造有限公司 | Super-junction MOSFET (metal-oxide-semiconductor field-effect transistor) device structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107464837A (en) | 2017-12-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107464837B (en) | Super junction power device | |
| US8829608B2 (en) | Semiconductor device | |
| TWI544648B (en) | Planar srfet using no additional masks and layout method | |
| US11652166B2 (en) | Power device having super junction and Schottky diode | |
| US9324855B2 (en) | Lateral power device having low specific on-resistance and using high-dielectric constant socket structure and manufacturing method therefor | |
| JP2004537162A (en) | Power device and its manufacturing method | |
| CN103928516A (en) | Semiconductor device having dual parallel channel structure and method of fabricating the same | |
| US11888022B2 (en) | SOI lateral homogenization field high voltage power semiconductor device, manufacturing method and application thereof | |
| EP3089216A1 (en) | Split-gate power semiconductor field-effect transistor | |
| US20190013383A1 (en) | Silicon carbide mosfet device and method for manufacturing the same | |
| CN111799322B (en) | Double-groove type SiC MOSFET structure for high-frequency application and manufacturing method | |
| CN113851523B (en) | Shielding gate MOSFET and manufacturing method thereof | |
| CN102290434B (en) | Metal-semiconductor field effect transistor with under-grid buffer layer structure and manufacturing method | |
| CN114664934B (en) | DMOS transistor with field plate and manufacturing method thereof | |
| CN114975126B (en) | Manufacturing method of shielded gate trench type MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of reducing gate charges | |
| US10355132B2 (en) | Power MOSFETs with superior high frequency figure-of-merit | |
| CN112164725B (en) | High-threshold power semiconductor device and manufacturing method thereof | |
| CN113241381A (en) | Novel high-voltage groove grid MOS device and preparation method thereof | |
| CN111969055A (en) | GaN high electron mobility transistor structure and manufacturing method thereof | |
| US20060160320A1 (en) | Method of fabricating a semiconductor device | |
| CN113130635B (en) | MOS device of I-type gate and preparation method thereof | |
| CN216288470U (en) | Shielding gate MOSFET | |
| CN116435335B (en) | Groove type MOSFET electric field shielding protection structure and preparation method | |
| CN219435880U (en) | Trench MOSFET transistor | |
| CN107895738A (en) | A kind of trap locally highly doped MOS type device and preparation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |