CN104638004A

CN104638004A - Super-junction MOSFET (metal-oxide-semiconductor field-effect transistor) device structure

Info

Publication number: CN104638004A
Application number: CN201310574061.4A
Authority: CN
Inventors: 刘继全
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2013-11-15
Filing date: 2013-11-15
Publication date: 2015-05-20
Anticipated expiration: 2033-11-15
Also published as: CN104638004B

Abstract

The invention discloses a super-junction MOSFET (metal-oxide-semiconductor field-effect transistor) device structure. The width ratio of a first semiconductor layer of an active region to a second semiconductor layer of the active region is S1, the width ratio of a first semiconductor layer of a terminal region to a second semiconductor layer of the terminal region is S2, the doping concentration of the first semiconductor layers of the active region and the terminal region is m, the doping concentration of the second semiconductor layers of the active region and the terminal region is n, and conditions that 0<1-S1m/n<=0.1 and -0.1<=1-S2m/n<0 or -0.1<=1-S1m/n<0 and 0<1-S2m/n<=0.1 are satisfied. The super-junction MOSFET device structure has the advantages that the width ratios and the doping concentration of the first semiconductor layers and the second semiconductor layers of the active region and the terminal region are designed reasonably, so that puncture voltages of the active region and the terminal region are distributed within a certain difference range, polar difference of the puncture voltages is decreased, and consistency between uniformity of the puncture voltages and the super-junction MOSFET device is improved.

Description

The structure of super junction MOSFET element

Technical field

The present invention relates to IC manufacturing field, particularly relate to the structure of super junction MOSFET element.

Background technology

VDMOSFET(vertical double-diffused MOS transistor) thickness of thinning drain terminal drift region can be adopted to reduce conducting resistance, but, the thickness of thinning drain terminal drift region will reduce the puncture voltage of device, therefore, in VDMOS, the puncture voltage improving device is conflict with the conducting resistance reducing device.

Super junction MOSFET have employed new structure of voltage-sustaining layer, utilize a series of P type of being alternately arranged and N type semiconductor thin layer, under lower reverse voltage, P type, N-type region are exhausted, realize electric charge mutually to compensate, thus make P type, N-type region can realize high puncture voltage under high-dopant concentration, so just can obtain low on-resistance and high-breakdown-voltage, the theoretical limit of the power MOSFET that breaks traditions simultaneously.

But the stability of the doping content of super junction MOSFET controls more difficult.Under normal circumstances, the active area of device and the P/N width of termination environment are than consistent, the breakdown voltage distribution also consistent (see figure 1) of active area and termination environment, the puncture voltage of device depends on the puncture voltage of one of them, be t3 to t1, this causes the fluctuation ratio of puncture voltage comparatively large, the less stable of device.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of structure of super junction MOSFET element, and it can improve the uniformity of puncture voltage, reduces the extreme difference of puncture voltage.

For solving the problems of the technologies described above, the structure of super junction MOSFET element of the present invention, the width of its active area first semiconductor layer and the second semiconductor layer, satisfies condition than the second semiconductor layer doped concentration n of the first semiconductor layer doped concentration m of S2, active area and termination environment, active area and termination environment than the width of S1, termination environment first semiconductor layer and the second semiconductor layer: 0<1-S1m/n≤0.1 and-0.1≤1-S2m/n<0; Or-0.1≤1-S1m/n<0 and 0<1-S2m/n≤0.1.

The present invention is by carrying out reasonable design to the first semiconductor layer of active area and termination environment and the width ratio of the second semiconductor layer and doping content ratio, make the breakdown voltage distribution of active area and the breakdown voltage distribution of termination environment in certain disparity range, reduce the extreme difference of puncture voltage, improve the uniformity of puncture voltage and the consistency of super junction MOSFET element.

Accompanying drawing explanation

Fig. 1 is active area and the termination environment breakdown voltage distribution figure of conventional Super junction structure.

Fig. 2-5 is formation process schematic flow sheets of the super-junction structures of the embodiment of the present invention.Wherein, Fig. 5 is the schematic cross-section of the super-junction structures that the embodiment of the present invention makes.

Fig. 6 is active area and the termination environment breakdown voltage distribution curve chart of the super-junction structures of the embodiment of the present invention.

In figure, description of reference numerals is as follows:

1: semiconductor base

2: the first semiconductor layers

3: the second semiconductor layers

4: the first electrodes

5: the second electrodes

6: source area

7: base region

8: before-metal medium layer

9: grid

10: gate dielectric layer

Embodiment

Understand more specifically for having technology contents of the present invention, feature and effect, now in conjunction with illustrated execution mode, details are as follows:

Refer to shown in Fig. 2-5, super junction MOSFET element of the present invention, its concrete manufacturing process steps is:

Step 1, grows the first semiconductor layer that a layer thickness is 10 ~ 100 microns on a semiconductor substrate, as shown in Figure 2, and grows a layer dielectric (not shown in FIG.) on the first semiconductor layer.

First semiconductor layer and semiconductor base have the first doping type.Typical first semiconductor layer is N-type silicon epitaxy layer, and typical semiconductor base is N-type silicon base.The doping content of the first semiconductor layer is set as m.The carrier concentration of semiconductor base is greater than the first semiconductor layer.

Deielectric-coating is at least one in silica, silicon nitride or silicon oxynitride.

Step 2, with photoetching and dry etching method, etches groove in the first semiconductor layer inside, as shown in Figure 3.

The width of groove is 1.0 ~ 10 microns, and the degree of depth is 8 ~ 90 microns, and spacing is 1.0 ~ 20 microns.

Groove is distributed in active area and termination environment.Active area can be identical with the degree of depth with the width of the groove of termination environment, also can be different, but groove pitch is not identical.The spacing of the groove of active area and the ratio of the width of groove are set as S1 by us, and the spacing of termination environment groove and the ratio of the width of groove are set as S2.

Step 3, fills the second semiconductor layer with selective silicon epitaxy technique at trench interiors, then carries out planarization with chemical mechanical milling tech to groove top, as shown in Figure 4.

Second semiconductor layer has the second doping type, and (first, second doping type is contrary, and such as the first doping type is N-type, then the second doping type is P type; First doping type is P type, then the second doping type is N-type).Typical second semiconductor layer is P-type silicon epitaxial loayer.The doping content of the second semiconductor layer is set as n.

Step 4, forms the thinning and back side first electrode formation of base region, source area, gate dielectric layer, grid, before-metal medium layer, the second electrode, semiconductor base etc. by conventional MOSFET technique, as shown in Figure 5.

In order to obtain good BV uniformity, reduce the extreme difference of device, the present invention to active area and the first semiconductor layer of termination environment and the width ratio (S1, S2) of the second semiconductor layer and doping content (m, n) to design, S1, S2, m, n demand fulfillment:

0<1-S1m/n≤0.1, and-0.1≤1-S2m/n<0;

Or-0.1≤1-S1m/n<0, and 0<1-S2m/n≤0.1.

The derivation of above-mentioned formula is as follows:

In setting Fig. 5, the width of spaced first semiconductor layer in active area and the second semiconductor layer is respectively a1 and b1, and the width of spaced first semiconductor layer in termination environment and the second semiconductor layer is respectively a2 and b2, then:

S1=a1/b1

S2=a2/b2

When the ratio that the difference of the charge carrier total amount of the first semiconductor layer and the second semiconductor layer accounts for the second semiconductor layer charge carrier total amount is within ± 10%, puncture voltage change not obvious, but when this ratio exceed ± 10% time, BV declines rapidly, therefore, this ratio should control within ± 10%.Can release thus:

0< (nb1-ma1)/nb1≤0.1(active area)

And-0.1≤(nb2-ma2)/nb2<0(termination environment)

Or

-0.1≤(nb1-ma1)/nb1<0(active area)

And 0< (nb2-ma2)/nb2≤0.1(termination environment)

That is:

0<1-S1m/n≤0.1 and-0.1≤1-S2m/n<0; Or-0.1≤1-S1m/n<0 and 0<1-S2m/n≤0.1.

Like this, by carrying out reasonable design to the first semiconductor layer of active area and termination environment and the width ratio of the second semiconductor layer and doping content ratio, just can make the breakdown voltage distribution of active area and the breakdown voltage distribution of termination environment in certain disparity range, as P(N) carrier concentration of post is when changing within the specific limits (as changed between X1-X2 in Fig. 6), the peak of puncture voltage is exactly the joining of two curves, minimum point is exactly the value of a certain bar curve when X1 or X2 (minimum of the puncture voltage of active area or termination environment), namely the fluctuation range of puncture voltage is t2 to t1.Clearly, t3-t1>t2-t1, therefore, compares the structure of conventional MOS FET, and super junction MOSFET element structure of the present invention can obviously reduce BV(puncture voltage) excursion, improve the consistency of device.

Claims

1. the structure of super junction MOSFET element, it is characterized in that, active area first semiconductor layer of this super junction MOSFET and the width of the second semiconductor layer, satisfy condition than the doping content n of the doping content m of S2, active area and termination environment first semiconductor layer, active area and termination environment second semiconductor layer than the width of S1, termination environment first semiconductor layer and the second semiconductor layer: 0<1-S1m/n≤0.1 and-0.1≤1-S2m/n<0; Or-0.1≤1-S1m/n<0 and 0<1-S2m/n≤0.1.