CN108110057B - Super junction metal oxide field effect transistor - Google Patents
Super junction metal oxide field effect transistor Download PDFInfo
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- CN108110057B CN108110057B CN201711328190.XA CN201711328190A CN108110057B CN 108110057 B CN108110057 B CN 108110057B CN 201711328190 A CN201711328190 A CN 201711328190A CN 108110057 B CN108110057 B CN 108110057B
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- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 21
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 21
- 230000005669 field effect Effects 0.000 title abstract description 18
- 230000007704 transition Effects 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 150000002500 ions Chemical class 0.000 claims description 29
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 230000005684 electric field Effects 0.000 description 8
- 230000007423 decrease Effects 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 210000000746 body region Anatomy 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 210000003850 cellular structure Anatomy 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000001727 in vivo Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a super junction metal oxide field effect transistor. The transistor is divided into an active region and a voltage-resistant region located on the periphery of the active region, the voltage-resistant region is divided into a transition region adjacent to the active region and a terminal region located on the periphery of the transition region, the transistor further comprises an N-type substrate, an N-type epitaxial layer located on the N-type substrate, a P-type doped junction located on the surface of the N-type epitaxial layer of the voltage-resistant region, a first P-type doped region located in the N-type epitaxial layer of the transition region, connected with the bottom of the P-type doped junction and extending towards the N-type substrate, and a second P-type doped region located in the N-type epitaxial layer below the P-type doped junction of the terminal region and extending along the direction parallel to the N-type substrate.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of semiconductor devices, in particular to a super junction metal oxide field effect transistor.
[ background of the invention ]
The super junction metal oxide field effect transistor is a novel device which has the advantages of an insulated gate structure of a metal oxide semiconductor transistor and has the advantages of high current density and low on resistance, and is a power semiconductor device which can be used for effectively reducing the conduction loss of the traditional power metal oxide semiconductor field effect transistor. It is a charge compensation device based on the charge balance principle.
The basic feature of a super junction mosfet is that it is voltage-tolerant with a drift region formed by spaced N-and P-doped regions. When a traditional high-voltage metal oxide field effect transistor device bears reverse high voltage, the voltage resistance is realized mainly by longitudinal depletion of a PN junction, and an electric field intensity peak value appears at the PN junction boundary of the whole device. And because of introducing the charge compensation mechanism, the super junction metal oxide field effect transistor has more uniform electric field distribution when the super junction metal oxide field effect transistor is used up and withstand voltage, and compared with the triangular peak electric field distribution of the traditional high-voltage metal oxide field effect transistor device, the super junction metal oxide field effect transistor has rectangular electric field distribution in the longitudinal withstand voltage direction. So that the whole device does not have individual electric field peak value in the process of depletion voltage resistance. Since the P-type region is inserted in the vertical direction, excessive current-conducted charges can be compensated. Applying a reverse bias voltage to the drift layer will generate a lateral electric field to deplete the PN junction. When the voltage reaches a certain value, the drift layer is completely exhausted, and the function of a voltage supporting layer is realized. The withstand voltage of the device in the vertical direction can be made high. However, device breakdown usually occurs at the termination, and for the conventional power device termination, a drift layer with a lower concentration is used inside the bulk silicon to ensure the voltage withstanding level, but because the super junction device has a special active region structure (also called a cellular structure), the drift region has a higher concentration, the drift layer has a smaller thickness, and the termination structure of the common high-voltage power device is not suitable for the super junction device, so how to improve the performance (such as voltage withstanding performance) of the termination region of the super junction device becomes an important issue.
[ summary of the invention ]
One of the objects of the present invention is to provide a super junction metal oxide field effect transistor to solve the above problems.
The transistor further comprises an N-type substrate, an N-type epitaxial layer positioned on the N-type substrate, a P-type doped junction positioned on the surface of the N-type epitaxial layer of the voltage-resistant region, a first P-type doped region positioned in the N-type epitaxial layer of the transition region, connected with the bottom of the P-type doped junction and extending towards the N-type substrate, and a second P-type doped region positioned in the N-type epitaxial layer below the P-type doped junction of the terminal region and extending along the direction parallel to the N-type substrate.
In one embodiment, the number of the first P-type doped regions is multiple, and the multiple first P-type doped regions are all connected to the P-type doped junction.
In one embodiment, the P-type ion concentration of the first P-type doped regions is gradually decreased along a direction away from the active region.
In one embodiment, in the plurality of first P-type doped regions, the distance between two adjacent first P-type doped regions gradually increases along a direction away from the active region.
In one embodiment, the active region includes a third P-type doped region, and the P-type ion concentration of the first P-type doped region adjacent to the active region is greater than the P-type ion concentration of the third P-type doped region.
In one embodiment, the number of the second P-type doped regions is multiple, the multiple second P-type doped regions all extend along a direction parallel to the P-type substrate, and the extension lengths of the multiple second P-type doped regions gradually decrease along a direction away from the P-type doped junction.
In one embodiment, the concentration of P-type ions in the second P-type doped region with the longest extension length is less than the concentration of P-type ions in the first P-type doped region with the smallest concentration of P-type ions in the first P-type doped regions.
In one embodiment, the P-type ion concentrations of the second P-type doped regions are equal, and the distance between any two adjacent second P-type doped regions in the second P-type doped regions is equal.
In one embodiment, the P-type ion concentration of the second P-type doped regions gradually decreases along a direction away from the P-type doped junction, and the distance between two adjacent second P-type doped regions among the second P-type doped regions gradually increases along the direction away from the P-type doped junction.
In one embodiment, the transistor further includes a thick oxygen layer disposed above the P-type doped junction, the thick oxygen layer extending from an edge of the withstand voltage region away from the active region to an edge of a first P-type doped region of the transition region adjacent to the active region near the termination region.
Compared with the prior art, the super-junction metal oxide field effect transistor provided by the invention has the advantages that on the basis of the traditional structure, the voltage-resistant area is divided into two parts: the transition region and the voltage-resistant region are respectively provided with a longitudinal voltage resistance and a transverse voltage resistance, specifically, the transition region is of a longitudinal voltage-resistant structure, and transverse P-type columns and N-type columns of the terminal region are alternately arranged to form a transverse voltage-resistant structure, so that the voltage resistance of the super-junction metal oxide field effect transistor is improved.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
fig. 1 is a schematic cross-sectional view of a super junction mosfet according to a preferred embodiment of the present invention.
[ detailed description ] embodiments
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a super junction mosfet according to a preferred embodiment of the invention. The super junction metal oxide field effect transistor is divided into an active area and a voltage-resistant area positioned on the periphery of the active area, the voltage-resistant region divides a transition region adjacent to the active region and a termination region located at the periphery of the transition region, the transistor further comprises an N-type substrate, an N-type epitaxial layer located on the N-type substrate, a P-type doped junction located on the surface of the N-type epitaxial layer of the pressure-resistant region, a first P-type doped region located in the N-type epitaxial layer of the transition region, connected with the bottom of the P-type doped junction and extending towards the N-type substrate, a second P-type doped region located in the N-type epitaxial layer below the P-type doped junction of the terminal region and extending along the direction parallel to the N-type substrate, a thick oxygen layer arranged above the P-type doped junction, a P-type body region located in the active region, polycrystalline silicon and a silicon oxide layer stacked with the polycrystalline silicon.
The first P-type doped region, the second P-type doped region and the third P-type doped region may be P-type highly doped regions. The P-type doped junction and the P-type body region may be P-type low doped regions. The surface of the P type body region can also be provided with an N type doped region.
Further, in this embodiment, the number of the first P-type doped regions is multiple, and the multiple first P-type doped regions are all connected to the P-type doped junction. The P-type ion concentration of the first P-type doped regions is gradually reduced along the direction far away from the active region. The distance between two adjacent first P-type doped regions is gradually increased along the direction far away from the active region. The active region may include a third P-type doped region, and a P-type ion concentration of the first P-type doped region adjacent to the active region is greater than a P-type ion concentration of the third P-type doped region.
Furthermore, the number of the second P-type doped regions is multiple, the second P-type doped regions extend along a direction parallel to the P-type substrate, and the extension lengths of the second P-type doped regions are gradually reduced along a direction away from the P-type doped junction.
In one embodiment, the concentration of P-type ions in the second P-type doped region with the longest extension length is less than the concentration of P-type ions in the first P-type doped region with the smallest concentration of P-type ions in the first P-type doped regions.
In one embodiment, the P-type ion concentrations of the second P-type doped regions are equal, and the distances between any two adjacent second P-type doped regions in the second P-type doped regions are equal.
In one embodiment, the P-type ion concentration of the second P-type doped regions gradually decreases along a direction away from the P-type doped junction, and the distance between two adjacent second P-type doped regions among the second P-type doped regions gradually increases along the direction away from the P-type doped junction.
In addition, the thick oxygen layer extends from the edge of the voltage-resistant region far away from the active region to one side edge of the first P-type doped region of the transition region close to the active region, wherein the one side edge is close to the terminal region.
On the basis of the traditional structure, the super-junction metal oxide field effect transistor divides a voltage-resistant area into two parts: the transition region and the voltage-resistant region are respectively provided with a longitudinal voltage resistance and a transverse voltage resistance, specifically, the transition region is of a longitudinal voltage-resistant structure, and transverse P-type columns and N-type columns of the terminal region are alternately arranged to form a transverse voltage-resistant structure, so that the voltage resistance of the super-junction metal oxide field effect transistor is improved. Meanwhile, the structure gives consideration to the manufacturing process of the traditional super junction device, the longitudinal voltage-resistant structure and the transverse voltage-resistant structure can be formed in a mode of multiple times of epitaxy and injection, and extra manufacturing cost cannot be increased.
Specifically, for the transition region, vertically arranged first P-type doped regions are adopted, the number of the first P-type doped regions can be determined according to the withstand voltage requirement of the device, and the higher the withstand voltage requirement is, the more the number of the first P-type doped regions is. Optionally, the concentration of P-type ions in the first P-type doped region may gradually decrease from left to right (the left side is the direction of the device active region, and the right side is the direction of the device termination region). The concentration of the P-type ions in the leftmost first P-type doped region is higher than that in the third P-type doped region in the active region of the device. Furthermore, the distance between the first P-type doped regions in the transition region can be gradually increased from left to right, so that a longitudinal electric field can be better alleviated, and the electric field intensity in the terminal region body can be reduced.
And aiming at the terminal region, second P-type doped regions which are transversely arranged are adopted, the length of each second P-type doped region is gradually shortened from top to bottom, the length of the uppermost second P-type doped region is determined according to the voltage-resistant requirement of the device, and the higher the voltage-resistant requirement is, the longer the length of each second P-type doped region is. Meanwhile, the concentration of the P-type ions of the second P-type doped region at the top is less than that of the first P-type doped region at the rightmost side of the transition region. Preventing in-vivo voltage spikes caused by concentration mismatches in the transition and termination regions. Furthermore, the concentration of P-type ions in the second P-type doped regions of the plurality of P-type columns arranged transversely can be kept consistent, and if the concentration of P-type ions is consistent, the distance between the second P-type doped regions arranged transversely also needs to be consistent, so that the charge mismatch is prevented. Optionally, in the second P-type doped regions arranged laterally, the concentration of P-type ions may gradually decrease from top to bottom, and the distance may gradually increase from top to bottom.
In addition, the surface of the whole terminal (including the transition region and the terminal region) is covered by the P-type doped junction, so that the surface leakage of the device in reverse bias is greatly reduced, and the performance of the device is improved. A thick oxygen layer is arranged above the P-type doped junction, so that the influence of external charges on the surface of the terminal is prevented, meanwhile, the influence of other technical processes of the device on the terminal can be prevented, and the stability of the terminal is improved.
In addition, the super-junction metal oxide field effect transistor with the structure can greatly reduce the terminal size of the device and reduce the cost of the device. Meanwhile, the stability of the terminal can be improved, and the voltage resistance of the device can be improved.
While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.
Claims (2)
1. A super junction metal oxide transistor, characterized by: the transistor is divided into an active region and a voltage-withstanding region positioned at the periphery of the active region, the voltage-withstanding region is divided into a transition region adjacent to the active region and a terminal region positioned at the periphery of the transition region, the transistor further comprises an N-type substrate, an N-type epitaxial layer positioned on the N-type substrate, a P-type doped junction positioned on the surface of the N-type epitaxial layer of the voltage-withstanding region, a first P-type doped region positioned in the N-type epitaxial layer of the transition region, connected with the bottom of the P-type doped junction and extending towards the N-type substrate, and a second P-type doped region positioned below the P-type doped junction of the terminal region and extending along the direction parallel to the N-type substrate; the number of the first P-type doped regions is multiple, and the multiple first P-type doped regions are connected with the P-type doped junctions; the number of the second P-type doped regions is multiple, the second P-type doped regions extend along a direction parallel to the N-type substrate, and the extension lengths of the second P-type doped regions are gradually reduced along a direction far away from the P-type doped junction; in the plurality of first P-type doped regions, the distance between two adjacent first P-type doped regions is gradually increased along the direction far away from the active region; the active region comprises a third P-type doped region, and the concentration of P-type ions of the first P-type doped region adjacent to the active region is greater than that of the third P-type doped region; the transistor further comprises a thick oxygen layer arranged above the P-type doped junction, wherein the thick oxygen layer extends from the edge of the pressure-resistant region far away from the active region to one side edge of a first P-type doped region of the transition region close to the active region, which is close to the terminal region; the P-type ion concentration of the first P-type doped regions is gradually reduced along the direction far away from the active region; the concentration of the P-type ions of the second P-type doped region with the longest extension length in the plurality of second P-type doped regions is less than that of the P-type ions of the first P-type doped region with the smallest concentration of the P-type ions in the plurality of first P-type doped regions; the P-type ion concentration of the second P-type doped regions is gradually reduced along the direction far away from the P-type doped junction, and the distance between two adjacent second P-type doped regions in the second P-type doped regions is gradually increased along the direction far away from the P-type doped junction.
2. The superjunction metal oxide transistor of claim 1, wherein: the second P-type doped regions have the same P-type ion concentration, and the distance between any two adjacent second P-type doped regions in the second P-type doped regions is equal.
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| CN112687729A (en) * | 2021-03-17 | 2021-04-20 | 中芯集成电路制造(绍兴)有限公司 | Terminal structure of power device |
| CN113078206A (en) * | 2021-03-30 | 2021-07-06 | 电子科技大学 | Power semiconductor device |
| CN114050182A (en) * | 2022-01-17 | 2022-02-15 | 深圳市创芯微微电子有限公司 | Super junction power device and terminal structure and manufacturing method thereof |
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| CN101510561A (en) * | 2009-03-30 | 2009-08-19 | 东南大学 | Ultra-junction longitudinal bilateral diffusion metal oxide semiconductor tube |
| CN104009072A (en) * | 2013-02-25 | 2014-08-27 | 中国科学院微电子研究所 | Insulated gate bipolar transistor and manufacturing method |
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| JP4788028B2 (en) * | 2000-08-28 | 2011-10-05 | 富士電機株式会社 | Bidirectional IGBT with reverse blocking IGBTs connected in antiparallel |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101510561A (en) * | 2009-03-30 | 2009-08-19 | 东南大学 | Ultra-junction longitudinal bilateral diffusion metal oxide semiconductor tube |
| CN104009072A (en) * | 2013-02-25 | 2014-08-27 | 中国科学院微电子研究所 | Insulated gate bipolar transistor and manufacturing method |
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