CN107464837A - A kind of super junction power device - Google Patents
A kind of super junction power device Download PDFInfo
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- CN107464837A CN107464837A CN201710665471.8A CN201710665471A CN107464837A CN 107464837 A CN107464837 A CN 107464837A CN 201710665471 A CN201710665471 A CN 201710665471A CN 107464837 A CN107464837 A CN 107464837A
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- 229910052710 silicon Inorganic materials 0.000 claims description 5
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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Abstract
The present invention relates to power semiconductor device technology field, and in particular to a kind of super junction power device.A kind of super junction power device provided by the invention, the second conductive type semiconductor post in its first conductive type semiconductor drift region have two or more different in width (a1, a2 ..., an；N >=2), and the spacing between the two neighboring second conductive type semiconductor post has two or more different in width (b1, b2 ..., bm；M >=2), because the superjunction post of different in width and spacing exhausts corresponding drain-source voltage point difference, the source-drain voltage span of miller capacitance Cgd and drain source capacitance Cds rapid drawdowns is thus added, Cgd and Coss dip is alleviated, reduces the concussion of Current Voltage.
Description
Technical field
The present invention relates to power semiconductor device technology field, and in particular to a kind of super junction power device.
Background technology
Capacitance characteristic is switched on and off that process is most important for power DMOS device, influences whether the switch speed of device
Degree and EMI (Electromagnetic Interference) characteristic.Hyperconjugation VDMOS is due to the drift region with conventional VDMOS
The difference of structure, there is also difference for its capacitance characteristic：The output capacitance (Coss) and miller capacitance (Cgd) curve of hyperconjugation VDMOS
The non-linear relation of height can be presented with the increase of drain-source voltage.Because cell density is higher, the Coss of hyperconjugation VDMOS is initial
Value is higher, and steep drop can occur near specific drain-source voltage in Coss and Cgd, as shown in figure 1, its reason is at this voltage
N posts are completely depleted, and the area for being equivalent to Coss and Cgd reduces.When hyperconjugation VDMOS is applied to PFC or DC/DC converters,
The steep drop phenomenon of electric capacity may cause voltage and current to vibrate, and produce EMI noise.
The gradual super junction power device of a kind of gate leakage capacitance that patent CN 104952928 is provided, is characterized in that body area has
Two or more unequal width, there is two or more unequal spacing between adjacent body area, will be super
Tie gate leakage capacitance mutation of the power device when being switched on or off and share multiple voltage nodes, dashed forward so as to reduce by gate leakage capacitance
Electromagnetic interference caused by change.But drop causes superjunction devices Cgd mainly due to mutually exhausting for PN posts suddenly, rather than adjacent body
JFET areas between area, which exhaust, to cause, therefore the program only changes the spacing in body area, and can not function well as makes Cgd gradual
Effect.
The content of the invention
The present invention is not influenceing the pressure-resistant premise of device in view of the above-mentioned problems, provide a kind of superjunction power VDMOSFET device
Under, improve the Cgd and Coss of hyperconjugation VDMOS with the increased steep drop problem of drain-source voltage, improve the capacitance characteristic of device.
The technical solution adopted in the present invention：A kind of super junction power device, be cascading metallization leakage from bottom to up
Pole 1, the first conductive type semiconductor substrate 2, the first conduction type lightly doped epitaxial layer 3 and metallizing source 10；Described first
There is the second conductive type semiconductor post 4 in conduction type lightly doped epitaxial layer 3；The second conductive type semiconductor post 4
Top has the second conductive type semiconductor body area 5；There is the first conduction type in the second conductive type semiconductor body area 5
The conductive type semiconductor heavy doping contact zone 11 of semiconductor source region 6 and second, first conductive type semiconductor 6 with it is adjacent
The second conductive type semiconductor body area 5 between first conduction type lightly doped epitaxial layer 3 is channel region；Grid oxide layer 7 is covered in
On the channel region and the first conduction type lightly doped epitaxial layer 3；Polysilicon gate 8 is covered on the grid oxide layer 7, dielectric layer 9
The polysilicon gate 8 and grid oxide layer 7 are surrounded, realizes the electrical isolation of the polysilicon gate 8 and metallizing source 10.Described second
The portion of upper surface of the upper surface of conductive type semiconductor heavy doping contact zone 11 and the first conductive type semiconductor source region 6 and gold
Categoryization source electrode 10 directly contacts.Characterized in that, the second conductive type semiconductor post 4 has two or more difference
Width (a1, a2 ..., an；N >=2), and the spacing between the two neighboring second conductive type semiconductor post 4 have two kinds or
Two or more different in width (b1, b2 ..., bm；M >=2), and the second conductive type semiconductor post 4 it is adjacent
One conduction type lightly doped region meets charge balance.
Beneficial effects of the present invention are：Hyperconjugation VDMOS is obtained near drain-source voltage specific, and Coss and Cgd can decline rapidly,
Voltage and current may be caused to vibrate.The vibration may cause grid source breakdown, bad EMI, larger switching loss, grid control
Failure, in some instances it may even be possible to cause device fault.By changing the width and spacing of superjunction post, superjunction post is set to exhaust the shielding to Cgd
Electrical voltage point disperses, and can alleviate Coss and Cgd mutation, reduces the concussion of Current Voltage.
Brief description of the drawings
Fig. 1 is the electric capacity Cgd of common hyperconjugation VDMOS with Vds change curve schematic diagram；
Fig. 2 is the structural representation of the super junction power device of embodiment 1；
Fig. 3 is the structural representation of the super junction power device of embodiment 2；
Fig. 4-Figure 12 is the manufacturing approach craft schematic flow sheet of embodiment 1
1 is metalized drain, and 2 be the first conductive type semiconductor substrate, and 3 be that the first conductive type semiconductor is lightly doped
Area, 4 be the conductive type semiconductor of column second, and 5 be the second conductive type semiconductor body area, and 6 be the first conductive type semiconductor,
7 be grid oxide layer, and 8 be polygate electrodes, and 9 be dielectric layer, and 10 be metallizing source, and 11 be that the second conductive type semiconductor is heavily doped
Miscellaneous contact zone.
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Embodiment 1
A kind of super junction power device, as shown in Fig. 2 including the metalized drain 1, first being cascading from bottom to up
Conduction type heavy doping substrate 2, the first conduction type lightly doped epitaxial layer 3 and metallizing source 10；First conduction type
Has the second conductive type semiconductor post 4 in lightly doped epitaxial layer 3；The second conductive type semiconductor post 4 and metallizing source
There is the second conductive type semiconductor body area 5, the upper strata of the second conductive type semiconductor body area 5 has between 11 lower surface
Separate and the first conductive type semiconductor source region 6 contacted and the second conductive type semiconductor heavy doping contact zone 11, and
Second conductive type semiconductor heavy doping contact zone 11 is located between the first conductive type semiconductor source region 6 of both sides, and first leads
The upper surface of the electric conductive type semiconductor heavy doping contact zone 11 of type semiconductor source region 6 and second connects with metallizing source 10
Touch；Second between the first conductive type semiconductor source region 6 and the first conduction type lightly doped epitaxial layer 3 adjacent thereto
Conductive type semiconductor body area 5 is channel region；The first conductive-type between two the second adjacent conductive type semiconductor posts 4
The upper surface of type lightly doped epitaxial layer 3 has the grid structure in embedded metallizing source 11, and the grid structure includes grid oxide layer 7
With the polysilicon gate 8 positioned at the upper surface of grid oxide layer 7, the grid structure extends to the conductive type semiconductor of part second to both sides
Body area 5 and the upper surface of part the first conductive type semiconductor source region 6；Lead between the grid structure and metallizing source 11
Dielectric layer 9 is crossed to isolate；Characterized in that, the second conductive type semiconductor post 4 has more than at least two different in width,
And the spacing between phase and the adjacent second conductive type semiconductor post 4 has more than at least two different in width, and second
The first adjacent conduction type lightly doped region of conductive type semiconductor post 4 meets charge balance.Device have two and
More than two above-mentioned repeat units.
Fig. 4-Figure 12, which is that a kind of gate leakage capacitance of the embodiment of the present invention one is gradual, obtains superjunction power VDMOSFET manufacturing approach craft
Schematic flow sheet.
First as shown in figure 4, passing through epitaxy technique, growth one on the heavily-doped semiconductor substrate 2 of the first conduction type
Layer meets the lightly doped epitaxial layer 3 of certain thickness first conduction type of specific resistance to pressure request, the usual substrate and outer oxygen layer
Material is silicon (Si)；
Then one layer of hard mask is formed by chemical vapor deposition in the lightly doped epitaxial layer 3 of the first conduction type, led to
Often the material of hard mask is silicon nitride (Si3N4), then gas phase is into counterdie, rotates resist coating, after exposure imaging, etches, is formed
Deep trouth, photoresist and hard mask are then removed by plasma etching, as shown in Figure 5；
As shown in fig. 6, by epitaxy technique growing P-type extension, put down after epitaxial growth by flatening process
The silicon chip of whole uniform thickness；
Next, carrying out field oxygen oxidation as shown in fig. 7, being sent into after Wafer Cleaning in high temperature furnace, spin coating, exposure shows
Shadow, dry etching active area, after Wafer Cleaning, grid oxygen 7 is formed into high temperature furnace dry-oxygen oxidation, passes through chemical vapor deposition method
Deposit one layer of certain thickness 8 layers of polysilicon gate；
As shown in figure 8, the purpose in the step is that have the second conductive-type at the top of the second conductive type semiconductor post 4
Type semiconductor body 5, Wafer Cleaning is carried out first after depositing polysilicon, then spin coating, exposure imaging, by dry after development
Method etches polycrystalline silicon 8 and grid oxide layer 7, then band glue the second conductive type ion of injection or this kind of ionic compound, remove photoresist, and clean
Body area 5, is formed at activator impurity by High temperature diffusion knot in diffusion furnace afterwards；
As shown in figure 9, spin coating, after photoetching, band glue injects the second conductive type ion or this kind of ionic compound, goes
Glue, the heavily doped area 11 of the second conductive type semiconductor is diffuseed to form into diffusion furnace high temperature knot after cleaning；
As shown in Figure 10, spin coating, after photoetching, band glue injects the first conductive type ion or this kind of ionic compound,
Remove photoresist, the heavily doped area 6 of the first conductive type semiconductor is diffuseed to form into diffusion furnace high temperature knot after cleaning；
Wafer Cleaning, by chemical vapor deposition dielectric layer 9, spin coating, exposure imaging, etch media layer 9, spreading
Flow back density in stove, forms source contact openings, as shown in figure 11.
Finally, as shown in figure 12, source metal and the moon are formed by metal sputtering, silicon chip back side reduction process, metallization
Pole metal.
Illustrate the operation principle of the present invention by taking embodiment 1 as an example.
For traditional superjunction devices, due to super-junction structure be present in Withstand voltage layer, so its internal pn-junction junction is larger.Cause
This, in drain-source voltage Vds very littles, the source drain capacitance value of hyperconjugation VDMOS is larger.Because the depletion layer of superjunction post is except in longitudinal direction
Extension is outer, still extends in the horizontal, so under less drain-source voltage Vds, whole post area is just completely depleted, so now
Space-charge region produces shielding action to miller capacitance Cgd and drain source capacitance Cds.Due to traditional hyperconjugation VDMOS, same
Voltage node Suo Zhu areas are just completely depleted so that miller capacitance Cgd occur and drain source capacitance Cds suddenly declines phenomenon.
Invention introduces multiple different PN posts width and spacing so that superjunction post area is respectively in multiple different source and drain
Voltage Vds nodes are completely depleted.Because the superjunction post area different with spacing of width in the present invention is in different source-drain voltage Vds
Under degree of exhaustion it is different, thus under certain source-drain voltage Vds, depletion region is to miller capacitance Cgd and drain source capacitance Cds screens
Lee-side product reduces, and chip total miller capacitance Cgd and total drain source capacitance Cds reduce amplitude and reduced, so as to compare traditional superjunction
VDMOS, the present invention can increase the source-drain voltage span of miller capacitance Cgd and drain source capacitance Cds rapid drawdowns, that is, reduce miller capacitance
The slope of Cgd and drain source capacitance Cds changes.So by such a mode, it can effectively alleviate miller capacitance Cgd and drain-source electricity
Hold the phenomenon that Cds drops suddenly.Simultaneously as the second described conductive type semiconductor post 4 it is adjacent the first conduction type it is light
Doped region meets charge balance, and the pressure-resistant of device can't be influenceed by superjunction column dimension and spacing change.
Embodiment 2
A kind of super junction power device, as shown in figure 3, the metalized drain 1 that is cascading from bottom to up, the first conductive-type
Type Semiconductor substrate 2, the first conduction type lightly doped epitaxial layer 3 and metallizing source 10；First conduction type is lightly doped
There is the second conductive type semiconductor post 4 in epitaxial layer 3；The top of the second conductive type semiconductor post 4 has second to lead
Electric type semiconductor body area 5；There is the He of the first conductive type semiconductor source region 6 in the second conductive type semiconductor body area 5
Second conductive type semiconductor heavy doping contact zone 11, first conductive type semiconductor 6 and the first adjacent conduction type
The second conductive type semiconductor body area 5 between lightly doped epitaxial layer 3 is channel region；Grid oxide layer 7 be covered in the channel region and
In first conduction type lightly doped epitaxial layer 3；Polysilicon gate 8 is covered on the grid oxide layer 7, and dielectric layer 9 surrounds the polycrystalline
Si-gate 8 and grid oxide layer 7, realize the electrical isolation of the polysilicon gate 8 and metallizing source 10.Second conduction type is partly led
The upper surface of body weight doping contact zone 11 and the portion of upper surface and metallizing source 10 of the first conductive type semiconductor source region 6 are straight
Contact.Characterized in that, the second conductive type semiconductor post 4 have two or more different in width (a1,
a2……、an；N >=2), and the spacing between the two neighboring second conductive type semiconductor post 4 has two or more
Different in width (b1, b2 ..., bn；N >=2), the arrangement mode of the second conductive type semiconductor post 4 and its spacing is a1, b1,
A1, b1......a2, b2, a2, b2 ... an, bn, an, bn ..., and the second described conductive type semiconductor post 4 faces with it
The first near conduction type lightly doped region meets charge balance.
Claims (3)
1. a kind of super junction power device, including metalized drain (1), the first conduction type weight being cascading from bottom to up
Doped substrate (2), the first conduction type lightly doped epitaxial layer (3) and metallizing source (10)；First conduction type is gently mixed
The second conductive type semiconductor post (4) of tool in miscellaneous epitaxial layer (3)；The second conductive type semiconductor post (4) and metallization source
There is the second conductive type semiconductor body area (5), the second conductive type semiconductor body area (5) between the lower surface of pole (11)
Upper strata has independently of each other and the first conductive type semiconductor source region (6) contacted and the second conductive type semiconductor heavy doping connect
Touch area (11), and the second conductive type semiconductor heavy doping contact zone (11) is located at the first conductive type semiconductor source region of both sides
(6) between, the upper surface of the first conductive type semiconductor source region (6) and the second conductive type semiconductor heavy doping contact zone (11)
Contacted with metallizing source (10)；It is light positioned at the first conductive type semiconductor source region (6) and the first conduction type adjacent thereto
The second conductive type semiconductor body area (5) between doped epitaxial floor (3) is channel region；In two the second adjacent conduction types
First conduction type lightly doped epitaxial layer (3) upper surface between semiconductor column (4) has in embedded metallizing source (11)
Grid structure, the grid structure include grid oxide layer (7) and the polysilicon gate (8) positioned at grid oxide layer (7) upper surface, the grid
Structure extends to part the second conductive type semiconductor body area (5) and part the first conductive type semiconductor source region to both sides
(6) upper surface；Isolated between the grid structure and metallizing source (11) by dielectric layer (9)；It is characterized in that, described
Second conductive type semiconductor post (4) has more than at least two different in width, and phase and adjacent second conduction type
Spacing between semiconductor column (4) has more than at least two different in width, and the second conductive type semiconductor post (4) faces with it
The first near conduction type lightly doped region meets charge balance.
2. a kind of super junction power device according to claim 1, it is characterised in that first conductive type semiconductor is n
Type semiconductor, second conductive type semiconductor are p-type semiconductor；Or first conductive type semiconductor is p-type half
Conductor, second conductive type semiconductor are n-type semiconductor.
3. a kind of super junction power device according to claim 1, it is characterised in that the material of the grid oxide layer (7) is oxidation
Silicon, silicon nitride, silicon oxynitride, the insulating materials of lead oxide or high-k.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710665471.8A CN107464837B (en) | 2017-08-07 | 2017-08-07 | Super junction power device |
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| CN201710665471.8A CN107464837B (en) | 2017-08-07 | 2017-08-07 | Super junction power device |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111989778A (en) * | 2018-04-20 | 2020-11-24 | 艾鲍尔半导体 | Small-spacing super junction MOSFET structure and method |
| WO2022257529A1 (en) * | 2021-06-07 | 2022-12-15 | 华润微电子（重庆）有限公司 | Super junction mosfet device |
| WO2023045414A1 (en) * | 2021-09-26 | 2023-03-30 | 苏州东微半导体股份有限公司 | Semiconductor super junction power device |
| WO2023087714A1 (en) * | 2021-11-17 | 2023-05-25 | 苏州东微半导体股份有限公司 | Semiconductor super-junction power device |
| WO2023087685A1 (en) * | 2021-11-17 | 2023-05-25 | 苏州东微半导体股份有限公司 | Semiconductor superjunction power device |
| WO2023087684A1 (en) * | 2021-11-17 | 2023-05-25 | 苏州东微半导体股份有限公司 | Semiconductor super-junction power device |
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2017
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| US5438215A (en) * | 1993-03-25 | 1995-08-01 | Siemens Aktiengesellschaft | Power MOSFET |
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| US20120267705A1 (en) * | 2008-08-29 | 2012-10-25 | Sony Corporation | Semiconductor device and manufacturing method of the same |
| CN102468337A (en) * | 2010-11-09 | 2012-05-23 | 富士电机株式会社 | Semiconductor device |
| CN104638004A (en) * | 2013-11-15 | 2015-05-20 | 上海华虹宏力半导体制造有限公司 | Super-junction MOSFET (metal-oxide-semiconductor field-effect transistor) device structure |
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| CN111989778A (en) * | 2018-04-20 | 2020-11-24 | 艾鲍尔半导体 | Small-spacing super junction MOSFET structure and method |
| CN111989778B (en) * | 2018-04-20 | 2024-02-13 | 艾鲍尔半导体 | Small-pitch superjunction MOSFET structure and method |
| WO2022257529A1 (en) * | 2021-06-07 | 2022-12-15 | 华润微电子（重庆）有限公司 | Super junction mosfet device |
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| WO2023087714A1 (en) * | 2021-11-17 | 2023-05-25 | 苏州东微半导体股份有限公司 | Semiconductor super-junction power device |
| WO2023087685A1 (en) * | 2021-11-17 | 2023-05-25 | 苏州东微半导体股份有限公司 | Semiconductor superjunction power device |
| WO2023087684A1 (en) * | 2021-11-17 | 2023-05-25 | 苏州东微半导体股份有限公司 | Semiconductor super-junction power device |
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