CN108511527A - Vertical double-diffusion metal-oxide-semiconductor field effect transistor and preparation method thereof with charge compensation block - Google Patents
Vertical double-diffusion metal-oxide-semiconductor field effect transistor and preparation method thereof with charge compensation block Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000009792 diffusion process Methods 0.000 title claims abstract description 19
- 238000002360 preparation method Methods 0.000 title abstract 2
- 238000002353 field-effect transistor method Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 52
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 34
- 239000000463 material Substances 0.000 claims abstract description 23
- 230000005669 field effect Effects 0.000 claims abstract description 15
- 238000000407 epitaxy Methods 0.000 claims description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 5
- 238000002161 passivation Methods 0.000 claims description 5
- 229910002601 GaN Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 230000007423 decrease Effects 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910003460 diamond Inorganic materials 0.000 claims description 2
- 239000010432 diamond Substances 0.000 claims description 2
- AHKZTVQIVOEVFO-UHFFFAOYSA-N oxide(2-) Chemical compound [O-2] AHKZTVQIVOEVFO-UHFFFAOYSA-N 0.000 claims 2
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 230000005684 electric field Effects 0.000 abstract description 7
- 230000017525 heat dissipation Effects 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 4
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/1608—Silicon carbide
Abstract
The present invention proposes a kind of vertical double-diffusion metal-oxide-semiconductor field effect transistor (VDMOS) and preparation method thereof with charge compensation block.The device forms the smaller N-type silicon carbide epitaxial layers of doping concentration in N+ type silicon carbide semiconductor substrate materials upper surface, and multilayer p-type charge compensation block is re-formed in the N-type silicon carbide drift region of VDMOS device；The active area of novel silicon carbide VDMOS device is formed on basis herein.The structure is modulated the longitudinal electric field of VDMOS device using the new electric field peak that multilayer p-type silicon carbide charge compensation block generates, while optimised devices breakdown voltage is with than conducting resistance contradiction, the features such as taking full advantage of wide bandgap semiconductor materials high critical breakdown electric field, being formed has the novel VDMOS of the low silicon carbide than conducting resistance and high-breakdown-voltage；In addition the high heat conductance characteristic of carbofrax material is conducive to the heat dissipation of VDMOS device, and the performance of device is effectively improved.
Description
Technical field
The present invention relates to power semiconductor field more particularly to a kind of vertical DMOS fields
Effect pipe.
Background technology
Power semiconductor refers to the transformation of electrical energy for being mainly used for power equipment and the high-power electricity in terms of control circuit
Sub- device.With the rapid development of power electronic technique, power semiconductor have been widely used for modern industry control and
In defence equipment.Vertical double-diffused MOS field-effect transistor (VDMOS, Vertical Double-
Diffusion Metal Oxide Semiconductor) with its switching speed is fast, loss is small, input impedance is high, driving power
The characteristics such as small, frequency characteristic is good, mutual conductance high linearity height are usually used in power integrated circuit and power integrated system.
However the most important problem of VDMOS power devices be exactly the ratio conducting resistance of device with the increase of breakdown voltage and
It increased dramatically, which greatly limits the development of VDMOS power devices and applications.
Invention content
The present invention proposes a kind of silicon carbide vertical DMOS power device with charge compensation block
Part, it is intended to advanced optimize the breakdown voltage of VDMOS and than conducting resistance, improve device performance.
Technical scheme is as follows：
The vertical double-diffusion metal-oxide-semiconductor field effect transistor with charge compensation block, including：
The N+ type substrates of semi-conducting material double as drain region；
In the N-type epitaxy layer for the same semiconductor material that the N+ types substrate top surface is formed；
In the N-type epitaxy layer upper area at two that both sides are formed p-type base area；
Raceway groove and N+ types source region and P+ the channeled substrates contact formed in the p-type base area of everywhere, wherein N+ types source region
It is abutted with raceway groove, the contact of P+ channeled substrates is located at raceway groove distal end relative to N+ type source regions；
Gate oxide, is located at the N-type epitaxy layer upper surface, part at covering two between p-type base area and corresponding
Raceway groove at two；
Grid is located at gate oxide upper surface；
Source electrode is covered in the upper surface that P+ channeled substrates contact the region that connects with N+ type source regions；Source electrode connects altogether at two；
Drain electrode is located at the N+ types substrate lower surface；
Be different from the prior art is：
The N+ types substrate and N-type epitaxy layer are wide bandgap semiconductor materials；In the N-type epitaxy layer, correspond to
P-type base area at two, the respectively longitudinally spaced p-type charge compensation block that multilayer same semiconductor material is distributed with；
The trend being sequentially reduced is presented from p-type base area to N+ type substrates for the transverse width of p-type charge compensation block, maximum horizontal
It is no more than the transverse width of p-type base area to width；The doping concentration of p-type charge compensation block is in then from p-type base area to N+ types substrate
The trend being now sequentially increased；
The low 4-6 order of magnitude of doping concentration of the doping concentration ratio N+ type substrates of N-type epitaxy layer, p-type charge compensation block
The low 3-5 order of magnitude of doping concentration of doping concentration ratio N+ type substrates.
N-type epitaxy layer and specific thickness, spacing and the doping concentration of p-type charge compensation block are determined by the resistance to pressure request of device
It is fixed.
Based on above scheme, the present invention has also further made following optimization：
The wide bandgap semiconductor materials are gallium nitride, silicon carbide or diamond.
The p-type base area, N+ types source region, the contact of P+ channeled substrates and raceway groove, are used in N-type epitaxy layer upper area
What ion implanting and double diffusion technique were formed.
The whole symmetrical structure of p-type base area and multilayer p-type charge compensation block.
Multilayer p-type charge compensation block transverse width successively decreases 10%~40% successively.
Maximum transverse width is the 70%~90% of p-type base area transverse width in multilayer p-type charge compensation block；Minimum
Transverse width is the 10%~40% of p-type base area transverse width.
Transverse width maximum (i.e. near p-type base area) p-type charge compensation block and p-type base area between fore-and-aft distance be
The 5%~20% of N-type epitaxy layer longitudinal thickness；The p-type charge compensation block and N of transverse width minimum (i.e. closest to N+ types substrate)
Fore-and-aft distance is the 5%~20% of N-type epitaxy layer longitudinal thickness between+type substrate.
Fore-and-aft distance between adjacent two layers p-type charge compensation block is equal, and for N-type epitaxy layer longitudinal thickness 5%~
20%；The sum of described multilayer p-type charge compensation block longitudinal thickness is the 40%~80% of N-type epitaxy layer longitudinal thickness.
Grid is polysilicon gate, and source electrode and drain electrode is metallic electrode.
A method of the above-mentioned vertical double-diffusion metal-oxide-semiconductor field effect transistor with charge compensation block is made,
Include the following steps：
Wide bandgap semiconductor materials N+ type substrates upper surface formed wide bandgap semiconductor materials N-type epitaxy layer and
P-type charge compensation block；
Metalized drain is formed in N+ type substrates lower surface；
P-type base area and its N+ types source region and P+ ditches at two are respectively formed using ion implanting in N-type epitaxy layer upper area
Road substrate contact, and corresponding raceway groove is formed using double diffusion technique；
Gate oxide and polysilicon are deposited in entire N-type epitaxy layer upper surface, then etches polycrystalline silicon and gate oxide
(removal is located at the part of source electrode upper surface at two), form polysilicon gate；
Passivation layer is deposited in device surface, and contact hole is etched in the position corresponding to source electrode；
Metal is deposited in contact hole and etches (removal remaining passivation layer of periphery) and forms source electrode, and source electrode at two is total to
It connects.
Beneficial effects of the present invention are as follows：
The present invention makes full use of the advantages such as the high critical breakdown electric field of wide bandgap semiconductor materials, first on N+ type substrates
Surface forms the smaller N-type epitaxy layer of doping concentration, and the carbonization of multilayer p-type is then re-formed in the N-type drift region of VDMOS device
Silicon charge compensation block；The active area of VDMOS device is formed on this basis again.The structure is mended using multilayer p-type silicon carbide charge
Repay block generation new electric field peak the longitudinal electric field of VDMOS device is modulated, optimised devices breakdown voltage with than conducting resistance
It is contradictory simultaneously as the advantages such as high critical breakdown electric field of wide bandgap semiconductor materials, formed have it is low than conducting resistance and
The novel VDMOS of high-breakdown-voltage.
The high heat conductance characteristic of the materials such as silicon carbide also helps the heat dissipation of novel VDMOS device, and the performance of device is into one
Step is effectively improved.
Description of the drawings
Fig. 1 is the structural schematic diagram of the present invention.
Wherein, 1- source electrodes；2- gate oxides；3- grids；4- source electrodes；5-P+ channeled substrates contact (P+ type body area)；6-N+
Type source region；7-P types base area；801-N type silicon carbide epitaxial layers；802-P type silicon carbide charge compensation blocks；803-N+ type substrates；9-
Drain electrode.
Specific implementation mode
The present invention is introduced by taking N-channel VDMOS as an example below in conjunction with the accompanying drawings.
As shown in Figure 1, the structure of the present embodiment includes：
The N+ types substrate 803 of carbofrax material；
In the N-type epitaxy layer for the manufacturing silicon carbide semiconductor material that 803 upper surface of N+ types substrate is formed, it is denoted as outside N-type silicon carbide
Prolong layer 801；
Multilayer p-type silicon carbide charge compensation block 802；802 number of plies of multilayer p-type charge compensation block can be with N-type silicon carbide epitaxy
The increase of 801 longitudinal thickness of layer successively increases；The transverse width of p-type charge compensation block 802 is from p-type base area 7 to N+ types substrate 803
The trend being sequentially reduced is presented, maximum lateral width is no more than the transverse width of p-type base area 7；P-type charge compensation block 802
The trend being sequentially increased then is presented from p-type base area 7 to N+ types substrate 803 in doping concentration；Multilayer p-type charge compensation block 802 is laterally
Width successively decreases 10%~40% successively；Maximum transverse width is 7 transverse width of p-type base area in multilayer p-type charge compensation block 802
70%~90%；Minimum transverse width is the 10%~40% of 7 transverse width of p-type base area；Transverse width it is maximum (i.e. near
Nearly p-type base area) p-type charge compensation block 802 and p-type base area 7 between fore-and-aft distance be that N-type silicon carbide epitaxial layers 801 are longitudinal
The 5%~20% of thickness；The p-type charge compensation block 802 of transverse width minimum (i.e. closest to N+ types substrate) and N+ types substrate 803
Between fore-and-aft distance be 801 longitudinal thickness of N-type silicon carbide epitaxial layers 5%~20%；Adjacent two layers p-type charge compensation block
(802) fore-and-aft distance between is equal, and is the 5%~20% of 801 longitudinal thickness of N-type silicon carbide epitaxial layers；The multilayer p-type
The sum of 802 longitudinal thickness of charge compensation block is the 40%~80% of 801 longitudinal thickness of N-type silicon carbide epitaxial layers；
The p-type base area 7 at two that 801 top of N-type silicon carbide epitaxial layers is formed；The ditch formed in everywhere p-type base area 7
Road and N+ types source region 6 and P+ channeled substrates contact 5, wherein N+ types source region 6 are abutted with raceway groove, and P+ channeled substrates contact 5 is opposite
It is located at raceway groove distal end in N+ types source region 6；
Gate oxide 2, is located at 801 upper surface of N-type silicon carbide epitaxial layers, part at covering two between p-type base area 7 and
Raceway groove at corresponding two；
Grid 3 is located at 2 upper surface of gate oxide；
Source electrode 1,4, the upper surface that covering P+ channeled substrates contact 5 connects region with N+ types source region 6；Source electrode 1,4 is total at two
It connects；
Drain electrode 9 is located at 803 lower surface of N+ types substrate.
The device can specifically be prepared by following steps：
N-type silicon carbide epitaxial layers 801 are formed in the upper surface of the N+ types substrate 803 of manufacturing silicon carbide semiconductor material；It is being formed
While N-type silicon carbide epitaxial layers 801, multilayer p-type silicon carbide charge compensation block 802, wherein N-type silicon carbide epitaxy are formed
The low 4-6 order of magnitude of doping concentration of the doping concentration ratio N+ types substrate 803 of layer 801, p-type silicon carbide charge compensation block 802
The low 3-5 order of magnitude of doping concentration of doping concentration ratio N+ types substrate 803；
Metalized drain is formed in 803 lower surface of N+ types substrate；
P-type base area 7 and its N+ types at two are respectively formed using ion implanting in 801 upper area of N-type silicon carbide epitaxial layers
Source region 6 and P+ channeled substrates contact 5, and corresponding raceway groove is formed using double diffusion technique；
Deposit gate oxide and polysilicon in entire 801 upper surface of N-type silicon carbide epitaxial layers, then etches polycrystalline silicon and
Gate oxide (removal is located at the part of source electrode upper surface at two), forms polysilicon gate；
Passivation layer is deposited in device surface, and contact hole is etched in the position corresponding to source electrode；
Metal is deposited in contact hole and etches (removal remaining passivation layer of periphery) and forms source electrode, and source electrode at two is total to
It connects.
Show that the device is imitated compared with Conventional silicon carbide vertical DMOS field through ISE TCAD emulation
Ying Guan, device performance are effectively improved, identical in two kinds of device drift region length and concentration, the breakdown of the device
Voltage improves 40% or more.
VDMOS in the present invention can certainly be P-type channel, and structure is equal with N-channel VDMOS, it should also be considered as
Belong to the application scope of the claims, details are not described herein.
The broad-band gap manufacturing silicon carbide semiconductor material that VDMOS in the present embodiment is used, naturally it is also possible to for gallium nitride, Buddha's warrior attendant
The wide bandgap semiconductor materials such as stone, structure are equal with silicon carbide VDMOS, it should also be considered as belonging to the guarantor of the application claim
Range is protected, details are not described herein.
Claims (10)
1. the vertical double-diffusion metal-oxide-semiconductor field effect transistor with charge compensation block, including：
The N+ types substrate (803) of semi-conducting material doubles as drain region；
In the N-type epitaxy layer (801) for the same semiconductor material that N+ types substrate (803) upper surface is formed；
In the N-type epitaxy layer (801) upper area at two that both sides are formed p-type base area (7)；
The raceway groove and N+ types source region (6) and P+ channeled substrates formed in everywhere p-type base area (7) contacts (5), wherein N+ types
Source region (6) is abutted with raceway groove, and P+ channeled substrates contact (5) and are located at raceway groove distal end relative to N+ types source region (6)；
Gate oxide (2), is located at the N-type epitaxy layer (801) upper surface, part at covering two between p-type base area (7) and
Raceway groove at corresponding two；
Grid (3) is located at gate oxide (2) upper surface；
Source electrode (1,4) is covered in P+ channeled substrates contact (5) and connects with N+ types source region (6) upper surface in region；Source electrode at two
(1,4) connect altogether；
It drains (9), is located at N+ types substrate (803) lower surface；
It is characterized in that：
The N+ types substrate (803) and N-type epitaxy layer (801) are wide bandgap semiconductor materials；In the N-type epitaxy layer
(801) in, correspond to p-type base area (7) at two, respectively the longitudinally spaced p-type charge that multilayer same semiconductor material is distributed with
Compensation block (802)；
Becoming of being sequentially reduced is presented from p-type base area (7) to N+ types substrate (803) for the transverse width of p-type charge compensation block (802)
Gesture, maximum lateral width are no more than the transverse width of p-type base area (7)；The doping concentration of p-type charge compensation block (802) is from p-type
The trend being sequentially increased then is presented to N+ types substrate (803) in base area (7)；
The low 4-6 order of magnitude of doping concentration of the doping concentration ratio N+ types substrate (803) of N-type epitaxy layer (801), p-type charge are mended
Repay the low 3-5 order of magnitude of doping concentration of the doping concentration ratio N+ types substrate (803) of block (802).
2. the vertical double-diffusion metal-oxide-semiconductor field effect transistor according to claim 1 with charge compensation block,
It is characterized in that：The wide bandgap semiconductor materials are gallium nitride, silicon carbide or diamond.
3. the vertical double-diffusion metal-oxide-semiconductor field effect transistor according to claim 1 with charge compensation block,
It is characterized in that：The p-type base area (7), N+ types source region (6), P+ channeled substrates contact (5) and raceway groove, are in N-type epitaxy layer
(801) upper area is formed using ion implanting and double diffusion technique.
4. the vertical double-diffusion metal-oxide-semiconductor field effect transistor according to claim 1 with charge compensation block,
It is characterized in that：P-type base area (7) and the whole symmetrical structure of multilayer p-type charge compensation block (802).
5. the vertical DMOS field-effect according to claim 1 or 4 with charge compensation block
Pipe, it is characterised in that：Multilayer p-type charge compensation block (802) transverse width successively decreases 10%~40% successively.
6. the vertical double-diffusion metal-oxide-semiconductor field effect transistor according to claim 5 with charge compensation block,
It is characterized in that：In multilayer p-type charge compensation block (802) maximum transverse width be p-type base area (7) transverse width 70%~
90%；Minimum transverse width is the 10%~40% of p-type base area (7) transverse width.
7. the vertical double-diffusion metal-oxide-semiconductor field effect transistor according to claim 5 with charge compensation block,
It is characterized in that：It is outside N-type closest to the fore-and-aft distance between the p-type charge compensation block (802) and p-type base area (7) of p-type base area
Prolong the 5%~20% of layer (801) longitudinal thickness；Closest to the p-type charge compensation block (802) and N+ type substrates of N+ type substrates
(803) fore-and-aft distance is the 5%~20% of N-type epitaxy layer (801) longitudinal thickness between.
8. the vertical double-diffusion metal-oxide-semiconductor field effect transistor according to claim 5 with charge compensation block,
It is characterized in that：Fore-and-aft distance between adjacent two layers p-type charge compensation block (802) is equal, and vertical for N-type epitaxy layer (801)
To the 5%~20% of thickness；The sum of described multilayer p-type charge compensation block (802) longitudinal thickness is that N-type epitaxy layer (801) is longitudinal
The 40%~80% of thickness.
9. the vertical double-diffusion metal-oxide-semiconductor field effect transistor according to claim 1 with charge compensation block,
It is characterized in that：The grid (3) is polysilicon gate, and the source electrode (1,4) and drain electrode (9) are metallic electrode.
10. a kind of making the vertical DMOS field effect described in claim 1 with charge compensation block
Should pipe method, include the following steps：
The N-type epitaxy layer and p-type of wide bandgap semiconductor materials are formed in the upper surface of the N+ type substrates of wide bandgap semiconductor materials
Charge compensation block；
Metalized drain is formed in N+ type substrates lower surface；
P-type base area and its N+ types source region and P+ raceway grooves at two are respectively formed in N-type epitaxy layer upper area using ion implanting to serve as a contrast
Bottom contacts, and forms corresponding raceway groove using double diffusion technique；
Gate oxide and polysilicon are deposited in entire N-type epitaxy layer upper surface, then etches polycrystalline silicon and gate oxide, form
Polysilicon gate；
Passivation layer is deposited in device surface, and contact hole is etched in the position corresponding to source electrode；
Metal is deposited in contact hole and is etched and forms source electrode, and source electrode at two is connect altogether.
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| CN110047932A (en) * | 2019-04-16 | 2019-07-23 | 西安电子科技大学 | Vertical double-diffused MOS field effect transistor and preparation method thereof with charge compensating layer and low impedance path |
| CN113394298A (en) * | 2021-06-23 | 2021-09-14 | 电子科技大学 | LDMOS device with ultralow specific on resistance and manufacturing method thereof |
| WO2023193288A1 (en) * | 2022-04-08 | 2023-10-12 | Hong Kong Applied Science and Technology Research Institute Company Limited | Silicon-carbide (sic) metal-oxide-semiconductor field-effect transistor (mosfet) with short circuit protection |
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| CN102420251A (en) * | 2011-12-05 | 2012-04-18 | 电子科技大学 | VDMOS (Vertical Double-Diffusion Metal-Oxide-Semiconductor) device with non-uniform floating island structure |
| US20140367771A1 (en) * | 2013-06-18 | 2014-12-18 | Monolith Semiconductor, Inc. | High voltage semiconductor devices and methods of making the devices |
| CN107437566A (en) * | 2017-07-27 | 2017-12-05 | 西安电子科技大学 | One kind has compound medium layer wide band gap semiconducter vertical double-diffused MOS FET and preparation method thereof |
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| CN102420251A (en) * | 2011-12-05 | 2012-04-18 | 电子科技大学 | VDMOS (Vertical Double-Diffusion Metal-Oxide-Semiconductor) device with non-uniform floating island structure |
| US20140367771A1 (en) * | 2013-06-18 | 2014-12-18 | Monolith Semiconductor, Inc. | High voltage semiconductor devices and methods of making the devices |
| CN107437566A (en) * | 2017-07-27 | 2017-12-05 | 西安电子科技大学 | One kind has compound medium layer wide band gap semiconducter vertical double-diffused MOS FET and preparation method thereof |
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| CN110047932A (en) * | 2019-04-16 | 2019-07-23 | 西安电子科技大学 | Vertical double-diffused MOS field effect transistor and preparation method thereof with charge compensating layer and low impedance path |
| CN113394298A (en) * | 2021-06-23 | 2021-09-14 | 电子科技大学 | LDMOS device with ultralow specific on resistance and manufacturing method thereof |
| CN113394298B (en) * | 2021-06-23 | 2023-06-16 | 电子科技大学 | LDMOS device with ultralow specific on-resistance and manufacturing method thereof |
| WO2023193288A1 (en) * | 2022-04-08 | 2023-10-12 | Hong Kong Applied Science and Technology Research Institute Company Limited | Silicon-carbide (sic) metal-oxide-semiconductor field-effect transistor (mosfet) with short circuit protection |
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