CN102420251A - VDMOS (Vertical Double-Diffusion Metal-Oxide-Semiconductor) device with non-uniform floating island structure - Google Patents
VDMOS (Vertical Double-Diffusion Metal-Oxide-Semiconductor) device with non-uniform floating island structure Download PDFInfo
- Publication number
- CN102420251A CN102420251A CN2011103986540A CN201110398654A CN102420251A CN 102420251 A CN102420251 A CN 102420251A CN 2011103986540 A CN2011103986540 A CN 2011103986540A CN 201110398654 A CN201110398654 A CN 201110398654A CN 102420251 A CN102420251 A CN 102420251A
- Authority
- CN
- China
- Prior art keywords
- type semiconductor
- conductive type
- chinampa
- vdmos
- floating island
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 110
- 238000007667 floating Methods 0.000 title abstract description 16
- 238000009792 diffusion process Methods 0.000 title abstract description 4
- 238000001465 metallisation Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 12
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 2
- 239000002131 composite material Substances 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 9
- 238000011084 recovery Methods 0.000 abstract description 9
- 238000001259 photo etching Methods 0.000 description 9
- 230000005684 electric field Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 238000009826 distribution Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000004308 accommodation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A VDMOS (Vertical Double-Diffusion Metal-Oxide-Semiconductor) device with a non-uniform floating island structure belongs to the technical field of semiconductor power. For the VDMOS device, the non-uniform floating island structure is drawn into a first conductive type semiconductor drift region of a common VDMOS and comprises at least two layers of second conductive type semiconductor floating islands which are respectively an upper layer of second conductive type semiconductor floating island and a lower layer of second conductive type semiconductor floating island, wherein the upper layer of second conductive type semiconductor floating island is larger in transverse width dimension and lower in doping density, and the lower layer of second conductive type semiconductor floating island is smaller in transverse width dimension and higher in doping density. Compared with the common VDMOS, the VDMOS with the non-uniform floating island, provided by the invention, can adopt higher electrical resistivity of an epitaxial layer under the condition the same puncture voltage, thereby the on-resistance is greatly reduced; compared with a VDMOS with a uniform floating island, the VDMOS with the non-uniform floating island is wider in current path and also can lead the on-resistance to be reduced; and compared with a super-junction VDMOS, the VDMOS is better in the reverse recovery characteristic of a body diode and is relatively simple in process.
Description
Technical field
The invention belongs to the power semiconductor technical field, (Vertical Double Diffusion MOSFET VDMOS), especially has the VDMOS device of chinampa structure to relate to vertical double diffusion Metal-oxide-semicondutor FET.
Background technology
The VDMOS device has plurality of advantages such as input impedance height, switching speed are fast, driven, Heat stability is good, thereby in power system, has widely and use.In switching device is used, hope that usually VDMOS not only has high puncture voltage, and have low conducting resistance to have good body diode reverse recovery characteristics simultaneously to suppress noise and the voltage surge in the switching process to reduce power consumption.Because there is the restricting relation (conducting resistance is proportional to 2.5 powers of puncture voltage) of conducting resistance and puncture voltage in traditional VDMOS; The researcher once proposed to introduce the compromise (as shown in Figure 1) that super-junction structure (super-junction) is optimized conducting resistance and puncture voltage in the drift region of common VDMOS device; But because super-junction structure has two big shortcomings: the reverse recovery characteristic difference of body diode and manufacture craft difficulty are high, and feasible application scenario with VDMOS device of super-junction structure is restricted and cost remains high.
For overcoming the shortcoming of super junction device; Document C é zac N; Morancho F; Rossel P, Tranducand H, Peyre Lavigne A.A New Generation of Power Unipolar Devices:the Concept of the FLoating Islands MOS Transistor.Proceedings of the 12
ThInternational symposium on power semiconductor Devices and ICs Toulouse.France, May 22-25,2000 p69 propose a kind of chinampa MOSFET (FLoating Islands MOSFET, notion FLIMOS).Through in the VDMOS device drift region, introducing the chinampa of opposite doping type; Can under the situation that does not reduce device electric breakdown strength, reduce its conducting resistance; Its reason is: the chinampa of introducing and drift region have formed additional PN junction, and a plurality of PN junctions can bear higher withstand voltage.Can reduce break-over of device resistance through increasing the drift region doping content in that withstand voltage constant situation is next.
In theory, the puncture voltage of chinampa MOSFET can increase along with the increase of chinampa number.In order to obtain the better compromise of conducting resistance and puncture voltage, document Luo X R, Fu D P; Gao H M; Chen X.Ultra-low On-resistance Trench Gate MOSFET with Buried P-Island.IEEE International Conference on Communications, Circuits and Systems (ICCCAS), Chengdu; China; July 28-30,2010 p496 have proposed a kind of two groove gate power MOS FET devices on P island that bury that have, and adopt self-registered technology to form width, thickness and doping content uniform two-layer p type chinampa structure (as shown in Figure 3).
Summary of the invention
The present invention provides a kind of VDMOS device with non-homogeneous chinampa structure; Through in the drift region of VDMOS device, introduce multilayer heterogeneous, with the chinampa structure of drift region films of opposite conductivity; Under the situation that does not increase conducting resistance, improve device withstand voltage, alleviated conducting resistance and withstand voltage between contradiction.Compare with traditional VDMOS device, under the identical situation of puncture voltage, the VDMOS device with non-homogeneous chinampa structure provided by the invention can adopt the epitaxial loayer with higher electric resistivity, thereby conducting resistance is reduced greatly; Compare with the VDMOS device with super-junction structure, the body diode reverse recovery characteristics in the VDMOS device with non-homogeneous chinampa structure provided by the invention is better, and technology is simple relatively, and process allowance is bigger; Compare with the VDMOS device with even chinampa structure, the VDMOS device current path when conducting with non-homogeneous chinampa structure provided by the invention is wideer, and conducting resistance is further reduced.
Technical scheme of the present invention is following:
A kind of VDMOS device with non-homogeneous chinampa structure; As shown in Figure 4, comprise metallization source electrode 1, polygate electrodes 2, insulating medium layer 3, the first conductive type semiconductor doping source region 4, the second conductive type semiconductor base 5, the second conductive type semiconductor doping contact zone 6, the first conductive type semiconductor doped drift region 7, the first conductive type semiconductor doped substrate 10 and metallization drain electrode 11.Metallization drain electrode 11 is positioned at the back side of the first conductive type semiconductor doped substrate 10, and the first conductive type semiconductor doped drift region 7 is positioned at the front of the first conductive type semiconductor doped substrate 10; The second conductive type semiconductor base 5 is positioned at the both sides, top of the first conductive type semiconductor doped drift region 7, has in the second conductive type semiconductor base 5 respectively and the metallization source electrode 1 contacted first conductive type semiconductor doping source region 4 and the second conductive type semiconductor doping contact zone 6; Gate dielectric layer is positioned at the upper surface of the second conductive type semiconductor base 5 and the first conductive type semiconductor doped drift region 7; Polygate electrodes 2 is positioned at the upper surface of gate dielectric layer, and what fill between polygate electrodes 2 and the metallization source electrode 1 is insulating medium layer 3.The said first conductive type semiconductor doped drift region 7 inside also have non-homogeneous chinampa structure, and said non-homogeneous chinampa structure comprises the two-layer at least second conductive type semiconductor chinampa: the second conductive type semiconductor chinampa 8 and the lower floor second conductive type semiconductor chinampa 9, upper strata; The transverse width dimension on the second conductive type semiconductor chinampa 8, said upper strata is greater than the transverse width dimension on the lower floor second conductive type semiconductor chinampa 9, and the doping content on the second conductive type semiconductor chinampa 8, said upper strata is less than the doping content on the lower floor second conductive type semiconductor chinampa 9.
VDMOS device with non-homogeneous chinampa structure provided by the invention, alleviated traditional VDMOS conducting resistance and withstand voltage between contradiction, at the constant situation decline low on-resistance of puncture voltage.Compare with even chinampa VDMOS structure, its current path is wideer, under same breakdown voltage, has lower conducting resistance.Compare with super-junction structure, the reverse recovery characteristic of body diode is better; The extrusion effect that does not have electric current under the high pressure, resistance can not increase, and technology is simple relatively simultaneously, and process allowance is bigger.Existing is that example is explained operation principle of the present invention with N channel device (like Fig. 4).
As shown in Figure 4, the VDMOS device with non-homogeneous chinampa structure provided by the present invention is on the basis of common VDMOS structure, at N
-Form P chinampa, upper strata heterogeneous 8 and lower floor P chinampa 9 in the drift region 7.The width on P chinampa, upper strata 8 is big but doping content is less, and the width on lower floor P chinampa 9 is less but doping content is bigger.For verifying the working mechanism of non-homogeneous chinampa VDMOS, the common VDMOS with identical N type epitaxial thickness and doping content, even chinampa VDMOS and non-homogeneous chinampa VDMOS have been carried out electrology characteristic emulation, the Electric Field Distribution when their puncture is as shown in Figure 5.Can find out the distribution triangular in shape of common VDMOS drift region electric field, and the drift region electric field of even chinampa VDMOS and non-homogeneous chinampa VDMOS there are three peak values.
The mechanism of chinampa structure raising puncture voltage is similar with the floating barnyard limiting ring structure in the plane terminal.As shown in Figure 6, under anti-situation partially, the depletion region of the PN junction that forms when P district and N drift region is during to the ground floor chinampa, and chinampa electromotive force increase and then produce new depletion layer is up to the orlop chinampa.Therefore, the maximum field at the PN junction place that P district and N drift region form is divided into a plurality of peak electric field, and puncture voltage is born by a plurality of PN junctions longitudinally jointly.In floating barnyard limit loop technique, can optimize terminal structure, reach the puncture voltage higher than even end ring through the doping content of adjustment ring spacing, ring width and ring.In like manner, non-homogeneous chinampa VDMOS also can obtain the compromise that has better conducting resistance and puncture voltage than even chinampa VDMOS.The situation that n layer chinampa arranged for the drift region; Puncture voltage is evenly shared by (n+1) individual PN junction; Reduced but compare the conducting area with common VDMOS structure, Fig. 7 has provided common VDMOS, even chinampa VDMOS and the current distributing figure of non-homogeneous chinampa VDMOS when conducting.Therefore evenly but chinampa structure drift zone resistance approximate representation is:
R wherein
D, limAnd R
D_HIt is respectively the drift zone resistance of common VDMOS and even chinampa VDMOS.The reason that non-homogeneous chinampa VDMOS is lower than the conducting resistance of even chinampa VDMOS is that current path is bigger.
Along with the increase of n, the tradeoff of conducting resistance and puncture voltage can improve, but technology can become more complicated.Therefore the structure that proposes of the present invention more has superiority in low pressure applications, and only need less chinampa number this moment, only increases less technology cost and just can under the constant situation of puncture voltage, obtain lower conducting resistance.
Compare with hyperconjugation VDMOS, the advantage of the VDMOS device with non-homogeneous chinampa structure that the present invention proposes is to have better body diode reverse recovery characteristics.In the hyperconjugation VDMOS,, there is a large amount of non-equilibrium few sons to be injected in the drift region when causing the body diode forward conduction because P post district has introduced large-area PN junction in the epitaxial loayer.Before device bears high back voltage, these non-equilibrium few sons must remove fully, the QRR that this has just increased.Simultaneously, the drain-source electric capacity (C of super junction VDMOS
Ds) in the reverse process of recovering, change acutely.C when drain-source voltage is low
DsVery big, and when P post district and N drift region exhaust C
DsCan reduce rapidly.Therefore, the reverse recovery characteristic of super junction VDMOS body diode is harder.In the VDMOS structure of non-homogeneous chinampa, because the P island is floating empty, current potential is variable, and the few subnumber order that is injected into the drift region by the P island is much smaller than super junction VDMOS, and therefore the drain-source changes in capacitance has better body diode reverse recovery characteristics also much smaller than super junction VDMOS.
Description of drawings
Fig. 1 is common VDMOS device architecture sketch map.
Fig. 2 is a super junction VDMOS device architecture sketch map.
Fig. 3 is the even chinampa VDMOS device architecture sketch map that proposes in the existing document.
Fig. 4 is a kind of VDMOS device architecture sketch map with non-homogeneous chinampa structure provided by the invention.
Among Fig. 1 to Fig. 4: the 1st, metallization source electrode, the 2nd, polygate electrodes, the 3rd, spacer medium, the 4th, N
+The source region, the 5th, P type base, the 6th, P
+The district, the 7th, N
-The drift region, the 8th, chinampa, upper strata, the 9th, lower floor chinampa, the 10th, N
+Substrate, the 11st, the metallization drain electrode.
Fig. 5 is the common VDMOS with identical epitaxial thickness and doping content, even chinampa VDMOS and the distribution map of the electric field of non-homogeneous chinampa VDMOS when avalanche breakdown takes place.
Wherein, figure (a) is common VDMOS, and figure (b) is even chinampa VDMOS, and figure (c) is non-homogeneous chinampa VDMOS.
Fig. 6 is resistance and the Electric Field Distribution sketch map of drift region VDMOS that the non-homogeneous chinampa of n layer arranged.
L wherein
aThe width of polygate electrodes 2 among the expression half dollar born of the same parents, L
bThe width of the second conductive type semiconductor base 5 among the expression half dollar born of the same parents, Rch, R
JFET, R
DRepresent channel resistance, JFET district resistance and drift zone resistance respectively.
Fig. 7 representes common VDMOS, even chinampa VDMOS and the CURRENT DISTRIBUTION of non-homogeneous chinampa VDMOS when conducting.
Wherein (a) is common VDMOS structure, (b) is even chinampa VDMOS structure, (c) is non-homogeneous chinampa VDMOS structure.
Embodiment
A kind of VDMOS device with non-homogeneous chinampa structure; As shown in Figure 4, comprise metallization source electrode 1, polygate electrodes 2, insulating medium layer 3, the first conductive type semiconductor doping source region 4, the second conductive type semiconductor base 5, the second conductive type semiconductor doping contact zone 6, the first conductive type semiconductor doped drift region 7, the first conductive type semiconductor doped substrate 10 and metallization drain electrode 11.Metallization drain electrode 11 is positioned at the back side of the first conductive type semiconductor doped substrate 10, and the first conductive type semiconductor doped drift region 7 is positioned at the front of the first conductive type semiconductor doped substrate 10; The second conductive type semiconductor base 5 is positioned at the both sides, top of the first conductive type semiconductor doped drift region 7, has in the second conductive type semiconductor base 5 respectively and the metallization source electrode 1 contacted first conductive type semiconductor doping source region 4 and the second conductive type semiconductor doping contact zone 6; Gate dielectric layer is positioned at the upper surface of the second conductive type semiconductor base 5 and the first conductive type semiconductor doped drift region 7; Polygate electrodes 2 is positioned at the upper surface of gate dielectric layer, and what fill between polygate electrodes 2 and the metallization source electrode 1 is insulating medium layer 3.The said first conductive type semiconductor doped drift region 7 inside also have non-homogeneous chinampa structure, and said non-homogeneous chinampa structure comprises the two-layer at least second conductive type semiconductor chinampa: the second conductive type semiconductor chinampa 8 and the lower floor second conductive type semiconductor chinampa 9, upper strata; The transverse width dimension on the second conductive type semiconductor chinampa 8, said upper strata is greater than the transverse width dimension on the lower floor second conductive type semiconductor chinampa 9, and the doping content on the second conductive type semiconductor chinampa 8, said upper strata is less than the doping content on the lower floor second conductive type semiconductor chinampa 9.
When device prepared, its main technique step comprised: (1) is epitaxial growth first conductive type semiconductor layer 7 on the first conductive type semiconductor substrate; (2) inject the formation lower floor second conductive type semiconductor chinampa 9 through photoetching and ion; (3) epitaxial growth first conductive type semiconductor layer 7 once more; (4) inject the formation second conductive type semiconductor chinampa 8, upper strata through photoetching and ion; (5) epitaxial growth first conductive type semiconductor layer 7 once more; 5 photoetching of (6) second conductive type semiconductor bases and ion inject; (7) gate oxidation, the deposit polysilicon, polysilicon doping and photoetching form polygate electrodes 2; (8) photoetching and ion inject the first conductive type semiconductor source region 4; (9) photoetching and ion inject the second conductive type semiconductor contact zone 6; (10) deposit passivation layer, the fine and close and lithography fair lead of annealing; (11) depositing metal anti-carves metal, passivation, photoetching passivation hole etc.
In implementation process, can be as the case may be, under the constant situation of basic structure, carry out certain accommodation design.For example: can adopt following steps when making non-homogeneous chinampa structure: (1) is epitaxial growth first conductive type semiconductor layer on the first conductive type semiconductor substrate; (2) photoetching, high energy ion are injected and are formed the lower floor chinampa; (3) photoetching, low energy ion are injected and are formed the chinampa, upper strata.
It will be appreciated by those skilled in the art that in the technique scheme, when said first conductive type semiconductor be N type semiconductor, when second conductive type semiconductor is P type semiconductor, said VDMOS device is a N raceway groove VDMOS device; When said first conductive type semiconductor be P type semiconductor, when second conductive type semiconductor is N type semiconductor, said VDMOS device is a P raceway groove VDMOS device.
Those skilled in the art should know; VDMOS device with non-homogeneous chinampa structure provided by the invention; The doping content that can increase the chinampa number of plies, the width that changes the chinampa and spacing and change chinampa according to the needs of device parameters such as puncture voltage waits the conducting resistance of optimised devices and the relation of puncture voltage, thereby obtains the more VDMOS device of low on-resistance, higher reverse recovery characteristic.
Semi-conducting materials such as also available carborundum, GaAs, indium phosphide or germanium silicon composite replace body silicon when making device.
Claims (4)
1. the VDMOS device with non-homogeneous chinampa structure comprises metallization source electrode (1), polygate electrodes (2), insulating medium layer (3), the first conductive type semiconductor doping source region (4), the second conductive type semiconductor base (5), the second conductive type semiconductor doping contact zone (6), the first conductive type semiconductor doped drift region (7), the first conductive type semiconductor doped substrate (10) and metallization drain electrode (11); Metallization drain electrode (11) is positioned at the back side of the first conductive type semiconductor doped substrate (10), and the first conductive type semiconductor doped drift region (7) is positioned at the front of the first conductive type semiconductor doped substrate (10); The second conductive type semiconductor base (5) is positioned at the both sides, top of the first conductive type semiconductor doped drift region (7), has in the second conductive type semiconductor base (5) respectively and the metallization contacted first conductive type semiconductor doping source region (4) of source electrode (1) and the second conductive type semiconductor doping contact zone (6); Gate dielectric layer is positioned at the upper surface of the second conductive type semiconductor base (5) and the first conductive type semiconductor doped drift region (7); Polygate electrodes (2) is positioned at the upper surface of gate dielectric layer, and what fill between polygate electrodes (2) and the metallization source electrode (1) is insulating medium layer (3);
It is characterized in that; Said first conductive type semiconductor doped drift region (7) inside also has non-homogeneous chinampa structure, and said non-homogeneous chinampa structure comprises the two-layer at least second conductive type semiconductor chinampa: second conductive type semiconductor chinampa (8), upper strata and the lower floor second conductive type semiconductor chinampa (9); The transverse width dimension on the second conductive type semiconductor chinampa (8), said upper strata is greater than the transverse width dimension on the lower floor second conductive type semiconductor chinampa (9), and the doping content on the second conductive type semiconductor chinampa (8), said upper strata is less than the doping content on the lower floor second conductive type semiconductor chinampa (9).
2. according to the said VDMOS device of claim 1 with non-homogeneous chinampa structure; It is characterized in that; When said first conductive type semiconductor be N type semiconductor, when second conductive type semiconductor is P type semiconductor, said VDMOS device is a N raceway groove VDMOS device.
3. according to the said VDMOS device of claim 1 with non-homogeneous chinampa structure; It is characterized in that; When said first conductive type semiconductor be P type semiconductor, when second conductive type semiconductor is N type semiconductor, said VDMOS device is a P raceway groove VDMOS device.
4. according to the said VDMOS device of claim 1, it is characterized in that said first, second conductive type semiconductor material is body silicon, carborundum, GaAs, indium phosphide or germanium silicon composite with non-homogeneous chinampa structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103986540A CN102420251A (en) | 2011-12-05 | 2011-12-05 | VDMOS (Vertical Double-Diffusion Metal-Oxide-Semiconductor) device with non-uniform floating island structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103986540A CN102420251A (en) | 2011-12-05 | 2011-12-05 | VDMOS (Vertical Double-Diffusion Metal-Oxide-Semiconductor) device with non-uniform floating island structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102420251A true CN102420251A (en) | 2012-04-18 |
Family
ID=45944560
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011103986540A Pending CN102420251A (en) | 2011-12-05 | 2011-12-05 | VDMOS (Vertical Double-Diffusion Metal-Oxide-Semiconductor) device with non-uniform floating island structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102420251A (en) |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104810397A (en) * | 2014-01-26 | 2015-07-29 | 国家电网公司 | Super junction silicon carbide metal-oxide-semiconductor field effect transistor (MOSFET) device and manufacture method thereof |
| WO2015109929A1 (en) * | 2014-01-24 | 2015-07-30 | 无锡华润华晶微电子有限公司 | Super barrier rectifier and manufacturing method therefor |
| CN104900701A (en) * | 2015-04-18 | 2015-09-09 | 西安电子科技大学 | Silicone carbon UMOSFET device with double-area floating junction and manufacture method thereof |
| CN107482059A (en) * | 2017-08-02 | 2017-12-15 | 电子科技大学 | A kind of GaN hetero-junctions longitudinal direction is inverse to lead FET |
| CN107768443A (en) * | 2016-08-15 | 2018-03-06 | 深圳尚阳通科技有限公司 | Superjunction devices and its manufacture method |
| CN108074963A (en) * | 2016-11-16 | 2018-05-25 | 深圳尚阳通科技有限公司 | Superjunction devices and its manufacturing method |
| CN108376710A (en) * | 2018-03-20 | 2018-08-07 | 重庆大学 | Wide bandgap semiconductor VDMOSFET devices and its manufacturing method with chinampa structure |
| CN108511527A (en) * | 2018-04-08 | 2018-09-07 | 西安电子科技大学 | Vertical double-diffusion metal-oxide-semiconductor field effect transistor and preparation method thereof with charge compensation block |
| CN108538909A (en) * | 2018-04-08 | 2018-09-14 | 西安电子科技大学 | Hetero-junctions vertical double-diffusion metal-oxide-semiconductor field effect transistor and preparation method thereof with charge compensation block |
| CN109616511A (en) * | 2018-12-18 | 2019-04-12 | 深圳市威兆半导体有限公司 | A kind of design method of the VDMOS potential dividing ring of the multiple PN junction in longitudinal direction |
| CN109904230A (en) * | 2017-12-11 | 2019-06-18 | 重庆大学 | A kind of lateral direction power MOS high tension apparatus |
| CN113224164A (en) * | 2021-04-21 | 2021-08-06 | 电子科技大学 | Super junction MOS device |
| CN114695516A (en) * | 2022-03-02 | 2022-07-01 | 电子科技大学 | Semiconductor voltage-resistant layer structure |
| WO2023193288A1 (en) * | 2022-04-08 | 2023-10-12 | Hong Kong Applied Science and Technology Research Institute Company Limited | Silicon-carbide (sic) metal-oxide-semiconductor field-effect transistor (mosfet) with short circuit protection |
| CN117238914A (en) * | 2023-11-13 | 2023-12-15 | 深圳天狼芯半导体有限公司 | SiC device integrated with SBD and preparation method |
| CN117253905A (en) * | 2023-11-13 | 2023-12-19 | 深圳天狼芯半导体有限公司 | SiC device with floating island structure and preparation method thereof |
| CN117317025A (en) * | 2023-11-27 | 2023-12-29 | 北京智芯微电子科技有限公司 | Silicon carbide MOSFET device, manufacturing method and power chip |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6066878A (en) * | 1997-11-10 | 2000-05-23 | Intersil Corporation | High voltage semiconductor structure |
| US6635906B1 (en) * | 1993-10-29 | 2003-10-21 | Third Dimension (3D) Semiconductor | Voltage sustaining layer with opposite-doped islands for semi-conductor power devices |
| CN1572018A (en) * | 2001-10-04 | 2005-01-26 | 通用半导体公司 | Method for fabricating a power semiconductor device having a floating island voltage sustaining layer |
| CN101404292A (en) * | 2008-09-27 | 2009-04-08 | 电子科技大学 | VDMOS device |
| CN102097479A (en) * | 2010-12-19 | 2011-06-15 | 电子科技大学 | Low-voltage buried channel VDMOS (vertical double-diffused metal oxide semiconductor) device |
-
2011
- 2011-12-05 CN CN2011103986540A patent/CN102420251A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6635906B1 (en) * | 1993-10-29 | 2003-10-21 | Third Dimension (3D) Semiconductor | Voltage sustaining layer with opposite-doped islands for semi-conductor power devices |
| US6066878A (en) * | 1997-11-10 | 2000-05-23 | Intersil Corporation | High voltage semiconductor structure |
| CN1572018A (en) * | 2001-10-04 | 2005-01-26 | 通用半导体公司 | Method for fabricating a power semiconductor device having a floating island voltage sustaining layer |
| CN101404292A (en) * | 2008-09-27 | 2009-04-08 | 电子科技大学 | VDMOS device |
| CN102097479A (en) * | 2010-12-19 | 2011-06-15 | 电子科技大学 | Low-voltage buried channel VDMOS (vertical double-diffused metal oxide semiconductor) device |
Cited By (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015109929A1 (en) * | 2014-01-24 | 2015-07-30 | 无锡华润华晶微电子有限公司 | Super barrier rectifier and manufacturing method therefor |
| CN104810397B (en) * | 2014-01-26 | 2018-01-09 | 国家电网公司 | A kind of super junction silicon carbide MOSFET device and preparation method thereof |
| CN104810397A (en) * | 2014-01-26 | 2015-07-29 | 国家电网公司 | Super junction silicon carbide metal-oxide-semiconductor field effect transistor (MOSFET) device and manufacture method thereof |
| CN104900701A (en) * | 2015-04-18 | 2015-09-09 | 西安电子科技大学 | Silicone carbon UMOSFET device with double-area floating junction and manufacture method thereof |
| CN104900701B (en) * | 2015-04-18 | 2018-07-03 | 西安电子科技大学 | Silicon carbide UMOSFET devices and production method with two-region floating junction |
| CN107768443A (en) * | 2016-08-15 | 2018-03-06 | 深圳尚阳通科技有限公司 | Superjunction devices and its manufacture method |
| CN107768443B (en) * | 2016-08-15 | 2020-12-08 | 深圳尚阳通科技有限公司 | Super junction device and manufacturing method thereof |
| CN108074963A (en) * | 2016-11-16 | 2018-05-25 | 深圳尚阳通科技有限公司 | Superjunction devices and its manufacturing method |
| CN107482059A (en) * | 2017-08-02 | 2017-12-15 | 电子科技大学 | A kind of GaN hetero-junctions longitudinal direction is inverse to lead FET |
| CN107482059B (en) * | 2017-08-02 | 2020-01-17 | 电子科技大学 | Vertical reverse conducting field effect transistor of gaN heterojunction |
| CN109904230A (en) * | 2017-12-11 | 2019-06-18 | 重庆大学 | A kind of lateral direction power MOS high tension apparatus |
| CN108376710A (en) * | 2018-03-20 | 2018-08-07 | 重庆大学 | Wide bandgap semiconductor VDMOSFET devices and its manufacturing method with chinampa structure |
| CN108538909A (en) * | 2018-04-08 | 2018-09-14 | 西安电子科技大学 | Hetero-junctions vertical double-diffusion metal-oxide-semiconductor field effect transistor and preparation method thereof with charge compensation block |
| CN108511527A (en) * | 2018-04-08 | 2018-09-07 | 西安电子科技大学 | Vertical double-diffusion metal-oxide-semiconductor field effect transistor and preparation method thereof with charge compensation block |
| CN109616511A (en) * | 2018-12-18 | 2019-04-12 | 深圳市威兆半导体有限公司 | A kind of design method of the VDMOS potential dividing ring of the multiple PN junction in longitudinal direction |
| CN113224164A (en) * | 2021-04-21 | 2021-08-06 | 电子科技大学 | Super junction MOS device |
| CN113224164B (en) * | 2021-04-21 | 2022-03-29 | 电子科技大学 | Super junction MOS device |
| CN114695516A (en) * | 2022-03-02 | 2022-07-01 | 电子科技大学 | Semiconductor voltage-resistant layer structure |
| WO2023193288A1 (en) * | 2022-04-08 | 2023-10-12 | Hong Kong Applied Science and Technology Research Institute Company Limited | Silicon-carbide (sic) metal-oxide-semiconductor field-effect transistor (mosfet) with short circuit protection |
| CN117238914A (en) * | 2023-11-13 | 2023-12-15 | 深圳天狼芯半导体有限公司 | SiC device integrated with SBD and preparation method |
| CN117253905A (en) * | 2023-11-13 | 2023-12-19 | 深圳天狼芯半导体有限公司 | SiC device with floating island structure and preparation method thereof |
| CN117317025A (en) * | 2023-11-27 | 2023-12-29 | 北京智芯微电子科技有限公司 | Silicon carbide MOSFET device, manufacturing method and power chip |
| CN117317025B (en) * | 2023-11-27 | 2024-03-08 | 北京智芯微电子科技有限公司 | Silicon carbide MOSFET device, manufacturing method and power chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102420251A (en) | VDMOS (Vertical Double-Diffusion Metal-Oxide-Semiconductor) device with non-uniform floating island structure | |
| CN105047712B (en) | Vertical gate semiconductor device and its manufacturing method | |
| CN101969073B (en) | Rapid superjunction longitudinal double-diffusion metal oxide semiconductor transistor | |
| CN104201206B (en) | A kind of laterally SOI power LDMOS device | |
| CN101950759A (en) | Super Junction VDMOS device | |
| CN102184939B (en) | Semiconductor power device with high-K medium tank | |
| CN108899370B (en) | VDMOS device integrated with resistor area | |
| CN102194879A (en) | Semiconductor device | |
| CN103219386B (en) | A kind of lateral power with high K insulation layer | |
| CN103268890A (en) | Power LDMOS device with junction field plate | |
| CN103280457B (en) | A kind of horizontal high voltage power device of Ultra-low Specific conducting resistance and manufacture method | |
| CN103579353B (en) | Half hyperconjugation VDMOS of buried regions assisted by a kind of P of having type | |
| CN103715238A (en) | Transverse high-voltage component with ultra-low specific on-resistance | |
| US20230053369A1 (en) | Soi lateral homogenization field high voltage power semiconductor device, manufacturing method and application thereof | |
| CN102376762A (en) | Super junction LDMOS(Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof | |
| CN102412297A (en) | Silicon-based power device structure based on substrate bias technology | |
| CN103474466A (en) | High-voltage device and manufacturing method thereof | |
| CN102723363A (en) | VDMOS device and manufacturing method thereof | |
| CN102097478A (en) | Extremely-low on resistance shallow slot buried channel VDMOS (vertical double diffusion metal oxide semiconductor) device | |
| CN105993076A (en) | Bi-directional MOS device and manufacturing method thereof | |
| CN103022134A (en) | Silicon on insulator (SOI) transverse high voltage power device with ultralow specific on resistance | |
| CN106356401A (en) | Field limiting ring terminal structure for power semiconductor device | |
| CN104851915A (en) | Trench-gate type compound semiconductor power VDMOS device and method for raising puncture voltage thereof | |
| CN110164975A (en) | A kind of accumulation type silicon carbide power MOSFET element | |
| CN103413831A (en) | Horizontal high-voltage device and manufacturing method of horizontal high-voltage device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: INSTITUTE OF ELECTRONIC AND INFORMATION ENGINEERIN Effective date: 20130326 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20130326 Address after: 611731 Chengdu province high tech Zone (West) West source Avenue, No. 2006 Applicant after: University of Electronic Science and Technology of China Applicant after: Institute of Electronic and Information Engineering In Dongguan, UESTC Address before: 611731 Chengdu province high tech Zone (West) West source Avenue, No. 2006 Applicant before: University of Electronic Science and Technology of China |
|
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20120418 |