CN107768443B - Super junction device and manufacturing method thereof - Google Patents
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Abstract
The invention discloses a super junction device, wherein an N-type electric field blocking layer is arranged in a P-type column of at least one super junction unit, and the P-type column is divided into a first P-type column and a second P-type column which are positioned at the top and the bottom of the electric field blocking layer by the N-type electric field blocking layer in the longitudinal direction; the N-type electric field blocking layer is used for realizing segmented depletion of the top and bottom super junction structures; when the source-drain voltage of the super junction device is less than or equal to a first voltage value, only the top super junction structure is depleted; when the source-drain voltage of the super junction device is larger than the first voltage value, depletion of the super junction structure at the top and the bottom occurs. The invention also discloses a manufacturing method of the super junction device. The invention can improve the gate-drain capacitance and the minimum value of the gate-drain capacitance, thereby effectively reducing the electromagnetic interference performance of the device in an application circuit, effectively reducing the overshoot of current and voltage brought by the device in the application circuit, increasing the softness factor of reverse recovery of the device, and keeping the breakdown voltage of the device.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a super junction (junction) device; the invention also relates to a manufacturing method of the super junction device.
Background
The super junction structure is a structure formed by alternately arranged N-type columns and P-type columns. If a super junction structure is used for replacing an N-type drift region in a Vertical Double-diffused Metal-Oxide-Semiconductor (VDMOS) device, a conduction path is provided through an N-type column in a conduction state, and the P-type column does not provide the conduction path when the conduction state is conducted; under the cut-off state, the PN upright posts bear the reverse bias voltage together, so that a super-junction Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is formed. The super-junction MOSFET can greatly reduce the on-resistance of the device by using an epitaxial layer with low resistivity under the condition that the reverse breakdown voltage is consistent with that of a traditional VDMOS device.
As shown in fig. 1, is a schematic diagram of a prior art superjunction device, which is a schematic cross-sectional diagram; taking the super junction device as a planar gate super junction N-type MOSFET device as an example, the super junction device comprises:
an N-type epitaxial layer 30 is formed on an N-type heavily doped semiconductor substrate 1, N-type columns 3 and P-type columns 4 are formed in the N-type epitaxial layer 30, the N-type columns 3 and the P-type columns 4 are alternately arranged to form a super junction structure, the N-type epitaxial layer 30 at the bottom of the super junction structure forms an N-type buffer layer 30, the impurity concentration of the N-type buffer layer 30 is the same as that of the N-type columns 3 or higher or lower than that of the N-type columns 3, and the semiconductor substrate 1 with high impurity concentration (higher than 1e19 atomic number/cubic centimeter) is arranged below the N-type buffer layer 30.
A super junction unit is formed by an N-type column 3 and a P-type column 4, and an original cell structure of a super junction device is formed in each super junction unit.
A P-type well 7 is formed at the top of the P-type column 4, a source region 8 consisting of an N + region and a P-well lead-out region 9 consisting of a P + region are formed in the P-type well 7, and a gate dielectric layer such as a gate oxide layer 5 and a polysilicon gate 6 is formed on the surface of the P-type well 7.
The interlayer film 10, the contact hole 11, the front metal layer 12 and the front metal layer 12 are patterned to respectively lead out a source electrode and a grid electrode. The drain region is formed by directly or further doping the thinned heavily doped semiconductor substrate 1, a back metal layer 13 is formed on the back of the semiconductor substrate 1, and the drain electrode is led out of the back metal layer 13.
In fig. 1, an interface C1C2 is the bottom surface of the thinned semiconductor substrate 1, an interface B1B2 is the top surface of the semiconductor substrate 1, an interface A1a2 is the bottom interface of the super junction structure, and an interface M1M2 is the top surface of the N-type epitaxial layer 30. The thickness between the interface C1C2 and the interface B1B2 is T00, the thickness between the interface C1C2 and the interface M1M2 is T10, the thickness between the interface A1a2 and the interface M1M2 is T20, and the thickness between the interface A1a2 and the interface B1B2 is T30.
As shown in fig. 1, a polysilicon gate 6 is disposed above each N-type column 3, the polysilicon gate 6 may partially cover the peripheral P-type columns 4 or not, a P-type well 7 is disposed above each P-type column 4, an N + source region 8 is disposed in the P-type well 7, a contact hole 11 is provided, source metal is connected to the source region 8 through the contact hole 11, and metal in the source region 8 is connected to the P-type well 7 through a high-concentration P-well lead-out region 9.
The upper part of the P-type column 4 of the device is connected to the source region 8 electrode through a contact hole 11, and the N-type column 2 is connected to the drain 13 through an N + substrate, i.e., a semiconductor substrate 11. At a low Vds, i.e., a source-drain voltage, the Vds basically applies a transverse electric field between the P-type pillars 4 and the N-type pillars 3, so that at a very low Vds, the alternately arranged P-type pillars 4 and N-type pillars 3 are quickly depleted under the action of the transverse electric field.
When the Vds voltage is increased from 0 to a certain value, for example, less than 50V, the P-type columns 4 and the N-type columns 3 of the device are completely depleted, and if the P-type columns 4 and the N-type columns 3 achieve a desired balance (the amount of N-type impurities is equal to the amount of P-type impurities) at each lateral position, the electric field intensity of the N-type drift region is distributed as shown in fig. 2, and the N-type drift region is composed of an N-type epitaxial layer directly located between the source region 8 and the drain region 1, including the N-type columns 3 and the bottom N-type buffer layer 30, corresponding to the N-type epitaxial layer between the interface M1M2 and the interface B1B2 in fig. 1. The electric field strength increases with increasing Vds until the maximum electric field strength reaches Ec, at which time avalanche breakdown of the device occurs, which is the breakdown voltage BVds of the device.
Because the alternately arranged P-type columns 4 and N-type columns 3 are quickly depleted under the action of a transverse electric field under the condition of very low Vds, the capacitance Crss, namely Cgd of the device has very large nonlinearity under the condition of small Vds, and Crss is a reverse transmission capacitance and is Cgd; for the super junction with the step of the N-P column, i.e. the P-type column 4 and the N-type column 3, being smaller than 12 micrometers, when Vds is changed from 0V to 20V, there is a sharp drop process for the Crss of the device, so that during the switching process of the super junction MOSFET, too fast switching process due to too low Crss is liable to occur, so that the electromagnetic interference of the application system of the device is large, and even the circuit is failed due to the overshoot of current and voltage, for the following reasons: in the process of changing the device from an on state to a reverse off state, due to the fact that adjacent P-type columns 4 and N-type columns 3 are laterally depleted and the N-type columns 3 are partially or completely depleted at a certain voltage, Csi becomes very small after the adjacent P-type columns 4 and N-type columns 3 are laterally depleted due to the fact that Cgd is the series connection of Cox and Csi, Cgd of the device at the moment becomes very small, and dVds/dt is Igp/Cgd (Vds), wherein Vds is drain-source voltage, Igp is gate current at platform voltage, and Vds/dt becomes very large at the voltage, so that good electromagnetic interference occurs in a circuit or a system using the device, and normal operation of the circuit or the system is affected; this is also the case during the change from the high-voltage reverse off state to the on state. In addition to oscillations in the applied loop, this excessive ddds/dt during switching can also cause excessive current and voltage overshoots in the applied system, resulting in circuit damage.
On the other hand, for a high voltage device, such as a BVds 600V device, during most of the off-time in a practical circuit, vds is less than 500V, or lower, particularly in bridge circuits or some other circuit, in a certain state, forward conduction is carried out on S/D of the MOSFET, namely a parasitic body diode between a source and a drain, namely a parasitic diode formed between the P-type well 7 and the drift region, and then reverse recovery (reverse recovery) occurs, when the voltage between DS reaches Vdd (typically not more than 400V), the current of the diode reaches the maximum reverse current value (Irrm), followed by reverse recovery, it is desirable to reduce current and voltage oscillations in the circuit during reverse recovery, and it is desirable that the reverse current recovery process of the device be as soft as possible, and to obtain a good softness factor, it is desirable to have a large carrier residue in the N-type drift region. However, in the conventional structure, since the carriers in the N-P column are completely depleted when Vds is less than 50V, even if the operating voltage Vdd is as low as 200V V-300V, the carriers remaining after the device voltage reaches Vdd are only a part of the carriers in the part of the N-type buffer layer 30 below the N-P column, and thus the softness factor of the device body diode in reverse recovery cannot be improved.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a super junction device, which can improve the gate-drain capacitance and the minimum value of the gate-drain capacitance, thereby effectively reducing the electromagnetic interference performance of the device in an application circuit, effectively reducing the overshoot of current and voltage brought by the device in the application circuit, and increasing the softness factor of the reverse recovery of the device. Therefore, the invention also provides a manufacturing method of the super junction device.
In order to solve the technical problem, the charge flowing area of the super junction device provided by the invention comprises a super junction structure consisting of a plurality of alternately arranged N-type columns and P-type columns; each of the N-type columns and the P-type column adjacent thereto constitute one super junction cell.
The P-type column of at least one super junction unit is provided with an N-type electric field blocking layer, and the P-type column is divided into a first P-type column positioned at the top of the N-type electric field blocking layer and a second P-type column positioned at the bottom of the N-type electric field blocking layer by the N-type electric field blocking layer in the longitudinal direction.
The first P-type columns and the adjacent N-type columns are alternately arranged to form a top super junction structure; the second P-type columns and the adjacent N-type columns are alternately arranged to form a bottom super junction structure; the N-type electric field blocking layer is used for realizing segmented depletion of the top super junction structure and the bottom super junction structure.
When the source-drain voltage of the super-junction device is smaller than or equal to a first voltage value, only the top super-junction structure is depleted, the electric field is stopped in the N-type electric field blocking layer, and the bottom super-junction structure is not depleted.
And when the source-drain voltage of the super junction device is greater than the first voltage value, the top super junction structure is completely depleted, and the electric field continues to deplete the bottom super junction structure after passing through the N-type electric field blocking layer.
The first voltage value is required to be more than or equal to the working voltage of the super junction device and less than the breakdown voltage of the super junction device, so that the super junction device is only depleted in the top super junction structure during working, the gate leakage capacitance is improved, and meanwhile, carriers can be provided during reverse recovery of the device by utilizing the characteristic that the bottom super junction structure is not depleted, and the reverse recovery softness factor of the device is increased; the breakdown voltage of the superjunction device is determined by a depletion region formed when both the top superjunction structure and the bottom superjunction structure are fully depleted.
In a further improvement, the first voltage value is determined by the voltage endurance capability of the top super junction structure, the larger the voltage endurance capability of the top super junction structure is, the larger the first voltage value is, and the smaller the voltage endurance capability of the top super junction structure is, the smaller the first voltage value is.
In a further improvement, the smaller the thickness of the top superjunction structure, the smaller the first voltage value.
The further improvement is that the larger the thickness of the bottom super junction structure is, the larger the reverse recovery softness of the super junction device is.
In a further improvement, the first P-type pillar is charge balanced with the adjacent N-type pillar.
Charge balance between the second P-type pillar and the adjacent N-type pillar; or the total impurity amount of the second P-type column is larger than that of the adjacent N-type column; or the total impurity amount of the second P-type column is less than that of the adjacent N-type column.
In a further improvement, the doping concentration of the N-type electric field blocking layer is 2 to 10 times of the maximum doping concentration of the first P-type column and the second P-type column.
The further improvement is that the thickness of the N-type electric field blocking layer is 1-5 microns.
In a further improvement, two sides of the N-type electric field blocking layer corresponding to each P-type column are in contact with the N-type column, and the width of each N-type electric field blocking layer is greater than or equal to the width of the corresponding first P-type column and the second P-type column; or the N-type electric field blocking layers of the super junction units with the N-type electric field blocking layers are connected into a whole.
In a further improvement, the thickness of the first P-type pillar is greater than the thickness of the second P-type pillar.
The further improvement is that the thickness of the second P-type column is 2-20 microns; the second P-type column is formed by ion implantation or diffusion, or the second P-type column is formed by trench filling.
The further improvement is that the super-junction structure is formed on an N-type epitaxial layer, an N-type buffer layer composed of the N-type epitaxial layer is formed at the bottom of the super-junction structure, and a heavily doped N-type semiconductor substrate is arranged at the bottom of the N-type buffer layer.
In order to solve the technical problem, in the manufacturing method of the super junction device provided by the invention, a charge flowing area of the super junction device comprises a super junction structure consisting of a plurality of alternately arranged N-type columns and P-type columns; each N-type column and the adjacent P-type column form a super junction unit; the P-type column of at least one super junction unit is provided with an N-type electric field blocking layer, and the super junction unit with the N-type electric field blocking layer is formed by the following steps:
step one, providing an N-type epitaxial layer, and forming a groove in the N-type epitaxial layer by adopting a photoetching process, wherein the depth of the groove is the same as that of the first P-type column.
Step two, carrying out first P-type ion implantation to form a second P-type column at the bottom of the groove; and performing second N-type ion implantation to form an N-type electric field blocking layer at the bottom of the groove, wherein the N-type electric field blocking layer is positioned at the top of the second P-type column.
Filling P-type silicon in the groove to form a first P-type column; the first P-type column and the second P-type column are longitudinally superposed to form the P-type column divided by the N-type electric field blocking layer; the N-type columns are composed of the N-type epitaxial layer between the P-type columns.
The first P-type columns and the adjacent N-type columns are alternately arranged to form a top super junction structure; the second P-type columns and the adjacent N-type columns are alternately arranged to form a bottom super junction structure; the N-type electric field blocking layer is used for realizing segmented depletion of the top super junction structure and the bottom super junction structure.
When the source-drain voltage of the super-junction device is smaller than or equal to a first voltage value, only the top super-junction structure is depleted, the electric field is stopped in the N-type electric field blocking layer, and the bottom super-junction structure is not depleted.
And when the source-drain voltage of the super junction device is greater than the first voltage value, the top super junction structure is completely depleted, and the electric field continues to deplete the bottom super junction structure after passing through the N-type electric field blocking layer.
The first voltage value is required to be more than or equal to the working voltage of the super junction device and less than the breakdown voltage of the super junction device, so that the super junction device is only depleted in the top super junction structure during working, the gate leakage capacitance is improved, and meanwhile, carriers can be provided during reverse recovery of the device by utilizing the characteristic that the bottom super junction structure is not depleted, and the reverse recovery softness factor of the device is increased; the breakdown voltage of the superjunction device is determined by a depletion region formed when both the top superjunction structure and the bottom superjunction structure are fully depleted.
In order to solve the technical problem, in the manufacturing method of the super junction device provided by the invention, a charge flowing area of the super junction device comprises a super junction structure consisting of a plurality of alternately arranged N-type columns and P-type columns; each N-type column and the adjacent P-type column form a super junction unit; the P-type column of at least one super junction unit is provided with an N-type electric field blocking layer, and the super junction unit with the N-type electric field blocking layer is formed by the following steps:
step one, providing a first N-type epitaxial layer, carrying out photoetching and P-type ion implantation on a first layer of P-type area on the first N-type epitaxial layer, and forming a first layer of N-type area by the first N-type epitaxial layer between the first layer of P-type area.
Step two, forming a second intrinsic epitaxial layer on the first N-type epitaxial layer; photoetching and P-type ion implantation are carried out on a second P-type region on the second intrinsic epitaxial layer, and photoetching and N-type ion implantation are carried out on a second N-type region on the second intrinsic epitaxial layer; the second layer of P-type region is superposed on the first P-type region, and the second N-type region is superposed on the first N-type region.
Step three, repeating the step two to form more layers of P-type regions and N-type regions, wherein the P-type regions of all the layers are overlapped to form a second P-type column, and the N-type regions of all the layers are also overlapped together; repeating the second step for 0 times or more than 1 time until the thickness of the second P-type column meets the requirement.
And step four, forming an N-type electric field blocking layer on the top of the second P-type column by adopting photoetching and N-type ion implantation.
Fifthly, growing an epitaxial layer to form a third N-type epitaxial layer; forming a groove in the third N-type epitaxial layer by adopting a photoetching process, wherein the N-type electric field blocking layer is exposed out of the bottom of the groove; filling P-type silicon in the groove to form a first P-type column; the first P-type column and the second P-type column are longitudinally superposed to form the P-type column divided by the N-type electric field blocking layer; the N-type columns are formed by overlapping N-type regions among the P-type columns and the third N-type epitaxial layer.
The first P-type columns and the adjacent N-type columns are alternately arranged to form a top super junction structure; the second P-type columns and the adjacent N-type columns are alternately arranged to form a bottom super junction structure; the N-type electric field blocking layer is used for realizing segmented depletion of the top super junction structure and the bottom super junction structure.
When the source-drain voltage of the super-junction device is smaller than or equal to a first voltage value, only the top super-junction structure is depleted, the electric field is stopped in the N-type electric field blocking layer, and the bottom super-junction structure is not depleted.
And when the source-drain voltage of the super junction device is greater than the first voltage value, the top super junction structure is completely depleted, and the electric field continues to deplete the bottom super junction structure after passing through the N-type electric field blocking layer.
The first voltage value is required to be more than or equal to the working voltage of the super junction device and less than the breakdown voltage of the super junction device, so that the super junction device is only depleted in the top super junction structure during working, the gate leakage capacitance is improved, and meanwhile, carriers can be provided during reverse recovery of the device by utilizing the characteristic that the bottom super junction structure is not depleted, and the reverse recovery softness factor of the device is increased; the breakdown voltage of the superjunction device is determined by a depletion region formed when both the top superjunction structure and the bottom superjunction structure are fully depleted.
In order to solve the technical problem, the invention provides a method for manufacturing a super junction device, wherein a charge flowing area of the super junction device comprises a super junction structure consisting of a plurality of alternately arranged N-type columns and P-type columns; each N-type column and the adjacent P-type column form a super junction unit; the P-type column of at least one super junction unit is provided with an N-type electric field blocking layer, and the super junction unit with the N-type electric field blocking layer is formed by the following steps:
step one, providing a first N-type epitaxial layer; forming a first groove in the first N-type epitaxial layer by adopting a photoetching process; and filling P-type silicon in the first groove to form a second P-type column.
Growing an epitaxial layer to form a second N-type epitaxial layer; and forming a second groove in the second N-type epitaxial layer by adopting a photoetching process, wherein the second groove is aligned to the second P-type column at the bottom and exposes the surface of the second P-type column.
And performing N-type ion implantation to form an N-type electric field blocking layer at the bottom of the second trench, wherein the N-type electric field blocking layer is positioned at the top of the second P-type column.
Filling P-type silicon in the second groove to form a first P-type column; the first P-type column and the second P-type column are longitudinally superposed to form the P-type column divided by the N-type electric field blocking layer; the N-type columns are formed by overlapping the first N-type epitaxial layer and the second N-type epitaxial layer between the P-type columns.
The first P-type columns and the adjacent N-type columns are alternately arranged to form a top super junction structure; the second P-type columns and the adjacent N-type columns are alternately arranged to form a bottom super junction structure; the N-type electric field blocking layer is used for realizing segmented depletion of the top super junction structure and the bottom super junction structure.
When the source-drain voltage of the super-junction device is smaller than or equal to a first voltage value, only the top super-junction structure is depleted, the electric field is stopped in the N-type electric field blocking layer, and the bottom super-junction structure is not depleted.
And when the source-drain voltage of the super junction device is greater than the first voltage value, the top super junction structure is completely depleted, and the electric field continues to deplete the bottom super junction structure after passing through the N-type electric field blocking layer.
The first voltage value is required to be more than or equal to the working voltage of the super junction device and less than the breakdown voltage of the super junction device, so that the super junction device is only depleted in the top super junction structure during working, the gate leakage capacitance is improved, and meanwhile, carriers can be provided during reverse recovery of the device by utilizing the characteristic that the bottom super junction structure is not depleted, and the reverse recovery softness factor of the device is increased; the breakdown voltage of the superjunction device is determined by a depletion region formed when both the top superjunction structure and the bottom superjunction structure are fully depleted.
In order to solve the technical problem, in the manufacturing method of the super junction device provided by the invention, a charge flowing area of the super junction device comprises a super junction structure consisting of a plurality of alternately arranged N-type columns and P-type columns; each N-type column and the adjacent P-type column form a super junction unit; the P-type column of at least one super junction unit is provided with an N-type electric field blocking layer, and the super junction unit with the N-type electric field blocking layer is formed by the following steps:
step one, providing a first N-type epitaxial layer; forming a first groove in the first N-type epitaxial layer by adopting a photoetching process; filling P-type silicon in the first groove to form a second P-type column; and carrying out N-type ion implantation to form an N-type electric field blocking layer at the top of the second P-type column.
Growing an epitaxial layer to form a second N-type epitaxial layer; and forming a second groove in the second N-type epitaxial layer by adopting a photoetching process, wherein the second groove is aligned to the second P-type column at the bottom and exposes the N-type electric field blocking layer.
Filling P-type silicon in the second groove to form a first P-type column; the first P-type column and the second P-type column are longitudinally superposed to form the P-type column divided by the N-type electric field blocking layer; the N-type columns are formed by overlapping the first N-type epitaxial layer and the second N-type epitaxial layer between the P-type columns;
the first P-type columns and the adjacent N-type columns are alternately arranged to form a top super junction structure; the second P-type columns and the adjacent N-type columns are alternately arranged to form a bottom super junction structure; the N-type electric field blocking layer is used for realizing segmented depletion of the top super junction structure and the bottom super junction structure.
When the source-drain voltage of the super-junction device is smaller than or equal to a first voltage value, only the top super-junction structure is depleted, the electric field is stopped in the N-type electric field blocking layer, and the bottom super-junction structure is not depleted.
And when the source-drain voltage of the super junction device is greater than the first voltage value, the top super junction structure is completely depleted, and the electric field continues to deplete the bottom super junction structure after passing through the N-type electric field blocking layer.
The first voltage value is required to be more than or equal to the working voltage of the super junction device and less than the breakdown voltage of the super junction device, so that the super junction device is only depleted in the top super junction structure during working, the gate leakage capacitance is improved, and meanwhile, carriers can be provided during reverse recovery of the device by utilizing the characteristic that the bottom super junction structure is not depleted, and the reverse recovery softness factor of the device is increased; the breakdown voltage of the superjunction device is determined by a depletion region formed when both the top superjunction structure and the bottom superjunction structure are fully depleted.
The invention can obtain the following beneficial effects:
according to the invention, the P-type column is longitudinally segmented by adding the N-type electric field blocking layer, segmented depletion of the top super-junction structure and the bottom super-junction structure after longitudinal segmentation can be realized, when the source-drain voltage of the super-junction device is greater than a first voltage value, the bottom super-junction structure begins to be depleted, when the source-drain voltage is less than or equal to the first voltage value, only the top super-junction structure is depleted, and the first voltage value is required to be greater than or equal to the working voltage of the super-junction device and less than the breakdown voltage of the super-junction device, so that only the top super-junction structure is depleted when the super-junction device works, the gate leakage capacitance is improved, the minimum value of the gate leakage capacitance is improved, the electromagnetic interference performance of the device in an application circuit is effectively reduced, and overshoot of current and voltage brought by the device in the application circuit is effectively reduced.
Meanwhile, the characteristic that the bottom super-junction structure is not depleted when the super-junction device works is utilized, so that the bottom super-junction structure provides current carriers when the device is reversely recovered, the reverse recovery softness factor of the device is increased, and the current and voltage oscillation in a circuit can be expected to be reduced in the reverse recovery process.
In addition, the breakdown voltage of the super junction device is determined by a depletion region formed when the top super junction structure and the bottom super junction structure are completely depleted, and compared with the existing structure, the breakdown voltage of the super junction device can be well maintained.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a schematic diagram of an existing superjunction device;
fig. 2 is a schematic diagram of electric field intensity distribution of a drift region of a conventional super junction device;
fig. 3 is a schematic diagram of a superjunction device of an embodiment of the present invention;
fig. 4A is a schematic diagram of electric field intensity distribution of a drift region of a super junction device when a source-drain voltage is less than or equal to a first voltage value according to an embodiment of the present invention;
fig. 4B is a schematic diagram of electric field intensity distribution of the drift region of the super junction device in the embodiment of the present invention when the source-drain voltage is greater than the first voltage value;
fig. 4C is a schematic diagram of electric field intensity distribution of the drift region of the second superjunction device in the embodiment of the present invention when the source-drain voltage is greater than the first voltage value;
fig. 4D is a schematic diagram of electric field intensity distribution of the drift region of the triple super junction device in the embodiment of the present invention when the source-drain voltage is greater than the first voltage value;
fig. 4E is a gate-drain capacitance curve of a superjunction device according to an embodiment of the present invention and a gate-drain capacitance curve of the conventional superjunction device shown in fig. 1 for comparison;
fig. 5 is a schematic diagram of a four superjunction device of an embodiment of the present invention;
fig. 6 is a schematic diagram of a five superjunction device of an embodiment of the present invention;
fig. 7 is a schematic diagram of a six superjunction device of an embodiment of the present invention.
Detailed Description
The embodiment of the invention discloses a super junction device:
fig. 3 is a schematic diagram of a superjunction device according to an embodiment of the present invention; in the first embodiment of the present invention:
the charge flowing region comprises a super junction structure consisting of a plurality of alternately arranged N-type columns 3 and P-type columns; each of the N-type columns 3 and the P-type columns adjacent thereto constitute one super junction cell.
The super junction structure is formed on an N-type epitaxial layer, an N-type buffer layer 30 composed of the N-type epitaxial layer is formed at the bottom of the super junction structure, and a heavily doped N-type semiconductor substrate 1 is arranged at the bottom of the N-type buffer layer 30.
An N-type electric field blocking layer 31 is arranged in the P-type column of at least one super junction unit, and the N-type electric field blocking layer 31 is included in all the P-type columns shown in fig. 3. The N-type electric field blocking layer 31 divides the P-type columns in the longitudinal direction into first P-type columns 41 located at the top of the N-type electric field blocking layer 31 and second P-type columns 42 located at the bottom of the N-type electric field blocking layer 31.
The first P-type columns 41 and the adjacent N-type columns 3 are alternately arranged to form a top super junction structure; the second P-type columns 42 and the adjacent N-type columns 3 are alternately arranged to form a bottom super junction structure.
In fig. 3, an interface M1M2 is a top surface of the entire super junction structure, that is, a top surface of the top super junction structure, an interface D1D2 is a bottom surface of the top super junction structure, an interface E1E2 is a top surface of the bottom super junction structure, an interface A1a2 is a bottom surface of the bottom super junction structure, that is, a bottom surface of the entire super junction structure, an interface C1C2 is a bottom surface of the thinned semiconductor substrate 1, and an interface B1B2 is a top surface of the semiconductor substrate 1. The thickness between the interface C1C2 and the interface B1B2, that is, the thickness of the thinned semiconductor substrate 1 is T00, the thickness between the interface A1a2 and the interface B1B2, that is, the thickness of the N-type buffer layer 30 is T30, the thickness between the interface A1a2 and the interface M1M2 is T20, and the thickness between the interface D1D2 and the interface M1M2 is T201. A top super junction structure region is formed between the interface M1M2 and the interface D1D2, a region of the N-type electric field blocking layer 31 is formed between the interface D1D2 and the interface E1E2, and a bottom super junction structure region is formed between the interface E1E2 and the interface A1a 2.
The N-type electric field blocking layer 31 is used for realizing segmented depletion of the top super junction structure and the bottom super junction structure. Preferably, the doping concentration of the N-type electric field blocking layer 31 is 2 to 10 times the maximum doping concentration of the first and second P- type columns 41 and 42. The thickness of the N-type electric field blocking layer 31 is 1-5 microns. Both sides of the N-type electric field blocking layer 31 corresponding to each P-type column are in contact with the N-type column 3, and the width of each N-type electric field blocking layer 31 is greater than or equal to the width of the corresponding first P-type column 41 and second P-type column 42.
The thickness of the first P-type pillar 41 is greater than the thickness of the second P-type pillar 42. Preferably, the thickness of the second P-type pillar 42 is 2 to 20 micrometers; the second P-type columns 42 are formed by ion implantation or diffusion. In the first embodiment of the present invention shown in fig. 3, the first P-type column 41 is formed by a trench filling process, and the N-type electric field blocking layer 31 and the second P-type column 42 are formed by ion implantation after the formation of the trench corresponding to the first P-type column 41.
In the first embodiment of the present invention, the charge balance between the first P-type pillar 41 and the adjacent N-type pillar 3 means that the total amount of impurities between the first P-type pillar 41 and the adjacent N-type pillar 3 is the same. The total amount of impurities of the second P-type column 42 is larger than that of the adjacent N-type column 3.
When the source-drain voltage of the super junction device is less than or equal to a first voltage value, only the top super junction structure is depleted, the electric field is terminated in the N-type electric field blocking layer 31, and the bottom super junction structure is not depleted. As shown in fig. 4A, a schematic diagram of electric field intensity distribution of a drift region of a super junction device in an embodiment of the present invention when a source-drain voltage is equal to or lower than a first voltage value, where the source-drain voltages Vds1, Vds2, Vds3, and Vds4 are gradually increased and are all smaller than the first voltage value, it can be seen that an electric field is only located between interfaces M1M2 and D1D2, that is, only a top super junction structure is depleted, and the electric field does not pass through the N-type electric field blocking layer 31 and enter a bottom super junction structure, so that the bottom super junction structure is not depleted.
When the source-drain voltage of the super junction device is greater than the first voltage value, the top super junction structure is completely depleted, and the electric field continues to deplete the bottom super junction structure after passing through the N-type electric field blocking layer 31. As shown in fig. 4B, which is a schematic diagram of distribution of electric field intensity of a drift region of a super junction device in an embodiment of the present invention when a source-drain voltage is greater than a first voltage value, because the total amount of impurities of the second P-type column 42 is set to be greater than the total amount of impurities adjacent to the N-type column 3 in the first embodiment of the present invention, the electric field intensity may drop in the N-type electric field blocking layer 31, and after passing through the N-type electric field blocking layer 31, the electric field intensity may rise between the interface E1E2 and the interface A1a2, that is, between bottom super junction structure regions, and finally drop to 0 in the N-type buffer layer 30; it is noted that the magnitude of the increase in electric field strength between the bottom superjunction structure regions needs to be controlled so that the maximum electric field strength occurs between E1E2 and A1a2, which would otherwise affect the EAS capability of the device to be extremely consistent.
The first voltage value is required to be more than or equal to the working voltage of the super junction device and less than the breakdown voltage of the super junction device, so that the super junction device is only depleted in the top super junction structure during working, the gate leakage capacitance (Cgd) is improved, and carriers can be provided during reverse recovery of the device by utilizing the characteristic that the bottom super junction structure is not depleted, so that the reverse recovery softness factor of the device is increased; the breakdown voltage of the superjunction device is determined by a depletion region formed when both the top superjunction structure and the bottom superjunction structure are fully depleted.
The first voltage value is determined by the voltage endurance capacity of the top super-junction structure, the larger the voltage endurance capacity of the top super-junction structure is, the larger the first voltage value is, and the smaller the voltage endurance capacity of the top super-junction structure is, the smaller the first voltage value is. The smaller the thickness of the top super junction structure is, the smaller the first voltage value is, that is, the first voltage value can be adjusted by adjusting the thickness of the top super junction structure, so that the flexibility of design can be improved. The larger the thickness of the bottom super junction structure is, the larger the reverse recovery softness of the super junction device is.
In order to more clearly illustrate the first embodiment of the present invention, the superjunction device according to the first embodiment of the present invention is further illustrated by taking an N-type superjunction MOSFET device with a breakdown voltage of 600V as an example and combining specific parameters:
the semiconductor substrate 1 is a silicon substrate, the silicon substrate 1 is a high-concentration base plate, the resistivity is 0.001-0.003 ohm-cm, and the thickness T00 of the thinned silicon substrate 1 is 60-160 micronsAnd (4) rice. The resistivity of the N-type epitaxial layer is 1 ohm cm to 2 ohm cm, preferably, the resistivity of the N-type epitaxial layer is 1.5 ohm cm, and the concentration of N-type impurities corresponding to the resistivity of 1.5 ohm cm is 3.13e15cm-3The thickness of the whole N-type epitaxial layer, i.e., the whole N-type epitaxial layer including the super junction structure and the N-type buffer layer 30, is 50 micrometers; the N-type buffer layer 30 and the N-type column 3 are both directly composed of N-type epitaxial layers, so that the resistivities of the N-type buffer layer 30 and the N-type column 3 are the same as those of the N-type epitaxial layers, and the thickness T30 of the N-type buffer layer 30 is 5-20 micrometers; the width of the N-type column is 5.5 micrometers, and the width of the P-type column is 4.5 micrometers; the thickness of the first P-type column 41 is 30-40 micrometers; further, the thickness of the N-type electric field blocking layer 31 is 1 to 2 micrometers, which is required to ensure that N-type carriers in the region are not completely consumed at a lower voltage; further, the thickness of the second P-type column 42 is 2 to 5 micrometers.
The N-type super junction MOSFET device further comprises a primitive cell structure formed in each super junction unit, wherein the primitive cell structure comprises:
a P-type well 7 is formed at the top of the P-type column, a source region 8 consisting of an N + region and a P-well lead-out region 9 consisting of a P + region are formed in the P-type well 7, and a gate dielectric layer such as a gate oxide layer 5 and a polysilicon gate 6 is formed on the surface of the P-type well 7.
The interlayer film 10, the contact hole 11, the front metal layer 12 and the front metal layer 12 are patterned to respectively lead out a source electrode and a grid electrode. The drain region is formed by directly or further doping the thinned heavily doped semiconductor substrate 1, a back metal layer 13 is formed on the back of the semiconductor substrate 1, and the drain electrode is led out of the back metal layer 13.
The drift region of the device is composed of an N-type column 3 and an N-type buffer layer 30 between a P-type well 7 and a drain region 1, and a parasitic body diode is formed between the P-type well 7 and the drift region.
Since the breakdown voltage of the superjunction device in the first embodiment of the present invention is determined by the depletion region formed when both the top superjunction structure and the bottom superjunction structure are completely depleted, compared with the prior art, the BVds of the device is slightly affected by increasing the N-type electric field blocking layer 31 in the first embodiment of the present invention, and is not changed basically, so that the first embodiment of the present invention can well realize the breakdown voltage of 600V. For a super junction device with BVds of 600V, the operating voltage is generally less than 500V or less than 0.8 × BVds, that is, Vds of the device is less than 500V or 0.8 × BVds when the device is in an operating state, then only the top super junction structure is depleted and the N-type electric field blocking layer 31 is partially depleted, which is a key parameter affecting Cgd, and the thickness of the depletion layer is reduced, so that Cgd of the device is increased relative to the prior art, which is described below with reference to fig. 4E: as shown in fig. 4E, a curve 102 is a gate-drain capacitance curve of the superjunction device according to the first embodiment of the present invention, and a curve 101 is a gate-drain capacitance curve of the superjunction device shown in fig. 1 as a comparison, it can be seen that, under the condition that the source-drain voltage Vds is lower than the first voltage value, Cgd corresponding to the curve 102 is greater than Cgd of the curve 101, the minimum value of Cgd in the curve 102 is Cgd2, and the minimum value of Cgd in the curve 101 is Cgd1, it is known that Cgd2 is greater than Cgd1, so that the superjunction device according to the first embodiment of the present invention can only be depleted in the top superjunction structure during operation, thereby increasing the gate-drain capacitance, and thus also increasing the minimum value of the gate-drain capacitance, thereby effectively reducing the electromagnetic interference performance of the device in the application circuit, and effectively reducing the overshoot of current and voltage brought by the device in the application circuit. The curves 101 and 102 are only consistent when the source-drain voltage continues to increase such that depletion of both the first P-type pillar 41 and the second P-type pillar 42 occurs.
In addition, when Vds of the super-junction device of the first super-junction device of the embodiment of the invention is less than 500V, only the top super-junction structure is depleted and part of the N-type electric field blocking layer 31 is depleted, so that in the reverse recovery process of the parasitic body diode, the working power supply Vdd in the circuit is usually less than 480V, and when Vds of the device reaches Vdd, the bottom super-junction structure in the device is not depleted yet, so that holes and electrons which are not depleted are mostly reserved in the device, compared with the prior art, the softness of reverse recovery of the device is increased, and the reverse recovery characteristic of the device is improved.
Second super junction device of the embodiment of the invention:
the second superjunction device according to the second embodiment of the present invention is different from the first superjunction device according to the first embodiment of the present invention in that charge balance is performed between the second P-type column 42 and the adjacent N-type column 3 in the second superjunction device according to the second embodiment of the present invention, that is, the total amount of impurities in the second P-type column 42 and the adjacent N-type column 3 is equal. Therefore, the electric field intensity distribution of the drift region of the second super junction device in the embodiment of the invention when the source-drain voltage is greater than the first voltage value is different from that in the first embodiment of the invention, as shown in fig. 4C, the electric field intensity distribution of the drift region of the second super junction device in the embodiment of the invention when the source-drain voltage is greater than the first voltage value is a schematic diagram; the electric field intensity is reduced in the N-type electric field blocking layer 31, and the electric field intensity is kept basically constant between the interface E1E2 and the interface A1A2 after passing through the N-type electric field blocking layer 31, namely between the bottom super junction structure areas, so that the maximum electric field intensity of the section area is lower than that of the top super junction structure, and therefore avalanche breakdown occurs in the top super junction structure, and the EAS capability and the consistency of the device are not affected; the electric field strength finally drops to 0 in the N-type buffer layer 30.
The embodiment of the invention provides a triple super junction device:
the third super junction device according to the embodiment of the present invention is different from the first super junction device according to the embodiment of the present invention in that the total amount of impurities of the second P-type column 42 in the third super junction device according to the embodiment of the present invention is smaller than the total amount of impurities adjacent to the N-type column 3. Therefore, the electric field intensity distribution of the drift region of the triple-junction device in the embodiment of the invention when the source-drain voltage is greater than the first voltage value is different from that in the first embodiment of the invention, as shown in fig. 4D, the electric field intensity distribution of the drift region of the triple-junction device in the embodiment of the invention when the source-drain voltage is greater than the first voltage value is a schematic diagram; the electric field intensity is reduced in the N-type electric field blocking layer 31, and after the electric field intensity passes through the N-type electric field blocking layer 31, the electric field intensity is gradually reduced between an interface E1E2 and an interface A1A2, namely between bottom super junction structure areas, so that the maximum electric field intensity of the section area is lower than that of the top super junction structure, and avalanche breakdown occurs in the top super junction structure, and the EAS capacity and consistency of the device are not affected; the electric field strength finally drops to 0 in the N-type buffer layer 30.
The four super junction devices of the embodiment of the invention:
as shown in fig. 5, is a schematic diagram of a four superjunction device of an embodiment of the present invention; the four super junction device of the embodiment of the invention is different from the one super junction device of the embodiment of the invention in that the four super junction device of the embodiment of the invention has the following characteristics: the second P-type column 42 is formed by multiple times of epitaxy plus ion implantation, which can increase the thickness of the second P-type column 42. Compared with the first superjunction device of the embodiment of the present invention, if the thickness of the first P-type column 41 is smaller and the thickness of the second P-type column 42 is larger in the fourth superjunction device of the embodiment of the present invention under the condition that the total thickness of the superjunction structure is kept constant, the N-type electric field blocking layer 31 can generate an electric field blocking effect at a lower Vds, that is, the first voltage value is smaller, the reverse recovery characteristic of the device is further improved, and the flexibility of the device design is increased.
The five super junction devices of the embodiment of the invention:
as shown in fig. 6, is a schematic diagram of a five superjunction device of an embodiment of the present invention; the five super junction device in the embodiment of the present invention is different from the one super junction device in the embodiment of the present invention in that the five super junction device in the embodiment of the present invention has the following characteristics: the second P-type column 43 is formed by trench-filling P-type silicon, here the trench-filled second P-type column is designated by reference numeral 43 alone. In the fifth embodiment of the present invention, the thickness of the second P-type column 43 can be adjusted, so that the flexibility of device design can be increased.
The six super junction devices of the embodiment of the invention:
fig. 7 is a schematic diagram of a six superjunction device according to an embodiment of the present invention; the six super junction device of the embodiment of the invention is different from the five super junction device of the embodiment of the invention in that the six super junction device of the embodiment of the invention has the following characteristics: the N-type electric field blocking layers 31 of the respective super junction units each having the N-type electric field blocking layer 31 are integrally connected. If all the super cells of the entire charge flow region have the N-type electric field blocking layer 31, the N-type electric field blocking layer 31 may extend throughout the entire charge flow region. The size of the N-type electric field blocking layer 31 is enlarged to further increase the electric field blocking effect and improve the reverse recovery characteristic of the device, thereby further enlarging the flexibility of the device design.
The embodiment of the invention discloses a method for manufacturing a super junction device, which comprises the following steps:
the method for manufacturing the super junction device is used for manufacturing the super junction device shown in fig. 3, wherein a charge flowing area of the super junction device comprises a super junction structure consisting of a plurality of alternately arranged N-type columns 3 and P-type columns; each N-type column 3 and the adjacent P-type columns form a super junction unit; the P-type column of at least one super junction unit is provided with an N-type electric field blocking layer 31, and the super junction unit provided with the N-type electric field blocking layer 31 is formed by the steps of:
step one, an N-type epitaxial layer is provided, and the N-type epitaxial layer is formed on a semiconductor substrate 1. And forming a groove in the N-type epitaxial layer by adopting a photoetching process, wherein the depth of the groove is the same as that of the first P-type column 41.
Step two, carrying out first P-type ion implantation to form a second P-type column 42 at the bottom of the groove; and performing a second N-type ion implantation to form an N-type electric field blocking layer 31 at the bottom of the trench, wherein the N-type electric field blocking layer 31 is located at the top of the second P-type column 42.
Preferably, after the two ion implantations are completed, a trench cleaning process may be performed to form a sacrificial oxide layer and remove the sacrificial oxide layer.
Step three, filling P-type silicon in the groove to form a first P-type column 41; the first P-type column 41 and the second P-type column 42 are longitudinally superposed to form the P-type columns divided by the N-type electric field blocking layer 31; the N-type columns 3 are composed of the N-type epitaxial layer between the P-type columns.
The first P-type columns 41 and the adjacent N-type columns 3 are alternately arranged to form a top super junction structure; the second P-type columns 42 and the adjacent N-type columns 3 are alternately arranged to form a bottom super junction structure; the N-type electric field blocking layer 31 is used for realizing segmented depletion of the top super junction structure and the bottom super junction structure.
When the source-drain voltage of the super junction device is less than or equal to a first voltage value, only the top super junction structure is depleted, the electric field is terminated in the N-type electric field blocking layer 31, and the bottom super junction structure is not depleted.
When the source-drain voltage of the super junction device is greater than the first voltage value, the top super junction structure is completely depleted, and the electric field continues to deplete the bottom super junction structure after passing through the N-type electric field blocking layer 31.
The first voltage value is required to be more than or equal to the working voltage of the super junction device and less than the breakdown voltage of the super junction device, so that the super junction device is only depleted in the top super junction structure during working, the gate leakage capacitance is improved, and meanwhile, carriers can be provided during reverse recovery of the device by utilizing the characteristic that the bottom super junction structure is not depleted, and the reverse recovery softness factor of the device is increased; the breakdown voltage of the superjunction device is determined by a depletion region formed when both the top superjunction structure and the bottom superjunction structure are fully depleted.
Taking the super junction device as an N-type super junction MOSFET device as an example, the method further comprises the following steps:
and step four, forming a P-type back gate, namely a P-type well 7 on the super junction structure by photoetching, ion implantation and annealing process, wherein the P-type well 7 is positioned at the top of the P-type column and extends to the top of the N-type column 3.
Then, a source region 8 composed of an N + region is formed in the P-type well 7; a gate dielectric layer such as a gate oxide layer 5 and a polysilicon gate 6 is formed on the surface of the P-type well 7; forming an interlayer film 10, a contact hole 11, a P well lead-out region 9 which is positioned in a P well 7 at the bottom of the contact hole 11 and consists of a P + region, and a front metal layer 12, and respectively leading out a source electrode and a grid electrode after patterning the front metal layer 12; thinning the semiconductor substrate 1 to form a drain region or thinning the semiconductor substrate 1 and then performing N + ion implantation to form the drain region to form a back metal layer 13, and leading out the drain from the back metal layer 13.
In order to more clearly illustrate the method of the embodiment of the present invention, the steps of the method of the embodiment of the present invention are further illustrated below by taking the formation of an N-type super junction MOSFET device with a breakdown voltage of 600V as an example and combining specific parameters:
in the first step, the thickness of the N-type epitaxial layer is 50 microns, and the depth of the groove is 30-40 microns.
In the second step, the parameters of the first P-type ion implantation process are as follows: the implantation impurity is boron, the implantation energy is 1 Mev-4 Mev, and the implantation dosage is 1E12cm-2～3E12cm-2(ii) a The technological parameters of the second N-type ion implantation are as follows: the implantation impurity is phosphorus, the implantation energy is 50Kev, and the implantation dosage is 2E12cm-2～3E12cm-2。
In step three, if the width of the top of the trench is 4.5 microns and the width of the top of the N-type epitaxy between the trenches is 5.5 microns, then the concentration of the P-type epitaxy, i.e. the first P-type silicon 41, is set according to the tilt angle of the trenches, typically at 4E15cm-3～6E15cm-3The goal is to allow a better balance of P-N impurity levels in the first P-N column, i.e., the top superjunction structure, or to ensure that the difference between the two is less than 10% of either impurity level.
The annealing process to form the P-well 7 in step four is a longer thermal process at higher temperatures, for example, temperatures in excess of 1100 c for 60 minutes. The further improvement of the process is that high-temperature annealing is formed after two times of ion implantation is completed in the second step, so that the implanted boron and phosphorus can be fully diffused, the thickness of the N-type electric field blocking layer 31 can reach 1-2 microns, and the thickness of the second P-type column 42 can reach 3-5 microns.
The second super junction device manufacturing method of the embodiment of the invention comprises the following steps:
the manufacturing method of the superjunction device according to the second embodiment of the present invention is used for manufacturing the four superjunction device according to the second embodiment of the present invention as shown in fig. 5, in the manufacturing method of the superjunction device according to the second embodiment of the present invention, a charge flowing region of the superjunction device includes a superjunction structure composed of a plurality of N-type columns 3 and P-type columns which are alternately arranged; each N-type column 3 and the adjacent P-type columns form a super junction unit; the P-type column of at least one super junction unit is provided with an N-type electric field blocking layer 31, and the super junction unit provided with the N-type electric field blocking layer 31 is formed by the steps of:
step one, providing a first N-type epitaxial layer, carrying out photoetching and P-type ion implantation on a first layer of P-type area on the first N-type epitaxial layer, and forming a first layer of N-type area by the first N-type epitaxial layer between the first layer of P-type area.
Step two, forming a second intrinsic epitaxial layer on the first N-type epitaxial layer; photoetching and P-type ion implantation are carried out on a second P-type region on the second intrinsic epitaxial layer, and photoetching and N-type ion implantation are carried out on a second N-type region on the second intrinsic epitaxial layer; the second layer of P-type region is superposed on the first P-type region, and the second N-type region is superposed on the first N-type region.
Step three, repeating the step two to form more layers of P-type regions and N-type regions, wherein the P-type regions of all the layers are overlapped to form a second P-type column 42, and the N-type regions of all the layers are also overlapped together; repeating the second step for 0 times or more than 1 time until the thickness of the second P-type column 42 meets the requirement. In the second method of the present invention, as shown in fig. 5, the thickness from the interface B1B2 to the interface D1D2 is finally 20 μm.
And fourthly, forming the N-type electric field blocking layer 31 on the top of the second P-type column 42 by adopting photoetching and N-type ion implantation.
And step five, growing the epitaxial layer to form a third N-type epitaxial layer. Preferably, in the second method of the present invention, the thickness of the third N-type epitaxial layer is 30 μm.
Forming a groove in the third N-type epitaxial layer by adopting a photoetching process, wherein the N-type electric field blocking layer 31 is exposed from the bottom of the groove; filling P-type silicon in the trench to form a first P-type column 41; the first P-type column 41 and the second P-type column 42 are longitudinally superposed to form the P-type columns divided by the N-type electric field blocking layer 31; the N-type columns 3 are formed by overlapping N-type regions among the P-type columns and the third N-type epitaxial layer.
The first P-type columns 41 and the adjacent N-type columns 3 are alternately arranged to form a top super junction structure; the second P-type columns 42 and the adjacent N-type columns 3 are alternately arranged to form a bottom super junction structure; the N-type electric field blocking layer 31 is used for realizing segmented depletion of the top super junction structure and the bottom super junction structure.
Preferably, in step five, if the width of the top of the trench is 4.5 microns and the width of the top of the N-type epitaxy between the trenches is 5.5 microns, then the P-type epitaxy is the firstThe concentration of P-type silicon 41 is set according to the tilt angle of the trench, and is generally 4E15cm-3～6E15cm-3,The aim is to make the P-N impurity amount in the first P-N column, i.e. the top super junction structure, well balanced, or to ensure that the difference between the two is less than 10% of the impurity amount of either one.
When the source-drain voltage of the super junction device is less than or equal to a first voltage value, only the top super junction structure is depleted, the electric field is terminated in the N-type electric field blocking layer 31, and the bottom super junction structure is not depleted.
When the source-drain voltage of the super junction device is greater than the first voltage value, the top super junction structure is completely depleted, and the electric field continues to deplete the bottom super junction structure after passing through the N-type electric field blocking layer 31.
The first voltage value is required to be more than or equal to the working voltage of the super junction device and less than the breakdown voltage of the super junction device, so that the super junction device is only depleted in the top super junction structure during working, the gate leakage capacitance is improved, and meanwhile, carriers can be provided during reverse recovery of the device by utilizing the characteristic that the bottom super junction structure is not depleted, and the reverse recovery softness factor of the device is increased; the breakdown voltage of the superjunction device is determined by a depletion region formed when both the top superjunction structure and the bottom superjunction structure are fully depleted.
Taking the super junction device as an N-type super junction MOSFET device as an example, the method further comprises the following steps:
and step six, forming a P-type back gate, namely a P-type well 7 on the super junction structure by photoetching, ion implantation and annealing process, wherein the P-type well 7 is positioned at the top of the P-type column and extends to the top of the N-type column 3.
Then, a source region 8 composed of an N + region is formed in the P-type well 7; a gate dielectric layer such as a gate oxide layer 5 and a polysilicon gate 6 is formed on the surface of the P-type well 7; forming an interlayer film 10, a contact hole 11, a P well lead-out region 9 which is positioned in a P well 7 at the bottom of the contact hole 11 and consists of a P + region, and a front metal layer 12, and respectively leading out a source electrode and a grid electrode after patterning the front metal layer 12; thinning the semiconductor substrate 1 to form a drain region or thinning the semiconductor substrate 1 and then performing N + ion implantation to form the drain region to form a back metal layer 13, and leading out the drain from the back metal layer 13.
The thermal process of the annealing drive well for forming the P well 7 in the sixth step is longer, the temperature is higher, for example, the temperature exceeds 1100 ℃, and the time is 60 minutes; this enables the P-type regions of the second P-type pillar 42 to be well connected together, and also enables the N-type regions of the N-type pillar adjacent to the second P-type pillar 42 to be well connected together, thus ensuring the normal characteristics of the device, such as on-resistance, breakdown voltage, etc.
The manufacturing method of the triple super junction device comprises the following steps:
the manufacturing method of the third super-junction device in the embodiment of the invention is different from the manufacturing method of the second super-junction device in the embodiment of the invention in that, in the third super-junction device in the embodiment of the invention, the N-type electric field blocking layer 31 does not need to be formed by adopting the separate step four, but the ion implantation step for forming the N-type electric field blocking layer 31 is arranged after the groove is formed in the step five and before the P-type silicon is filled, so that the N-type electric field blocking layer 31 is directly defined by using the mask for forming the groove, and the definition by adopting a single photolithography process is not needed.
The manufacturing method of the four super junction device comprises the following steps:
the manufacturing method of the four-super-junction device of the embodiment of the invention is used for manufacturing the five-super-junction device of the embodiment of the invention as shown in fig. 6, in the manufacturing method of the four-super-junction device of the embodiment of the invention, a charge flowing area of the super-junction device comprises a super-junction structure consisting of a plurality of N-type columns 3 and P-type columns which are alternately arranged; each N-type column 3 and the adjacent P-type columns form a super junction unit; the P-type column of at least one super junction unit is provided with an N-type electric field blocking layer 31, and the super junction unit provided with the N-type electric field blocking layer 31 is formed by the steps of:
step one, providing a first N-type epitaxial layer; forming a first groove in the first N-type epitaxial layer by adopting a photoetching process; and filling P-type silicon in the first groove to form a second P-type column 42. The first N-type epitaxial layer corresponds to the N-type epitaxial layer between the interface B1B2 and the interface D1D2 in fig. 6, and preferably has a thickness of 15 to 20 μm. Filling P-type silicon requires Chemical Mechanical Polishing (CMP) to achieve planarization.
Growing an epitaxial layer to form a second N-type epitaxial layer; and forming a second groove in the second N-type epitaxial layer by adopting a photoetching process, wherein the second groove is aligned to the second P-type column 42 at the bottom and exposes the surface of the second P-type column 42. Preferably, the thickness of the second N-type epitaxial layer is 30 μm.
Performing N-type ion implantation to form an N-type electric field blocking layer 31 at the bottom of the second trench, wherein the N-type electric field blocking layer 31 is located at the top of the second P-type column 42;
step three, filling P-type silicon in the second trench to form a first P-type column 41; filling P-type silicon requires chemical mechanical polishing to achieve planarization. The first P-type column 41 and the second P-type column 42 are longitudinally superposed to form the P-type columns divided by the N-type electric field blocking layer 31; the N-type columns 3 are formed by overlapping the first N-type epitaxial layer and the second N-type epitaxial layer between the P-type columns.
The first P-type columns 41 and the adjacent N-type columns 3 are alternately arranged to form a top super junction structure; the second P-type columns 42 and the adjacent N-type columns 3 are alternately arranged to form a bottom super junction structure; the N-type electric field blocking layer 31 is used for realizing segmented depletion of the top super junction structure and the bottom super junction structure;
when the source-drain voltage of the super junction device is less than or equal to a first voltage value, only the top super junction structure is depleted, the electric field is terminated in the N-type electric field blocking layer 31, and the bottom super junction structure is not depleted;
when the source-drain voltage of the super junction device is greater than the first voltage value, the top super junction structure is completely depleted, and an electric field continues to deplete the bottom super junction structure after passing through the N-type electric field blocking layer 31;
the first voltage value is required to be more than or equal to the working voltage of the super junction device and less than the breakdown voltage of the super junction device, so that the super junction device is only depleted in the top super junction structure during working, the gate leakage capacitance is improved, and meanwhile, carriers can be provided during reverse recovery of the device by utilizing the characteristic that the bottom super junction structure is not depleted, and the reverse recovery softness factor of the device is increased; the breakdown voltage of the superjunction device is determined by a depletion region formed when both the top superjunction structure and the bottom superjunction structure are fully depleted.
Taking the super junction device as an N-type super junction MOSFET device as an example, the method further comprises the following steps:
and step four, forming a P-type back gate, namely a P-type well 7 on the super junction structure by photoetching, ion implantation and annealing process, wherein the P-type well 7 is positioned at the top of the P-type column and extends to the top of the N-type column 3.
Then, a source region 8 composed of an N + region is formed in the P-type well 7; a gate dielectric layer such as a gate oxide layer 5 and a polysilicon gate 6 is formed on the surface of the P-type well 7; forming an interlayer film 10, a contact hole 11, a P well lead-out region 9 which is positioned in a P well 7 at the bottom of the contact hole 11 and consists of a P + region, and a front metal layer 12, and respectively leading out a source electrode and a grid electrode after patterning the front metal layer 12; thinning the semiconductor substrate 1 to form a drain region or thinning the semiconductor substrate 1 and then performing N + ion implantation to form the drain region to form a back metal layer 13, and leading out the drain from the back metal layer 13.
The manufacturing method of the five super junction device comprises the following steps:
the manufacturing method of the five-super-junction device in the embodiment of the invention is used for manufacturing the six-super-junction device in the embodiment of the invention as shown in fig. 7, in the manufacturing method of the five-super-junction device in the embodiment of the invention, a charge flowing area of the super-junction device comprises a super-junction structure consisting of a plurality of alternately arranged N-type columns 3 and P-type columns; each N-type column 3 and the adjacent P-type columns form a super junction unit; the P-type column of at least one super junction unit is provided with an N-type electric field blocking layer 31, and the super junction unit provided with the N-type electric field blocking layer 31 is formed by the steps of:
step one, providing a first N-type epitaxial layer; forming a first groove in the first N-type epitaxial layer by adopting a photoetching process; filling P-type silicon in the first trench to form a second P-type column 42; n-type ion implantation is performed to form an N-type electric field blocking layer 31 on top of the second P-type columns 42.
The first N-type epitaxial layer corresponds to the N-type epitaxial layer between the interface B1B2 and the interface D1D2 in fig. 6, and preferably has a thickness of 15 to 20 μm. Filling P-type silicon requires Chemical Mechanical Polishing (CMP) to achieve planarization.
Growing an epitaxial layer to form a second N-type epitaxial layer; and forming a second groove in the second N-type epitaxial layer by adopting a photoetching process, wherein the second groove is aligned to the second P-type column 42 at the bottom and exposes the N-type electric field blocking layer 31. Preferably, the thickness of the second N-type epitaxial layer is 30 μm.
Step three, filling P-type silicon in the second trench to form a first P-type column 41; filling P-type silicon requires chemical mechanical polishing to achieve planarization. The first P-type column 41 and the second P-type column 42 are longitudinally superposed to form the P-type columns divided by the N-type electric field blocking layer 31; the N-type columns 3 are formed by overlapping the first N-type epitaxial layer and the second N-type epitaxial layer between the P-type columns.
The first P-type columns 41 and the adjacent N-type columns 3 are alternately arranged to form a top super junction structure; the second P-type columns 42 and the adjacent N-type columns 3 are alternately arranged to form a bottom super junction structure; the N-type electric field blocking layer 31 is used for realizing segmented depletion of the top super junction structure and the bottom super junction structure.
When the source-drain voltage of the super junction device is less than or equal to a first voltage value, only the top super junction structure is depleted, the electric field is terminated in the N-type electric field blocking layer 31, and the bottom super junction structure is not depleted.
When the source-drain voltage of the super junction device is greater than the first voltage value, the top super junction structure is completely depleted, and the electric field continues to deplete the bottom super junction structure after passing through the N-type electric field blocking layer 31.
The first voltage value is required to be more than or equal to the working voltage of the super junction device and less than the breakdown voltage of the super junction device, so that the super junction device is only depleted in the top super junction structure during working, the gate leakage capacitance is improved, and meanwhile, carriers can be provided during reverse recovery of the device by utilizing the characteristic that the bottom super junction structure is not depleted, and the reverse recovery softness factor of the device is increased; the breakdown voltage of the superjunction device is determined by a depletion region formed when both the top superjunction structure and the bottom superjunction structure are fully depleted.
Taking the super junction device as an N-type super junction MOSFET device as an example, the method further comprises the following steps:
and step four, forming a P-type back gate, namely a P-type well 7 on the super junction structure by photoetching, ion implantation and annealing process, wherein the P-type well 7 is positioned at the top of the P-type column and extends to the top of the N-type column 3.
Then, a source region 8 composed of an N + region is formed in the P-type well 7; a gate dielectric layer such as a gate oxide layer 5 and a polysilicon gate 6 is formed on the surface of the P-type well 7; forming an interlayer film 10, a contact hole 11, a P well lead-out region 9 which is positioned in a P well 7 at the bottom of the contact hole 11 and consists of a P + region, and a front metal layer 12, and respectively leading out a source electrode and a grid electrode after patterning the front metal layer 12; thinning the semiconductor substrate 1 to form a drain region or thinning the semiconductor substrate 1 and then performing N + ion implantation to form the drain region to form a back metal layer 13, and leading out the drain from the back metal layer 13.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. A super junction device, characterized in that:
the charge flowing region comprises a super junction structure consisting of a plurality of alternately arranged N-type columns and P-type columns; each N-type column and the adjacent P-type column form a super junction unit;
an N-type electric field blocking layer is arranged in the P-type column of at least one super junction unit, and the P-type column is divided into a first P-type column located at the top of the N-type electric field blocking layer and a second P-type column located at the bottom of the N-type electric field blocking layer by the N-type electric field blocking layer in the longitudinal direction;
the first P-type columns and the adjacent N-type columns are alternately arranged to form a top super junction structure; the second P-type columns and the adjacent N-type columns are alternately arranged to form a bottom super junction structure; the N-type electric field blocking layer is used for realizing segmented depletion of the top super junction structure and the bottom super junction structure;
when the source-drain voltage of the super junction device is less than or equal to a first voltage value, only the top super junction structure is depleted, the electric field is terminated in the N-type electric field blocking layer, and the bottom super junction structure is not depleted;
when the source-drain voltage of the super junction device is larger than the first voltage value, the top super junction structure is completely depleted, and an electric field continues to deplete the bottom super junction structure after passing through the N-type electric field blocking layer;
the first voltage value is required to be more than or equal to the working voltage of the super junction device and less than the breakdown voltage of the super junction device, so that the super junction device is only depleted in the top super junction structure during working, the gate leakage capacitance is improved, and meanwhile, carriers can be provided during reverse recovery of the device by utilizing the characteristic that the bottom super junction structure is not depleted, and the reverse recovery softness factor of the device is increased; the breakdown voltage of the superjunction device is determined by a depletion region formed when both the top superjunction structure and the bottom superjunction structure are fully depleted.
2. The superjunction device of claim 1, wherein: the first voltage value is determined by the voltage endurance capacity of the top super-junction structure, the larger the voltage endurance capacity of the top super-junction structure is, the larger the first voltage value is, and the smaller the voltage endurance capacity of the top super-junction structure is, the smaller the first voltage value is.
3. The superjunction device of claim 2, wherein: the smaller the thickness of the top superjunction structure, the smaller the first voltage value.
4. The superjunction device of claim 1, wherein: the larger the thickness of the bottom super junction structure is, the larger the reverse recovery softness of the super junction device is.
5. The superjunction device of claim 1, wherein: charge balance between the first P-type pillar and the adjacent N-type pillar;
charge balance between the second P-type pillar and the adjacent N-type pillar; or the total impurity amount of the second P-type column is larger than that of the adjacent N-type column; or the total impurity amount of the second P-type column is less than that of the adjacent N-type column.
6. The superjunction device of claim 1, wherein: the doping concentration of the N-type electric field blocking layer is 2-10 times of the maximum doping concentration of the first P-type column and the second P-type column.
7. The superjunction device of claim 1, wherein: the thickness of the N-type electric field blocking layer is 1-5 microns.
8. The superjunction device of claim 1, wherein: the two sides of the N-type electric field blocking layer corresponding to each P-type column are in contact with the N-type columns, and the width of each N-type electric field blocking layer is larger than or equal to the width of the corresponding first P-type column and the second P-type column; or the N-type electric field blocking layers of the super junction units with the N-type electric field blocking layers are connected into a whole.
9. The superjunction device of claim 1, wherein: the thickness of the first P-type column is larger than that of the second P-type column.
10. The superjunction device of claim 1, 4 or 9, wherein: the thickness of the second P-type column is 2-20 micrometers; the second P-type column is formed by ion implantation or diffusion, or the second P-type column is formed by trench filling.
11. The superjunction device of claim 1, wherein: the super-junction structure is formed on the N-type epitaxial layer, an N-type buffer layer composed of the N-type epitaxial layer is formed at the bottom of the super-junction structure, and a heavily doped N-type semiconductor substrate is arranged at the bottom of the N-type buffer layer.
12. A manufacturing method of a super junction device is characterized in that a charge flowing area of the super junction device comprises a super junction structure composed of a plurality of alternately arranged N-type columns and P-type columns; each N-type column and the adjacent P-type column form a super junction unit; the P-type column of at least one super junction unit is provided with an N-type electric field blocking layer, and the super junction unit with the N-type electric field blocking layer is formed by the following steps:
providing an N-type epitaxial layer, and forming a groove in the N-type epitaxial layer by adopting a photoetching process, wherein the depth of the groove is the same as that of the first P-type column;
step two, carrying out first P-type ion implantation to form a second P-type column at the bottom of the groove; performing second N-type ion implantation to form an N-type electric field blocking layer at the bottom of the trench, wherein the N-type electric field blocking layer is positioned at the top of the second P-type column;
filling P-type silicon in the groove to form a first P-type column; the first P-type column and the second P-type column are longitudinally superposed to form the P-type column divided by the N-type electric field blocking layer; the N-type columns are composed of the N-type epitaxial layer among the P-type columns;
the first P-type columns and the adjacent N-type columns are alternately arranged to form a top super junction structure; the second P-type columns and the adjacent N-type columns are alternately arranged to form a bottom super junction structure; the N-type electric field blocking layer is used for realizing segmented depletion of the top super junction structure and the bottom super junction structure;
when the source-drain voltage of the super junction device is less than or equal to a first voltage value, only the top super junction structure is depleted, the electric field is terminated in the N-type electric field blocking layer, and the bottom super junction structure is not depleted;
when the source-drain voltage of the super junction device is larger than the first voltage value, the top super junction structure is completely depleted, and an electric field continues to deplete the bottom super junction structure after passing through the N-type electric field blocking layer;
the first voltage value is required to be more than or equal to the working voltage of the super junction device and less than the breakdown voltage of the super junction device, so that the super junction device is only depleted in the top super junction structure during working, the gate leakage capacitance is improved, and meanwhile, carriers can be provided during reverse recovery of the device by utilizing the characteristic that the bottom super junction structure is not depleted, and the reverse recovery softness factor of the device is increased; the breakdown voltage of the superjunction device is determined by a depletion region formed when both the top superjunction structure and the bottom superjunction structure are fully depleted.
13. A manufacturing method of a super junction device is characterized in that a charge flowing area of the super junction device comprises a super junction structure composed of a plurality of alternately arranged N-type columns and P-type columns; each N-type column and the adjacent P-type column form a super junction unit; the P-type column of at least one super junction unit is provided with an N-type electric field blocking layer, and the super junction unit with the N-type electric field blocking layer is formed by the following steps:
providing a first N-type epitaxial layer, carrying out photoetching and P-type ion implantation to form a first layer of P-type region on the first N-type epitaxial layer, and forming a first layer of N-type region by the first N-type epitaxial layer between the first layer of P-type region;
step two, forming a second intrinsic epitaxial layer on the first N-type epitaxial layer; photoetching and P-type ion implantation are carried out on a second P-type region on the second intrinsic epitaxial layer, and photoetching and N-type ion implantation are carried out on a second N-type region on the second intrinsic epitaxial layer; the second layer of P-type area is superposed on the first layer of P-type area, and the second layer of N-type area is superposed on the first layer of N-type area;
step three, repeating the step two to form more layers of P-type regions and N-type regions, wherein the P-type regions of all the layers are overlapped to form a second P-type column, and the N-type regions of all the layers are also overlapped together; repeating the second step for 0 time or more than 1 time until the thickness of the second P-type column meets the requirement;
step four, forming an N-type electric field blocking layer on the top of the second P-type column by adopting photoetching and N-type ion implantation;
fifthly, growing an epitaxial layer to form a third N-type epitaxial layer; forming a groove in the third N-type epitaxial layer by adopting a photoetching process, wherein the N-type electric field blocking layer is exposed out of the bottom of the groove; filling P-type silicon in the groove to form a first P-type column; the first P-type column and the second P-type column are longitudinally superposed to form the P-type column divided by the N-type electric field blocking layer; the N-type columns are formed by overlapping N-type regions of all layers among the P-type columns and the third N-type epitaxial layer;
the first P-type columns and the adjacent N-type columns are alternately arranged to form a top super junction structure; the second P-type columns and the adjacent N-type columns are alternately arranged to form a bottom super junction structure; the N-type electric field blocking layer is used for realizing segmented depletion of the top super junction structure and the bottom super junction structure;
when the source-drain voltage of the super junction device is less than or equal to a first voltage value, only the top super junction structure is depleted, the electric field is terminated in the N-type electric field blocking layer, and the bottom super junction structure is not depleted;
when the source-drain voltage of the super junction device is larger than the first voltage value, the top super junction structure is completely depleted, and an electric field continues to deplete the bottom super junction structure after passing through the N-type electric field blocking layer;
the first voltage value is required to be more than or equal to the working voltage of the super junction device and less than the breakdown voltage of the super junction device, so that the super junction device is only depleted in the top super junction structure during working, the gate leakage capacitance is improved, and meanwhile, carriers can be provided during reverse recovery of the device by utilizing the characteristic that the bottom super junction structure is not depleted, and the reverse recovery softness factor of the device is increased; the breakdown voltage of the superjunction device is determined by a depletion region formed when both the top superjunction structure and the bottom superjunction structure are fully depleted.
14. A manufacturing method of a super junction device is characterized in that a charge flowing area of the super junction device comprises a super junction structure composed of a plurality of alternately arranged N-type columns and P-type columns; each N-type column and the adjacent P-type column form a super junction unit; the P-type column of at least one super junction unit is provided with an N-type electric field blocking layer, and the super junction unit with the N-type electric field blocking layer is formed by the following steps:
step one, providing a first N-type epitaxial layer; forming a first groove in the first N-type epitaxial layer by adopting a photoetching process; filling P-type silicon in the first groove to form a second P-type column;
growing an epitaxial layer to form a second N-type epitaxial layer; forming a second groove in the second N-type epitaxial layer by adopting a photoetching process, wherein the second groove is aligned to the second P-type column at the bottom and exposes the surface of the second P-type column;
performing N-type ion implantation to form an N-type electric field blocking layer at the bottom of the second trench, wherein the N-type electric field blocking layer is positioned at the top of the second P-type column;
filling P-type silicon in the second groove to form a first P-type column; the first P-type column and the second P-type column are longitudinally superposed to form the P-type column divided by the N-type electric field blocking layer; the N-type columns are formed by overlapping the first N-type epitaxial layer and the second N-type epitaxial layer between the P-type columns;
the first P-type columns and the adjacent N-type columns are alternately arranged to form a top super junction structure; the second P-type columns and the adjacent N-type columns are alternately arranged to form a bottom super junction structure; the N-type electric field blocking layer is used for realizing segmented depletion of the top super junction structure and the bottom super junction structure;
when the source-drain voltage of the super junction device is less than or equal to a first voltage value, only the top super junction structure is depleted, the electric field is terminated in the N-type electric field blocking layer, and the bottom super junction structure is not depleted;
when the source-drain voltage of the super junction device is larger than the first voltage value, the top super junction structure is completely depleted, and an electric field continues to deplete the bottom super junction structure after passing through the N-type electric field blocking layer;
the first voltage value is required to be more than or equal to the working voltage of the super junction device and less than the breakdown voltage of the super junction device, so that the super junction device is only depleted in the top super junction structure during working, the gate leakage capacitance is improved, and meanwhile, carriers can be provided during reverse recovery of the device by utilizing the characteristic that the bottom super junction structure is not depleted, and the reverse recovery softness factor of the device is increased; the breakdown voltage of the superjunction device is determined by a depletion region formed when both the top superjunction structure and the bottom superjunction structure are fully depleted.
15. A manufacturing method of a super junction device is characterized in that a charge flowing area of the super junction device comprises a super junction structure composed of a plurality of alternately arranged N-type columns and P-type columns; each N-type column and the adjacent P-type column form a super junction unit; the P-type column of at least one super junction unit is provided with an N-type electric field blocking layer, and the super junction unit with the N-type electric field blocking layer is formed by the following steps:
step one, providing a first N-type epitaxial layer; forming a first groove in the first N-type epitaxial layer by adopting a photoetching process; filling P-type silicon in the first groove to form a second P-type column; performing N-type ion implantation to form an N-type electric field blocking layer at the top of the second P-type column;
growing an epitaxial layer to form a second N-type epitaxial layer; forming a second groove in the second N-type epitaxial layer by adopting a photoetching process, wherein the second groove is aligned to the second P-type column at the bottom and exposes the N-type electric field blocking layer;
filling P-type silicon in the second groove to form a first P-type column; the first P-type column and the second P-type column are longitudinally superposed to form the P-type column divided by the N-type electric field blocking layer; the N-type columns are formed by overlapping the first N-type epitaxial layer and the second N-type epitaxial layer between the P-type columns;
the first P-type columns and the adjacent N-type columns are alternately arranged to form a top super junction structure; the second P-type columns and the adjacent N-type columns are alternately arranged to form a bottom super junction structure; the N-type electric field blocking layer is used for realizing segmented depletion of the top super junction structure and the bottom super junction structure;
when the source-drain voltage of the super junction device is less than or equal to a first voltage value, only the top super junction structure is depleted, the electric field is terminated in the N-type electric field blocking layer, and the bottom super junction structure is not depleted;
when the source-drain voltage of the super junction device is larger than the first voltage value, the top super junction structure is completely depleted, and an electric field continues to deplete the bottom super junction structure after passing through the N-type electric field blocking layer;
the first voltage value is required to be more than or equal to the working voltage of the super junction device and less than the breakdown voltage of the super junction device, so that the super junction device is only depleted in the top super junction structure during working, the gate leakage capacitance is improved, and meanwhile, carriers can be provided during reverse recovery of the device by utilizing the characteristic that the bottom super junction structure is not depleted, and the reverse recovery softness factor of the device is increased; the breakdown voltage of the superjunction device is determined by a depletion region formed when both the top superjunction structure and the bottom superjunction structure are fully depleted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610671434.3A CN107768443B (en) | 2016-08-15 | 2016-08-15 | Super junction device and manufacturing method thereof |
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| CN111883422A (en) * | 2020-07-16 | 2020-11-03 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of super junction device |
| CN114464672B (en) * | 2022-04-11 | 2022-07-08 | 江苏长晶科技股份有限公司 | Super junction device for improving body diode characteristics |
| CN116053300B (en) * | 2023-02-09 | 2024-01-05 | 上海功成半导体科技有限公司 | Super junction device, manufacturing method thereof and electronic device |
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| CN101246904A (en) * | 2007-02-15 | 2008-08-20 | 恩益禧电子股份有限公司 | Semiconductor device and method for manufacturing same |
| CN102420251A (en) * | 2011-12-05 | 2012-04-18 | 电子科技大学 | VDMOS (Vertical Double-Diffusion Metal-Oxide-Semiconductor) device with non-uniform floating island structure |
| CN105489500A (en) * | 2015-12-30 | 2016-04-13 | 西安龙腾新能源科技发展有限公司 | Preparation method for super-junction VDMOS and super-junction VDMOS device |
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| CN101246904A (en) * | 2007-02-15 | 2008-08-20 | 恩益禧电子股份有限公司 | Semiconductor device and method for manufacturing same |
| CN102420251A (en) * | 2011-12-05 | 2012-04-18 | 电子科技大学 | VDMOS (Vertical Double-Diffusion Metal-Oxide-Semiconductor) device with non-uniform floating island structure |
| CN105489500A (en) * | 2015-12-30 | 2016-04-13 | 西安龙腾新能源科技发展有限公司 | Preparation method for super-junction VDMOS and super-junction VDMOS device |
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