CN105489500A - Preparation method for super-junction VDMOS and super-junction VDMOS device - Google Patents
Preparation method for super-junction VDMOS and super-junction VDMOS device Download PDFInfo
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- CN105489500A CN105489500A CN201511030078.9A CN201511030078A CN105489500A CN 105489500 A CN105489500 A CN 105489500A CN 201511030078 A CN201511030078 A CN 201511030078A CN 105489500 A CN105489500 A CN 105489500A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 238000001259 photo etching Methods 0.000 claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052796 boron Inorganic materials 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 238000002347 injection Methods 0.000 claims abstract description 7
- 239000007924 injection Substances 0.000 claims abstract description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 5
- 238000004544 sputter deposition Methods 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000137 annealing Methods 0.000 claims abstract description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 abstract 5
- 238000000151 deposition Methods 0.000 abstract 2
- 230000008021 deposition Effects 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 239000011229 interlayer Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 9
- 230000005684 electric field Effects 0.000 description 7
- 238000000407 epitaxy Methods 0.000 description 5
- 238000004088 simulation Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a preparation method for a super-junction VDMOS. The preparation method comprises the steps of growing a first N-epitaxial layer on an N+ substrate; performing p type impurity boron injection through a photomask to form a p type region; continuing to perform epitaxial growth of a second N-epitaxial layer; injecting boron to the second N-epitaxial layer through a photomask to form a body co-pushing well; defining a trench region on the second N-epitaxial layer through photoetching and performing deep trench etching and back-filling of P-type monocrystalline silicon to form a P-pillar region of a super-junction VDMOS device; then performing thermal growth of gate oxide and deposition of N+ type polycrystalline silicon; after photoetching the polycrystalline silicon, defining an N+ injection region by a photoetching process and injecting N+ epitaxial layer impurity, and performing annealing to form an N+ source region; then performing inter-layer dielectric deposition, and etching an electrode contact; and sputtering metal Al, and after performing photoetching, obtaining a final device structure. The invention also discloses the super-junction VDMOS device. According to the preparation method for the super-junction VDMOS and the super-junction VDMOS device, breakdown voltage can be effectively improved and the reliability of the device can be enhanced under the condition of keeping the depth, width, and the depth-width ratio of the trenches.
Description
Technical field
The invention belongs to the preparing technical field of hyperconjugation VDMOS, be specifically related to a kind of preparation method and hyperconjugation VDMOS device thereof of hyperconjugation VDMOS.
Background technology
The high pressure superjunction preparation technology comparing main flow at present has two kinds, and a kind of is with the repeatedly injection of Infineon and ST position representative and epitaxy technology.Another kind is with the etching groove of Toshiba and Hua Hongwei representative and backfill technology.Two kinds of technology are compared, repeatedly inject and epitaxy technology comparative maturity but expensive, etching groove and backfill technology technics comparing simple, cost is relative also more cheap, concerning etching groove and backfill form the Technology Ways of superjunction, puncture voltage depends on the degree of depth of groove to a great extent, the degree of depth is larger, puncture voltage is higher, but, if the depth-to-width ratio of groove is too large, the monocrystalline silicon technique of backfill P type can be a challenge, and that is exactly the reliability easily forming cavity and affect device.
Summary of the invention
In view of this, main purpose of the present invention is the preparation method and the hyperconjugation VDMOS device thereof that provide a kind of hyperconjugation VDMOS.
For achieving the above object, technical scheme of the present invention is achieved in that
The embodiment of the present invention provides a kind of preparation method of hyperconjugation VDMOS, the method is: at N+ Grown the one N-epitaxial loayer, the boron first being carried out p-type impurity by reticle injects formation p-type area, continue epitaxial growth the 2nd N-epitaxial loayer, 2nd N-extension injects boron by reticle, forms body and push away trap; Then on described 2nd N-epitaxial loayer, define trench region by photoetching and carry out deep plough groove etched and backfill P-type monocrystalline silicon, forming the P-pillar district of hyperconjugation VDMOS device; Then the heat growth of grid oxygen and the deposit of N+ type polysilicon is carried out; After polysilicon photoetching, define N+ injection zone by photoetching process and inject N+ impurities, and annealing forms N+ source region; Then carry out the deposit of inter-level dielectric, and etch electrode contact; Splash-proofing sputtering metal Al, forms last device architecture after photoetching.
In such scheme, described in carry out deep plough groove etched formation deep trench and be positioned at a described N-epitaxial loayer p-type area aim at.
In such scheme, described is the N-epitaxial loayer of 10-20um at N+ Grown thickness.
In such scheme, described N+ impurities is As or P.
The embodiment of the present invention also provides a kind of hyperconjugation VDMOS device, this device comprises N+ substrate, a N-epitaxial loayer, the 2nd N-epitaxial loayer that superposition is arranged, p type island region is provided with in a described N-epitaxial loayer, being provided with P-pillar district in described 2nd N-epitaxial loayer, aligns with p type island region in described P-pillar district.
In such scheme, the distance between described P-pillar district and p type island region is 3um to 20um.
Compared with prior art, beneficial effect of the present invention:
The p-type area that the present invention is embedded by injection one and deep trench p-pillar district aims at and there is certain distance in p-type area and p-pillar district, when keeping the deeply wide and depth-to-width ratio of groove, effectively can improve puncture voltage, avoid because groove is too dark, p-type Si backfill causes possible cavity, thus improves the reliability of device.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of step one of the present invention;
Fig. 2 is the schematic diagram of step 2 of the present invention;
Fig. 3 is the schematic diagram that step 3 of the present invention forms body;
Fig. 4 is the schematic diagram that step 4 of the present invention forms p-pillar;
Fig. 5 is the schematic diagram of step 5 of the present invention;
Fig. 6 is the schematic diagram of step 6 of the present invention;
Fig. 7 is the schematic diagram of step 7 of the present invention;
Fig. 8 is the schematic diagram of step 8 of the present invention;
Fig. 9 is the schematic diagram of conventional groove superjunction;
Figure 10 is the puncture voltage comparison diagram that conventional groove superjunction closes super-junction structure of the present invention simulation;
Figure 11 is that the electric field that conventional groove superjunction closes super-junction structure of the present invention simulation prolongs the distribution map of the electric field of x=0.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
The embodiment of the present invention provides a kind of preparation method of hyperconjugation VDMOS, the method is: at N+ Grown the one N-epitaxial loayer, the boron first being carried out p-type impurity by reticle injects formation p-type area, continue epitaxial growth the 2nd N-epitaxial loayer, 2nd N-extension injects boron by reticle, forms body and push away trap; Then on described 2nd N-epitaxial loayer, define trench region by photoetching and carry out deep plough groove etched and backfill P-type monocrystalline silicon, forming the P-pillar district of hyperconjugation VDMOS device; Then the heat growth of grid oxygen and the deposit of N+ type polysilicon is carried out; After polysilicon photoetching, define N+ injection zone by photoetching process and inject N+ impurities, and annealing forms N+ source region; Then carry out the deposit of inter-level dielectric, and etch electrode contact; Splash-proofing sputtering metal Al, forms last device architecture after photoetching.
Describedly carry out deep plough groove etched and backfill P-type monocrystalline silicon, the P-pillar district forming hyperconjugation VDMOS device and the p-type area being positioned at a described N-epitaxial loayer are aimed at.
Described is the N-epitaxial loayer of 10-20um at N+ Grown thickness.
The embodiment of the present invention also provides a kind of hyperconjugation VDMOS device, as shown in Figure 8, this device comprises N+ substrate, a N-epitaxial loayer, the 2nd N-epitaxial loayer that superposition is arranged, p type island region is provided with in a described N-epitaxial loayer, being provided with P-pillar district in described 2nd N-epitaxial loayer, aligns with p type island region in described P-pillar district.
Distance between described P-pillar district and p type island region is 3um to 20um.
Embodiment:
The embodiment of the present invention provides a kind of preparation method of hyperconjugation VDMOS, and the method is embodied as by following steps:
Step one: as shown in Figure 1, at a N-epitaxial loayer of N+ substrate epitaxial growth thickness 10-20um, injects boron by reticle and forms p-type area.
Step 2: continued growth the 2nd N-epitaxial loayer on the first epitaxial layer, as shown in Figure 2.
Step 3: heat growth 400A oxide layer on the 2nd N-epitaxial loayer, is pushed away trap formed body by reticle implanted with p-type impurity, as shown in Figure 3.
Step 4: following reticle carries out deep plough groove etched and backfill that is p-type monocrystalline silicon, utilizes CMP technology that the p-type Si of groove outside is removed, forms p-pillar, as shown in Figure 4.
Step 5: next carry out certain thickness grid oxygen heat and grow and carry out the poly deposit of N-type doping, by reticle poly dry etching, form grid, as shown in Figure 5.
Step 6: (As or P also pushes away trap, forms N+ source region, as shown in Figure 6 then to inject N-type impurity by reticle.
Step 7: then certain thickness SiO
2layer deposit growth (i.e. ILD) go forward side by side perform hole photoetching formation contact, as shown in Figure 7.
Step 8: the sputtering of last metal A l and photoetching, form the final structure of device, as shown in Figure 8.
As shown in Figure 8,9, super-junction structure of the present invention (Fig. 8) be that conventional groove super-junction structure (Fig. 9) contrasts, wherein gash depth is identical with whole epitaxy layer thickness.
Figure 10 is the puncture voltage comparison diagram that conventional groove superjunction closes super-junction structure of the present invention simulation, wherein gash depth is identical with whole epitaxy layer thickness, from the puncture voltage result of simulation, the present invention introduces the p-type area of embedding, effectively can improve the puncture voltage of device.
Figure 11 is that the electric field that conventional groove superjunction closes super-junction structure of the present invention simulation prolongs the Electric Field Distribution of x=0, wherein gash depth is identical with whole epitaxy layer thickness, puncture voltage is exactly electric field integration in the y-direction, because the present invention embeds the introducing of p-type area, electric field is made to decline more mild at tail end, thus make the integral area of electric field larger, thus puncture voltage increases.
Bottom the p-pillar of superjunction, inject an Embedded p-type area, this p-type area and superjunction p-pillar aim at.
The p-pillar of described p-type area and superjunction is disjunct, distance from 3um to 20um within.
The above, be only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.
Claims (6)
1. the preparation method of a hyperconjugation VDMOS, it is characterized in that, the method is: at N+ Grown the one N-epitaxial loayer, the boron first being carried out p-type impurity by reticle injects formation p-type area, continue epitaxial growth the 2nd N-epitaxial loayer, 2nd N-extension injects boron by reticle, forms body and push away trap; Then on described 2nd N-epitaxial loayer, define trench region by photoetching and carry out deep plough groove etched and backfill P-type monocrystalline silicon, forming the P-pillar district of hyperconjugation VDMOS device; Then the heat growth of grid oxygen and the deposit of N+ type polysilicon is carried out; After polysilicon photoetching, define N+ injection zone by photoetching process and inject N+ impurities, and annealing forms N+ source region; Then carry out the deposit of inter-level dielectric, and etch electrode contact; Splash-proofing sputtering metal Al, forms last device architecture after photoetching.
2. the preparation method of hyperconjugation VDMOS according to claim 1, is characterized in that: described in carry out deep plough groove etched formation deep trench and be positioned at a described N-epitaxial loayer p-type area aim at.
3. the preparation method of hyperconjugation VDMOS according to claim 1 and 2, is characterized in that: described is the N-epitaxial loayer of 10-20um at N+ Grown thickness.
4. the preparation method of hyperconjugation VDMOS according to claim 3, is characterized in that: described N+ impurities is As or P.
5. a hyperconjugation VDMOS device, it is characterized in that, this device comprises N+ substrate, a N-epitaxial loayer, the 2nd N-epitaxial loayer that superposition is arranged, and is provided with p type island region in a described N-epitaxial loayer, being provided with P-pillar district in described 2nd N-epitaxial loayer, aligns with p type island region in described P-pillar district.
6. hyperconjugation VDMOS device according to claim 5, is characterized in that: the distance between described P-pillar district and p type island region is 3um to 20um.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106206742A (en) * | 2016-09-12 | 2016-12-07 | 厦门元顺微电子技术有限公司 | The high-voltage MOSFET in a kind of superjunction P district with Heterogeneous Permutation and manufacture method thereof |
| CN107768443A (en) * | 2016-08-15 | 2018-03-06 | 深圳尚阳通科技有限公司 | Superjunction devices and its manufacture method |
| CN108598148A (en) * | 2018-04-19 | 2018-09-28 | 北京工业大学 | A kind of radioresistance MOSFET structure with p-type island buffer layer structure |
| CN109087866A (en) * | 2018-04-19 | 2018-12-25 | 北京工业大学 | The n-MOSFET preparation method of boron injection composite double layer extension before a kind of extension |
| CN110224017A (en) * | 2019-04-30 | 2019-09-10 | 上海功成半导体科技有限公司 | Super junction device structure and preparation method thereof |
| CN113808946A (en) * | 2020-06-12 | 2021-12-17 | 芯恩（青岛）集成电路有限公司 | Super junction power device and preparation method thereof |
| CN113808944A (en) * | 2020-06-12 | 2021-12-17 | 芯恩（青岛）集成电路有限公司 | Super junction power device and preparation method thereof |
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| US20020079535A1 (en) * | 1999-05-12 | 2002-06-27 | Jenoe Tihanyi | Low impedance VDMOS semiconductor component |
| CN102142459A (en) * | 2010-12-23 | 2011-08-03 | 上海北京大学微电子研究院 | Coolmos structure |
| US20110233656A1 (en) * | 2010-03-24 | 2011-09-29 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
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Patent Citations (3)
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| US20020079535A1 (en) * | 1999-05-12 | 2002-06-27 | Jenoe Tihanyi | Low impedance VDMOS semiconductor component |
| US20110233656A1 (en) * | 2010-03-24 | 2011-09-29 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107768443A (en) * | 2016-08-15 | 2018-03-06 | 深圳尚阳通科技有限公司 | Superjunction devices and its manufacture method |
| CN107768443B (en) * | 2016-08-15 | 2020-12-08 | 深圳尚阳通科技有限公司 | Super junction device and manufacturing method thereof |
| CN106206742A (en) * | 2016-09-12 | 2016-12-07 | 厦门元顺微电子技术有限公司 | The high-voltage MOSFET in a kind of superjunction P district with Heterogeneous Permutation and manufacture method thereof |
| CN106206742B (en) * | 2016-09-12 | 2022-11-22 | 厦门元顺微电子技术有限公司 | High-voltage MOSFET (Metal-oxide-semiconductor field Effect transistor) with super junction P area in staggered arrangement and manufacturing method thereof |
| CN108598148A (en) * | 2018-04-19 | 2018-09-28 | 北京工业大学 | A kind of radioresistance MOSFET structure with p-type island buffer layer structure |
| CN109087866A (en) * | 2018-04-19 | 2018-12-25 | 北京工业大学 | The n-MOSFET preparation method of boron injection composite double layer extension before a kind of extension |
| CN109087866B (en) * | 2018-04-19 | 2021-01-05 | 北京工业大学 | Preparation method of n-MOSFET (metal-oxide-semiconductor field effect transistor) with boron injection before epitaxy composite double-layer epitaxy |
| CN108598148B (en) * | 2018-04-19 | 2021-01-05 | 北京工业大学 | Radiation-resistant MOSFET structure with P-type island buffer layer structure |
| CN110224017A (en) * | 2019-04-30 | 2019-09-10 | 上海功成半导体科技有限公司 | Super junction device structure and preparation method thereof |
| CN113808946A (en) * | 2020-06-12 | 2021-12-17 | 芯恩（青岛）集成电路有限公司 | Super junction power device and preparation method thereof |
| CN113808944A (en) * | 2020-06-12 | 2021-12-17 | 芯恩（青岛）集成电路有限公司 | Super junction power device and preparation method thereof |
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| CN105489500B (en) | 2018-08-07 |
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