CN103236437B - High-reliability N-type transverse insulated gate bipolar device and preparation process thereof - Google Patents

High-reliability N-type transverse insulated gate bipolar device and preparation process thereof Download PDF

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CN103236437B
CN103236437B CN201310148959.5A CN201310148959A CN103236437B CN 103236437 B CN103236437 B CN 103236437B CN 201310148959 A CN201310148959 A CN 201310148959A CN 103236437 B CN103236437 B CN 103236437B
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layer
trap
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CN103236437A (en
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刘斯扬
于朝辉
于冰
张春伟
孙伟锋
陆生礼
时龙兴
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东南大学
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Abstract

The invention relates to a high-reliability N-type transverse insulated gate bipolar device and a preparation process thereof. The high-reliability N-type transverse insulated gate bipolar device comprises a P-type substrate. Buried oxides are arranged on the P-type substrate. An N-type well is arranged on the buried oxides. An N-type buffer well and a P-type body region are arranged in the N-type well. A P-type anode region is arranged in the N-type buffer well. An N-type cathode region and a P-type body contact region are arranged in the P-type body region. A field oxidation layer is arranged on the surface of the N-type well. A polycrystalline silicon gate is arranged on the surface of the P-type body region. Passivation layers are respectively arranged on the surfaces of the field oxidation layer, the P-type body contact region, the N-type cathode region, the polycrystalline silicon gate and the P-type anode region. The high-reliability N-type transverse insulated gate bipolar device is characterized in that the thickness of the field oxidation layer which is embedded in the N-type well accounts for 60-80 percent of total thickness and the ratio of the thickness of the part exposed out of the N-type well of the field oxidation layer to the thickness of the part embedded in the N-type well of the field oxidation layer is enabled to be 2:3 to 1:4. Therefore, the electric field intensity and the impact ionization rate at the bird's beak of the device are obviously weakened and the reliability of the device is greatly improved.

Description

A kind of N-type lateral insulated gate bipolar device of high reliability and preparation technology thereof

Technical field

The present invention relates generally to field of high voltage power semiconductor devices, specifically, be a kind of N-type lateral insulated gate bipolar device and preparation technology thereof with high reliability, be applicable to the driving chip such as plasma flat-plate display device, half-bridge drive circuit and automobile production field.

Background technology

Along with the development of high voltage integrated circuit is more and more rapider, technology is also improving constantly, landscape insulation bar double-pole-type transistor (Lateral Insulated Gate Bipolar Transistor under these circumstances, LIGBT) come out, the working mechanism of its uniqueness, namely the working mechanism that combines with bipolar device of MOS device, reduces conducting resistance to a great extent, substantially increases the performance of device and circuit.Because LIGBT devices function is under the environment of high voltage, big current, be thus faced with very severe integrity problem.The channel region end of LIGBT device also has the risk producing high field intensity near drift region, and then causes hot carrier's effect and have a strong impact on the degeneration generation of device, also has serious restriction in addition to puncture voltage.Therefore, probe into its operating characteristic and improve the application tool of device reliability to LIGBT as far as possible and be of great significance.

How compatible with CMOS technology and device reliability is improved more significantly in the basis not increasing process costs, it is the key problem that high-performance LIGBT preparation technology will solve.Because oxygen is at SiO 2in diffusion coefficient limited, oxidation rate can be reduced to zero gradually along with the increase of oxidated layer thickness, thus terminating the growth of oxide layer, when making to grow oxide layer there is an extreme value in the consumption of silicon, and the consumption of general silicon is approximately 44% of final oxidated layer thickness.In common LIGBT preparation technology, device only needs primary field oxide layer growth, and the part making field oxide expose N-type trap is like this about 5:4 with the thickness proportion of the part embedding N-type trap.In this case the electric field line below device beak is intensive, and electric field strength is large, and impact ionization rate is remarkable, and device reliability is unsatisfactory.The common process basic step of preparation LIGBT device is as follows:

Step one, by P type substrate and P-type silicon layer bonding; The bonding dynamics of annealing enhancing two disks; Thinning P-type silicon layer is carried out to designed thickness by grinding, polishing;

Step 2, injects phosphorus impurities in P-type silicon layer, is advanced form N-type trap by high temperature; Inject boron and form P type tagma, then inject phosphorus and form N-type buffering trap;

Step 3, the sacrificial oxide layer of growth 45 ~ 55 nanometers, and the silicon nitride of deposit 140 ~ 160 nanometer, photoetching, development etch the silicon nitride of field oxide overlying regions; At 950 DEG C, O 2and H 2the ratio of volume content is grow field oxide in the atmosphere of 7:13 70 minutes, and then at 950 DEG C, O 2be grow field oxide in the atmosphere of 16:0.32 20 minutes with the ratio of HCL volume content, then complete the growth of field oxide;

Step 4, grows gate oxide and depositing polysilicon grid;

Step 5, injects phosphorus and arsenic forms N-type cathodic region; Injection boron fluoride and boron form p type anode district and P type body contact zone; Annealing activator impurity ion;

Step 6, passivation, etching oxidation layer form contact hole; Metal level deposit, photoetching, etching, form the first metal layer and the second metal level.

Summary of the invention

The invention provides a kind of N-type lateral insulated gate bipolar device and preparation technology thereof of high reliability, the present invention can improve the electrology characteristic of N-type lateral insulated gate bipolar device and the reliability of device.

The present invention adopts following technical scheme: a kind of N-type landscape insulation bar double-pole-type transistor of high reliability, comprise: P type substrate, P type substrate is provided with and buries oxygen, be provided with N-type trap burying on oxygen, N-type buffering trap and P type tagma is provided with in the inside of N-type trap, p type anode district is provided with in N-type buffering trap, N-type cathodic region and P type body contact zone is provided with in P type tagma, field oxide is provided with and one end of field oxide extends to p type anode district and terminates in p type anode district on the surface of N-type trap, the other end extends to P type tagma and terminates in front end, P type tagma, polysilicon gate is provided with and polysilicon gate extends to the portion of upper surface of field oxide on the surface in P type tagma, at field oxide, P type body contact zone, N-type cathodic region, the surface in polysilicon gate and p type anode district is provided with passivation layer, the first metal layer is connected with on surface, p type anode district, the second metal level is connected with in P type body contact zone and surface, N-type cathodic region.

The preparation method of the N-type lateral insulated gate bipolar device of described high reliability:

Step one, to get two resistivity be 25 Ω cm thickness is the P-type silicon layer of 500 ~ 600 microns, oxidation growth oxide layer respectively in every sheet P-type silicon layer; By two P-type silicon layer bondings at 15 DEG C ~ 35 DEG C, form oxygen buried layer, the bonding dynamics of annealing enhancing two disks; Carry out skiving side P-type silicon layer to 6 ~ 7 microns by grinding, polishing and corrosion, do basis for forming N-type trap, opposite side P-type silicon layer directly makes P type substrate;

Step 2 is 2.5e12 cm at 6 ~ 7 microns of P-type silicon layer implantation dosages -2, energy is the phosphorus impurities of 120Kev, advance at 1150 DEG C and form N-type trap; Photoetching, doped region is determined in development, and implantation dosage is 5e13 cm -2, energy be 120Kev boron formed P type tagma, then implantation dosage is 1.8e13 cm -2, energy be 140Kev phosphorus formed N-type buffering trap;

Step 3, the first sacrificial oxide layer of growth 45 ~ 55 nanometers above N-type buffering trap, N-type trap and P type tagma, and the first silicon nitride of deposit 140 ~ 160 nanometer, photoetching, development etching are carried out to the first silicon nitride, one end of etch areas is positioned at N-type buffering trap, and the other end and the P type tagma of etch areas offset; At 950 DEG C, O 2and H 2the ratio of volume content is grow field oxide in the atmosphere of 7:13 70 minutes, and then at 950 DEG C, O 2be grow field oxide in the atmosphere of 16:0.32 20 minutes with the ratio of HCL volume content, form transition field oxide in etch areas; Again first sacrificial oxide layer of transition field oxide, the first remaining silicon nitride and remnants is all etched, form groove on 6 ~ 7 microns of P-type silicon layer surfaces;

Step 4, the second sacrificial oxide layer of growth 45 ~ 55 nanometers above N-type buffering trap, N-type trap and P type tagma, and the second silicon nitride of deposit 140 ~ 160 nanometer, photoetching, development and etched recesses above the second silicon nitride, expose the groove etched in previous step; At 950 DEG C, O 2and H 2the ratio of volume content is grow field oxide in the atmosphere of 7:13 70 minutes, and then at 950 DEG C, O 2be grow field oxide in the atmosphere of 16:0.32 20 minutes with the ratio of HCL volume content, in groove, form field oxide; Second silicon nitride of remnants and the second remaining sacrificial oxide layer are all etched;

Step 5, the gate oxide of growth 23 ~ 27 nanometers, the polysilicon gate that then under 950 DEG C of environment, deposition thickness is 400 ~ 440 nanometers, resistivity is 6.4e-4 Ω cm;

Step 6, by mask blank Selective ion mode injection zone, in P type tagma, implantation dosage is 6e13 cm -2, energy be the phosphorus of 50Kev and dosage is 5e15 cm -2, energy is the arsenic of 80Kev, forms N-type cathodic region; In N-type buffering trap, implantation dosage is 5e15 cm -2, energy be the boron fluoride of 80Kev and dosage is 5e15 cm -2, energy is the boron of 140Kev, forms p type anode district, in P type tagma, implantation dosage is 5e15 cm simultaneously -2, energy be the boron fluoride of 80Kev and dosage is 5e15 cm -2, energy is the boron of 140Kev, forms P type body contact zone; Annealing activator impurity ion;

Step 7, passivation forms passivation layer, and etching oxidation layer forms contact hole; Carry out Metal deposition, photoetching, etching again, form the first metal layer and the second metal level.

Compared with prior art, tool of the present invention has the following advantages:

(1), device technology of the present invention, overcome field oxide 8 in general preparation technology and embed the limit of N-type trap 3 degree of depth (under general preparation technology, the thickness that field oxide 8 embeds N-type trap 3 accounts for 44% of the gross thickness of field oxide 8), the thickness that field oxide 8 embeds N-type trap 3 reaches 60% ~ 80% of field oxide 8 gross thickness, and accompanying drawing 30 obviously can find out the effect of this technique.

(2), in device of the present invention, it is darker that field oxide 8 embeds N-type trap 3, insert depth accounts for 60% ~ 80% of whole field oxide thickness, the part making field oxide 8 expose N-type trap 3 is 2:3 to 1:4 with the thickness proportion of the part embedding N-type trap 3, on grid, the inversion layer width of positive voltage induction is larger, slow down electric field strength to raise and the speed of rising with grid voltage, reduce in identical grid voltage lower channel longitudinal electric field intensity simultaneously, improve device ON state, breakdown voltage.Can find out that the breakdown voltage of device significantly improves from accompanying drawing 33; Accompanying drawing 34 can illustrate that device ON state puncture voltage also significantly improves.

(3), in device of the present invention, it is darker that field oxide 8 embeds N-type trap 3, insert depth accounts for 60% ~ 80% of whole field oxide thickness, the part making field oxide 8 expose N-type trap 3 is 2:3 to 1:4 with the thickness proportion of the part embedding N-type trap 3, power line face south polar region extruding, to make under ON state the density of electric fluxline comparatively before sparse (accompanying drawing 31 is for adopting device power line chart after the present invention, accompanying drawing 32 is device power line chart before employing the present invention), thus electric field strength reduces, reduce the impact ionization rate at beak place simultaneously, hot carrier's effect is eased, improve the reliability of device.As can be seen from accompanying drawing 35, beak place (x=13 ~ 15 micron) impact ionization rate obviously reduces, and device reliability is improved.

(4), device of the present invention adopts and generates field oxide technique twice, and this technique easily realizes, and can not increase extra cost.In addition, device making technics of the present invention can be compatible with existing CMOS technology, is easy to preparation.

(5), device of the present invention can not only improve reliability effectively, and because device channel region carrier concentration does not become, the length of raceway groove and width do not become; And gate oxide thickness and growth of gate oxide layer environment do not become, so the almost no change of the threshold voltage of device, as shown in Figure 36, before and after device improvements, threshold voltage is all between 0.75 ~ 0.85 volt.

Accompanying drawing explanation

Fig. 1 be for the present invention improve after the cross-section structure of N-type lateral insulated gate bipolar device.

Below the technological process after device improvements:

Fig. 2 is step one (1), the two panels P-type silicon layer namely after thermal oxidation.

Fig. 3 is step one (2), i.e. two panels P-type silicon layer bonding.

Fig. 4 is step one (3), and namely skiving side P-type silicon layer is to 6 ~ 7 microns, retains opposite side P-type silicon layer thickness and makes P type substrate.

Fig. 5 is step 2 (1), injects phosphorus impurities form N-type trap by 6 ~ 7 microns of P-type silicon layer.

Fig. 6 is step 2 (2), namely injects corresponding impurity and forms P type tagma and N-type buffering trap.

Fig. 7 is step 3 (1), namely above N-type buffering trap, N-type trap and P type tagma, grows the first sacrificial oxide layer, and deposit first silicon nitride.

Fig. 8 is step 3 (2), namely carries out photoetching, development etching to the first silicon nitride, and one end of etch areas is positioned at N-type buffering trap, and the other end and the P type tagma of etch areas offset.

Fig. 9 is step 3 (3), namely at etch areas growth transition field oxide.

Figure 10 is step 3 (4), all etches, obtain groove by transition field oxide, remaining first silicon nitride and remaining first sacrificial oxide layer.

Figure 11 is step 4 (1), namely above N-type buffering trap, groove and P type tagma, grows the second sacrificial oxide layer, and deposit second silicon nitride.

Figure 12 is step 4 (2), i.e. photoetching, development the second silicon nitride etched above the groove of field, expose the groove etched in previous step.

Figure 13 is step 4 (3), namely in groove, forms field oxide.

Figure 14 is step 4 (4), all etches by remaining second silicon nitride and remaining second sacrificial oxide layer.

Figure 15 is the device complete graph after step 4 completes.

Figure 16 is step 5 (1), namely grows gate oxide.

Figure 17 is step 5 (2), namely clicks polysilicon gate.

Figure 18 is the device complete graph after step 5 completes.

Figure 19 is step 6, namely forms N-type cathodic region, p type anode district and P type body contact zone.

Figure 20 is step 7, namely forms passivation layer, the first metal layer and the second metal level.

General preparation technology's flow chart below:

Figure 21 is step one, and namely two P-type silicon layer are through thermal oxidation, bonding, then by a P-type silicon layer skiving to 6 ~ 7 microns.

Figure 22 is step 2, namely forms N-type trap, P type tagma and N-type buffering trap.

Figure 23 is step 3 (1), namely above N-type buffering trap, N-type trap and P type tagma, grows sacrificial oxide layer, and deposit silicon nitride.

Figure 24 is step 3 (2), namely carries out photoetching, development etching to silicon nitride, and one end of etch areas is positioned at N-type buffering trap, and the other end and the P type tagma of etch areas offset.

Figure 25 is step 3 (3), namely at etch areas growth field oxide.

Figure 26 is the device complete graph after step 3 completes.

Figure 27 is step 4, namely grows gate oxide and depositing polysilicon grid.

Figure 28 is step 5, namely forms N-type cathodic region, p type anode district and P type body contact zone.

Figure 29 is step 6, namely forms passivation layer, the first metal layer and the second metal level.

Figure 30 is present invention process and general technology effect contrast figure.

Figure 31 is device power line chart after process modification, is the density of electric fluxline contrast district in black circles.

Figure 32 is device power line chart before process modification, and be the density of electric fluxline contrast district in black circles, through comparing Figure 31 and Figure 32, after obviously can finding out process modification, below beak, the density of electric fluxline is more sparse than the density of electric fluxline below general technology device beak.

Figure 33 is the OFF state anode voltage current curve comparison diagram of device of the present invention and general device, and can obviously find out from figure, the puncture voltage of the device after improvement obviously promotes.

Figure 34 is the ON state anode voltage current curve comparison diagram of device of the present invention and general device, and can obviously find out from figure, the puncture voltage of the device after improvement obviously promotes.

Figure 35 is the comparison diagram of the hot carrier impact ionization rate of device of the present invention and general device surface area, as can be seen from the figure the impact ionization rate of beak place (x=13 ~ 15 micron) obviously reduces, namely hot-carrier concern improves, and the reliability of device is improved.

Figure 36 is the transfer characteristic curve comparison diagram of device of the present invention and general device, can obviously find out from figure, and before and after improving, the threshold voltage of device has almost no change.

Embodiment

Below in conjunction with accompanying drawing 2, the present invention is elaborated, a kind of N-type lateral insulated gate bipolar device of high reliability, comprise: P type substrate 1, P type substrate 1 is provided with and buries oxygen 2, be provided with N-type trap 3 burying on oxygen 2, N-type buffering trap 4 and P type tagma 13 is provided with in the inside of N-type trap 3, p type anode district 5 is provided with in N-type buffering trap 4, N-type cathodic region 12 and P type body contact zone 11 is provided with in P type tagma 13, field oxide 8 is provided with and one end of field oxide 8 extends to p type anode district 5 and terminates in p type anode district 5 on the surface of N-type trap 3, the other end extends to P type tagma 13 and terminates in front end, P type tagma 13, polysilicon gate 9 is provided with and polysilicon gate 9 extends to the portion of upper surface of field oxide 8 on the surface in P type tagma 13, at field oxide 8, P type body contact zone 11, N-type cathodic region 12, the surface in polysilicon gate 9 and p type anode district 5 is provided with passivation layer 7, the first metal layer 6 is connected with on surface, p type anode district 5, the second metal level 10 is connected with in P type body contact zone 11 and surface, N-type cathodic region 12.

Make the N-type lateral insulated gate bipolar device of high reliability as above, concrete steps are as follows:

Step one, to get two resistivity be 25 Ω cm thickness is the P-type silicon layer of 500 ~ 600 microns, thermal oxide growth oxide layer respectively in every sheet P-type silicon layer; By two P-type silicon layer bondings at 15 DEG C ~ 35 DEG C, form oxygen buried layer 2, the bonding dynamics of annealing enhancing two disks; Carry out skiving side P-type silicon layer to 6 ~ 7 microns by grinding, polishing, do basis for forming N-type trap 3, opposite side P-type silicon layer directly makes P type substrate 1;

Step 2 is 2.5e12 cm at 6 ~ 7 microns of P-type silicon layer implantation dosages -2, energy is 120Kev phosphorus impurities, advance at 1150 DEG C and form N-type trap 3; Photoetching, doped region is determined in development, and implantation dosage is 5e13 cm -2, energy be 120Kev boron formed P type tagma 13, then implantation dosage is 1.8e13 cm -2, energy be 140Kev phosphorus formed N-type buffering trap 4;

Step 3, first sacrificial oxide layer of growth 45 ~ 55 nanometers above N-type buffering trap 4, N-type trap 3 and P type tagma 13, and the first silicon nitride of deposit 140 ~ 160 nanometer, photoetching, development etching are carried out to the first silicon nitride, one end of etch areas is positioned at N-type buffering trap 4, and the other end and the P type tagma 13 of etch areas offset; At 950 DEG C, O 2and H 2the ratio of volume content is grow field oxide in the atmosphere of 7:13 70 minutes, and then at 950 DEG C, O 2be grow field oxide in the atmosphere of 16:0.32 20 minutes with the ratio of HCL volume content, form transition field oxide in etch areas; Again transition field oxide, remaining first silicon nitride and remaining first are sacrificed field oxide and all etched, form groove on 6 ~ 7 microns of P-type silicon layer surfaces;

Step 4, second sacrificial oxide layer of growth 45 ~ 55 nanometers above N-type buffering trap 4, groove and P type tagma 13, and the second silicon nitride of deposit 140 ~ 160 nanometer, photoetching, development and etched recesses above the second silicon nitride, expose the groove etched in previous step; At 950 DEG C, O 2and H 2the ratio of volume content is grow gate oxide in the atmosphere of 7:13 70 minutes, and then at 950 DEG C, O 2be grow gate oxide in the atmosphere of 16:0.32 20 minutes with the ratio of HCL volume content, in groove, form field oxide 8; Second silicon nitride of remnants and the second remaining sacrificial oxide layer are all etched;

Step 5, the gate oxide of growth 23 ~ 27 nanometers, the polysilicon gate 9 that then under 950 DEG C of environment, deposition thickness is 400 ~ 440 nanometers, resistivity is 6.4e-4 Ω cm;

Step 6, by mask blank Selective ion mode injection zone, in P type tagma 13, implantation dosage is 6e13 cm -2, energy be the phosphorus of 50Kev and dosage is 5e15 cm -2, energy is the arsenic of 80Kev, forms N-type cathodic region 12; In N-type buffering trap 4, implantation dosage is 5e15 cm -2, energy be the boron fluoride of 80Kev and dosage is 5e15 cm -2, energy is the boron of 140Kev, forms p type anode district 5, in p-type body district 13, implantation dosage is 5e15 cm simultaneously -2, energy be the boron fluoride of 80Kev and dosage is 5e15 cm -2, energy is the boron of 140Kev, forms P type body contact zone 11; Annealing activator impurity ion;

Step 7, passivation forms passivation layer 7, and etching oxidation layer forms contact hole; Carry out metal level deposit, photoetching, etching again, form the first metal layer 6 and the second metal level 10.

Claims (1)

1. a preparation technology for the N-type lateral insulated gate bipolar device of high reliability, is characterized in that:
Step one, to get two resistivity be 25 Ω cm thickness is the P-type silicon layer of 500 ~ 600 microns, thermal oxide growth oxide layer respectively in every sheet P-type silicon layer; By two P-type silicon layer bondings at 15 DEG C ~ 35 DEG C, form oxygen buried layer (2), the bonding dynamics of annealing enhancing two disks; Carry out skiving side P-type silicon layer to 6 ~ 7 microns by grinding, polishing, do basis for forming N-type trap (3), opposite side P-type silicon layer directly makes P type substrate (1);
Step 2 is 2.5e12cm at 6 ~ 7 microns of P-type silicon layer implantation dosages -2, energy is the phosphorus impurities of 120Kev, advance at 1150 DEG C and form N-type trap (3); Photoetching, development determines that doped region is near N-type cathodic region (12), and implantation dosage is 5e13cm -2, energy is that the boron of 120Kev forms P type tagma (13), and then photoetching, development determines that doped region is near p type anode district (5), and implantation dosage is 1.8e13cm -2, energy be 140Kev phosphorus formed N-type buffering trap (4);
Step 3, at the first sacrificial oxide layer of top growth 45 ~ 55 nanometers in N-type buffering trap (4), N-type trap (3) and P type tagma (13), and the first silicon nitride of deposit 140 ~ 160 nanometer, photoetching, development etching are carried out to the first silicon nitride, one end of etch areas is positioned at N-type buffering trap (4), and the other end and the P type tagma (13) of etch areas offset; At 950 DEG C, O 2and H 2the ratio of volume content is grow field oxide in the atmosphere of 7:13 70 minutes, and then at 950 DEG C, O 2be grow field oxide in the atmosphere of 16:0.32 20 minutes with the ratio of HCL volume content, form transition field oxide in etch areas; Sacrifice field oxide by first of transition field oxide, the first remaining silicon nitride and remnants more all to etch, form groove on 6 ~ 7 microns of P-type silicon layer surfaces;
Step 4, at the second sacrificial oxide layer of top growth 45 ~ 55 nanometers in N-type buffering trap (4), groove and P type tagma (13), and the second silicon nitride of deposit 140 ~ 160 nanometer, photoetching, development and etched recesses above the second silicon nitride, expose the groove etched in previous step; At 950 DEG C, O 2and H 2the ratio of volume content is grow gate oxide in the atmosphere of 7:13 70 minutes, and then at 950 DEG C, O 2be grow gate oxide in the atmosphere of 16:0.32 20 minutes with the ratio of HCL volume content, in groove, form field oxide (8); Second silicon nitride of remnants and the second remaining sacrificial oxide layer are all etched;
Step 5, the gate oxide of growth 23 ~ 27 nanometers, the polysilicon gate (9) that then under 950 DEG C of environment, deposition thickness is 400 ~ 440 nanometers, resistivity is 6.4e-4 Ω cm;
Step 6, by mask blank Selective ion mode injection zone, in P type tagma (13), implantation dosage is 6e13cm -2, energy be the phosphorus of 50Kev and dosage is 5e15cm -2, energy is the arsenic of 80Kev, forms N-type cathodic region (12); In N-type buffering trap (4), implantation dosage is 5e15cm -2, energy be the boron fluoride of 80Kev and dosage is 5e15cm -2, energy is the boron of 140Kev, forms p type anode district (5), in P type tagma (13), implantation dosage is 5e15cm simultaneously -2, energy be the boron fluoride of 80Kev and dosage is 5e15cm -2, energy is the boron of 140Kev, forms P type body contact zone (11); Annealing activator impurity ion;
Step 7, passivation forms passivation layer (7), and etching oxidation layer forms contact hole; Carry out metal level deposit, photoetching, etching again, form the first metal layer (6) and the second metal level (10).
CN201310148959.5A 2013-04-25 2013-04-25 High-reliability N-type transverse insulated gate bipolar device and preparation process thereof CN103236437B (en)

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Publication number Priority date Publication date Assignee Title
US5670396A (en) * 1995-11-21 1997-09-23 Lucent Technologies Inc. Method of forming a DMOS-controlled lateral bipolar transistor
CN102437181A (en) * 2011-12-08 2012-05-02 东南大学 N type silicon on insulator transverse insulated gate bipolar device

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Publication number Priority date Publication date Assignee Title
US5670396A (en) * 1995-11-21 1997-09-23 Lucent Technologies Inc. Method of forming a DMOS-controlled lateral bipolar transistor
CN102437181A (en) * 2011-12-08 2012-05-02 东南大学 N type silicon on insulator transverse insulated gate bipolar device

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