CN105448722B - A kind of production method and semiconductor device of superjunction semiconductor field - Google Patents
A kind of production method and semiconductor device of superjunction semiconductor field Download PDFInfo
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- CN105448722B CN105448722B CN201410383910.2A CN201410383910A CN105448722B CN 105448722 B CN105448722 B CN 105448722B CN 201410383910 A CN201410383910 A CN 201410383910A CN 105448722 B CN105448722 B CN 105448722B
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Abstract
The invention discloses the production methods and semiconductor device of a kind of superjunction semiconductor field to simplify manufacture craft, reduce cost of manufacture to optimize production process.The production method of the superjunction semiconductor field, including the first conductive type epitaxial layer, the first protective layer are successively made on a semiconductor substrate；The first conductive type epitaxial layer without the protection of the first protective layer is etched, first groove is formed；The second protective layer is made in the semiconductor substrate for be formed with first groove；The second protective layer is etched, forms the second protective layer side wall in the side wall of first groove；The first conductive type epitaxial layer without the first protective layer and the second protective layer side wall protection is etched, second groove is formed；The second conductive type epitaxial layer is made in second groove；The second protective layer side wall is removed, the second conductive type epitaxial layer is made in first groove；The depth of first groove is less than the depth of second groove；The material of the material of first protective layer and the second protective layer is different.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of production methods and half of superjunction semiconductor field
Conductor device.
Background technique
The semiconductor devices of super-junction structure, it has also become the important trend of device development, the prior art are aoxidized in superjunction metal
Object semiconductor field effect pipe (Metal Oxide Semiconductor Field Effect Transistor, MOSFET),
I.e. in the manufacture of metal-oxide-semiconductor, one of way is that deep trench is etched in N-type epitaxy layer, then the growing P-type in deep trench
Then extension further makes polysilicon gate, the injection in the area PXing Ti is carried out in the polysilicon window of etching and is driven in, from
And form the area PXing Ti.
Specifically, it as shown in Figure 1, growing N-type epitaxy layer 11 in N-type substrate 10, is grown in N-type epitaxy layer 11 initial
Then oxide layer 12 gets rid of the initial oxide layer for needing to etch at deep trench region, etch deep trench 13, in deep trench 13
Interior growing P-type epitaxial layer 20, as shown in Fig. 2, then falling extra p-type epitaxial layer grinding and polishing, as shown in figure 3, later again
Gate oxide 40 is grown, as shown in figure 4, the growing polycrystalline silicon grid layer 41 on gate oxide 40 again, then etching gets rid of portion
Point polycrystalline silicon gate layer, as shown in figure 5, carry out the injection of P-type ion again and drive in, due to polycrystalline silicon gate layer thickness compared with
Thickness, therefore, the region P-type ion for having polycrystalline silicon gate layer to cover will not be injected into N-type epitaxy layer 11 below, no polycrystalline
The region P-type ion of polysilicon gate layer covering can be injected into p-type epitaxial layer 20 below, then again to the P-type ion of injection
It carries out high temperature and drives in processing, under high temperature action, the P-type ion of injection will do it horizontal proliferation, in this way, just in p-type epitaxial layer
In form the body area of superjunction MOS.As shown in fig. 6, photoresist is coated in the N-type substrate 10 for being formed with polycrystalline silicon gate layer,
And the photoresist of coating is exposed, is developed, photoresist 60 shown in fig. 6 is eventually formed, N-type ion is then reinjected,
The region that no polycrystalline silicon gate layer 41 and photoresist 60 cover, N-type ion can be injected into p-type epitaxial layer below, form N
Then+source area 61 makes between dielectric layer 70 and dielectric layer in the N-type substrate of formation N+ source area shown in Fig. 6
Contact hole finally forms metal layer 71, as shown in Figure 7 on dielectric layer.
In conclusion the prior art during making superjunction MOS, needs to carry out P-type ion when forming the area PXing Ti
Injection with drive in, complex manufacturing technology, and manufacturing cost is higher.
Summary of the invention
The embodiment of the invention provides the production methods and semiconductor device of a kind of superjunction semiconductor field, to excellent
Change production process, simplify manufacture craft, reduces cost of manufacture.
A kind of production method of superjunction semiconductor field provided in an embodiment of the present invention, comprising:
The first conductive type epitaxial layer is made on a semiconductor substrate, passes through composition work on the first conductive type epitaxial layer
Skill forms the first protective layer；
The first conductive type epitaxial layer without the protection of the first protective layer is etched, first groove is formed；
The second protective layer is made in the semiconductor substrate for be formed with first groove；
The second protective layer is etched, forms the second protective layer side wall in the side wall of first groove；
The first conductive type epitaxial layer without the first protective layer and the second protective layer side wall protection is etched, the second ditch is formed
Slot；
The second conductive type epitaxial layer is made in second groove；
The second protective layer side wall is removed, the second conductive type epitaxial layer is made in first groove；
Wherein, the depth of the first groove is less than the depth of the second groove；The material of first protective layer and
The material of second protective layer is different.
It is first due to when making groove by the production method of superjunction semiconductor field provided in an embodiment of the present invention
First groove is first produced, makes second groove again later, meanwhile, when making conductive epitaxial layer, first in second groove
The second conductive type epitaxial layer is made, makes the second conductive type epitaxial layer in first groove later, by simply growing
Second conductive type epitaxial layer forms the area PXing Ti in first groove, eliminates prior art needs when forming the area PXing Ti
The process for carrying out the injection of P-type ion and driving in simplifies manufacture craft so as to reach optimization production process, reduces production
The purpose of cost.
Preferably, the semiconductor substrate is N-type semiconductor substrate, first conductive type epitaxial layer is that N-type is conductive
Epitaxial layer, second conductive type epitaxial layer are P-type conduction epitaxial layer.
In this way, when making superjunction semiconductor field, it is more convenient, simple.
Preferably, the depth of the first groove is 1 micron to 5 microns.
In this way, the depth of first groove is 1 micron to 5 microns, it is more convenient, simple when being subsequently formed the area PXing Ti.
Preferably, the depth of the second groove is 40 microns to 50 microns.
In this way, the depth of second groove is 40 microns to 50 microns, the PN column of alternately connection can be preferably formed, half
Better super-junction structure is formed in conductor substrate.
Preferably, the material of first protective layer is silica.
In this way, make the material of the first protective layer with silica, it is more convenient in the actual production process, simple.
Preferably, the material of second protective layer is silicon nitride.
In this way, make the material of the second protective layer with silicon nitride, it is more convenient in the actual production process, simple.
Preferably, the second protective layer side wall of the removal, comprising: use hot phosphoric acid, erosion removal the second protective layer side wall.
In this way, the second protective layer side wall is removed using hot phosphoric acid, it is more convenient in the actual production process, simple.
Preferably, described form the first protective layer by patterning processes on the first conductive type epitaxial layer, comprising:
The first protective layer is deposited on the first conductive type epitaxial layer；
Photoresist is coated on first protective layer, and photoresist is exposed, is developed；
Etching removes the first protective layer of no photoresist protection, and removes remaining photoresist, forms the first protective layer.
In this way, the first protective layer is formed by the above method, it is more convenient in the actual production process, simple.
Preferably, after making the second conductive type epitaxial layer in first groove, the method also includes:
The first protective layer is removed, is successively made on first conductive type epitaxial layer and the second conductive type epitaxial layer
Gate oxide and grid layer, wherein the gate oxide covers the first conductive type epitaxial layer and the second conductive type epitaxial layer,
The grid layer covers the first conductive type epitaxial layer and the second conductive type epitaxial layer of part；
Do not formed photoresist in partial region that grid layer covers, injecting N+ ion, not by grid layer and
N+ source area is formed in p-type epitaxial layer in the first groove of photoresist overlay；
Photoresist is removed, dielectric layer is made on grid layer, metal layer is made on dielectric layer.
In this way, obtaining superjunction semiconductor field by the production that the above method can be convenient.
The embodiment of the present invention also provides a kind of semiconductor device, which includes using the prepared superjunction of the above method
Semiconductor field.
The semiconductor device provided by the present invention, due to be adopt it is prepared with the aforedescribed process, this is partly led
The manufacture craft of body device is simple, and cost of manufacture is lower.
Detailed description of the invention
Fig. 1-Fig. 7 is respectively the structural schematic diagram of the different phase of prior art production superjunction semiconductor field；
Fig. 8 is a kind of production method flow chart of superjunction semiconductor field provided in an embodiment of the present invention；
Fig. 9-Figure 19 be respectively a kind of superjunction semiconductor field provided in an embodiment of the present invention in the production process
The structural schematic diagram of different phase.
Specific embodiment
The embodiment of the invention provides the production methods and semiconductor device of a kind of superjunction semiconductor field, to excellent
Change production process, simplify manufacture craft, reduces cost of manufacture.
As shown in figure 8, the specific embodiment of the invention provides a kind of production method of superjunction semiconductor field, it is described
Method includes:
S101, the first conductive type epitaxial layer is made on a semiconductor substrate, pass through on the first conductive type epitaxial layer
Patterning processes form the first protective layer；
S102, the first conductive type epitaxial layer protected without the first protective layer is etched, forms first groove；
S103, the second protective layer is made in the semiconductor substrate for be formed with first groove；
S104, the second protective layer of etching form the second protective layer side wall in the side wall of first groove；
S105, the first conductive type epitaxial layer for etching no first protective layer and the second protective layer side wall protection, form
Second groove；
S106, the second conductive type epitaxial layer is made in second groove；
S107, the second protective layer side wall of removal, make the second conductive type epitaxial layer in first groove；
Wherein, the depth of the first groove is less than the depth of the second groove；The material of first protective layer and
The material of second protective layer is different.
The production side of the superjunction semiconductor field of specific embodiment of the invention offer is provided with reference to the accompanying drawing
Method.
As shown in figure 9, the first conductive type epitaxial layer 111 is made on semiconductor substrate 110 first, in the first conductive-type
The first protective layer 112 is formed by patterning processes on type epitaxial layer 111, wherein semiconductor substrate in the specific embodiment of the invention
110 be N-type semiconductor substrate, and the first conductive type epitaxial layer 111 is N-type conduction epitaxial layer, and the material of the first protective layer 112 is
Silica (SiO2), the growth temperature of the first protective layer 112 is about 800 DEG C to 1100 DEG C in the specific embodiment of the invention, thick
About 0.4 micron to 1.0 microns of degree, certainly, according to needs of production, the growth temperature and thickness of the first protective layer can be into
Row adjustment appropriate, the present invention do not limit it specifically.Pass through patterning processes on the first conductive type epitaxial layer 111
The process for forming the first protective layer 112 is SiO2 film to be deposited first on the first conductive type epitaxial layer 111, in deposition
Photoresist is coated on SiO2 film, and the photoresist of coating is exposed, is developed, and etching removes no photoresist protection later
SiO2 film, and remove remaining photoresist, form the first protective layer 112.Later the of first protective layer 112 protection
First groove 113 is etched on one conductive type epitaxial layer 111, the etching of first groove can lead in the specific embodiment of the invention
It crosses plasma dry etch to perform etching, the depth of the first groove 113 etched is 1 micron to 5 microns, certainly can be with
It is needed to carry out adjustment appropriate to the depth of first groove 113 according to actual production, the present invention does not limit it specifically
It is fixed.
As shown in Figure 10, the second protective layer 120, the specific embodiment of the invention are made in semiconductor substrate shown in Fig. 9
In the second protective layer 120 material be silicon nitride (SiN), the growth temperature of SiN is about 700 DEG C to 1000 DEG C, and thickness is about
0.1 micron to 0.5 micron, certainly, according to needs of production, the growth temperature and thickness of SiN can carry out adjustment appropriate,
The present invention does not limit it specifically.
As shown in figure 11, prepared second protective layer in Figure 10 is etched, forms second in the side wall of first groove 113
Protective layer side wall is etched in the specific embodiment of the invention by plasma dry etch, vertically downward due in etching process
In, etching speed vertically downward is very fast, and the etching speed of horizontal direction is slower, therefore when the second protective layer in vertical direction
When being etched away, the second protective layer of part is still remained in the side-walls of first groove 113, which is the
Two protective layer side walls 130.
As shown in figure 12, the first conduction type extension without the first protective layer and the second protective layer side wall protection is etched
Layer forms second groove 140, in the specific embodiment of the invention, forms second groove 140 by plasma dry etch,
In, the depth of second groove 140 is 40 microns to 50 microns in the specific embodiment of the invention, certainly can also be according to actual life
It produces and needs to carry out adjustment appropriate to the depth of second groove 140, the present invention does not limit it specifically.
As shown in figure 13, the second conductive type epitaxial layer 150, the specific embodiment of the invention are made in second groove 140
In the second conductive type epitaxial layer 150 be P-type conduction epitaxial layer, due to second groove 140 side wall be the first conduction type
Epitaxial layer 111, and the side wall of first groove 113 is the second protective layer SiN side wall, by the limitation of epitaxial growth technology condition, this
When the second conductive type epitaxial layer can only be grown in second groove 140, can not two conductive-type of growth regulation in first groove 113
Type epitaxial layer, at this point, the first conductive type epitaxial layer 111 and the second conductive type epitaxial layer 150 constitute the PN column of alternately connection,
Super-junction structure is formed in semiconductor substrate.
As shown in figure 14, remove the second protective layer side wall, specifically, the specific embodiment of the invention by using hot phosphoric acid,
The temperature of hot phosphoric acid is generally 180 DEG C, and erosion removal the second protective layer side wall, hot phosphoric acid only has the work of corrosion to the second protective layer
With not playing the role of corrosion to the first protective layer and the first conductive type epitaxial layer and the second conductive type epitaxial layer, when
Two protective layer side walls are corroded get rid of after, the side wall of first groove 113 is the first conductive type epitaxial layer 111, first
The second conductive type epitaxial layer 150 is made in groove 113, as shown in figure 15, at this point, grow in first groove 113 second leads
Electric type epitaxial layer 150 forms the area PXing Ti.
As shown in figure 16, the first protective layer is removed, in the first conductive type epitaxial layer 111 and the second conductive type epitaxial layer
Successively manufacturing gate oxide layers 180 and grid layer 181 on 150, wherein grid layer 181 is polysilicon layer, the specific embodiment of the invention
The growth temperature of middle gate oxide 180 is about 800 DEG C to 1100 DEG C, and thickness is about 0.05 micron to 0.2 micron, certainly, according to
Needs of production, the growth temperature and thickness of gate oxide can carry out adjustment appropriate, and the present invention does not make it specifically
Restriction.The growth temperature of grid layer 181 is about 500 DEG C to 700 DEG C in the specific embodiment of the invention, and thickness is about 0.2 micron
To 0.8 micron, certainly, according to needs of production, the growth temperature and thickness of grid layer can carry out adjustment appropriate, this hair
It is bright it not to be limited specifically.
As shown in figure 17, photoresist is coated on prepared grid layer, and photoresist is exposed, is developed, and is carved
Eating away does not have the grid layer of photoresist overlay, forms the first conductive type epitaxial layer of covering and the second conductive type epitaxial layer of part
Grid layer 181.
As shown in figure 18, not by grid layer cover partial region in formed photoresist 200, later inject N+ from
Son, N+ ion cannot penetrate the region there are grid layer and photoresist overlay and be injected into region below, and N+ ion
The region of no grid layer and photoresist overlay can be penetrated and in the p-type epitaxial layer that is injected into first groove below, shape
At N+ source area 201, the N+ injection ion in the specific embodiment of the invention is phosphonium ion, and implantation dosage is 1.0E15~1.0E16
A/cm2, Implantation Energy is 50Kev to 150Kev.
As shown in figure 19, dielectric layer 210, Jie in the specific embodiment of the invention are made on the grid layer 181 in Figure 18
The structure of matter layer is the SiO2 and phosphorosilicate glass to undope, the SiO2 to undope with a thickness of 0.2 micron, the thickness of phosphorosilicate glass
It is 0.8 micron, certainly, the thickness of the SiO2 and phosphorosilicate glass that undope can carry out tune appropriate according to needs of production
Whole, the present invention does not limit it specifically, wherein the specific production method of dielectric layer is same as the prior art, here not
It is repeated.Metal layer 211 is made on dielectric layer 210, the metal layer 211 in the specific embodiment of the invention it is micro- with a thickness of 2
Rice to 5 microns, the material of metal layer 211 be aluminium or be aluminium, silicon, copper alloy, wherein the specific production method of metal layer and existing
There is technology identical, here without repeating.
In conclusion the specific embodiment of the invention optimizes the process flow of production superjunction semiconductor field,
When etching groove, shallow trench is etched first, then produce silicon nitride spacer, side wall is then utilized to carry out the quarter of deep trench
Erosion, the growing P-type extension in deep trench, then silicon nitride spacer is removed, regrowth p-type extension, the area self-assembling formation PXing Ti saves
It the injection in the area LiaoPXing Ti and drives in.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of production method of superjunction semiconductor field, which is characterized in that the described method includes:
The first conductive type epitaxial layer is made on a semiconductor substrate, passes through patterning processes shape on the first conductive type epitaxial layer
At the first protective layer；
The first conductive type epitaxial layer without the protection of the first protective layer is etched, first groove is formed；
The second protective layer is made in the semiconductor substrate for be formed with first groove；
The second protective layer is etched, forms the second protective layer side wall in the side wall of first groove；
The first conductive type epitaxial layer without the first protective layer and the second protective layer side wall protection is etched, second groove is formed；
The second conductive type epitaxial layer is made in second groove；
The second protective layer side wall is removed, the second conductive type epitaxial layer is made in first groove；
Wherein, the depth of the first groove is less than the depth of the second groove；The material of first protective layer and described
The material of second protective layer is different.
2. the method according to claim 1, wherein the semiconductor substrate is N-type semiconductor substrate, described the
One conductive type epitaxial layer is N-type conduction epitaxial layer, and second conductive type epitaxial layer is P-type conduction epitaxial layer.
3. the method according to claim 1, wherein the depth of the first groove is 1 micron to 5 microns.
4. the method according to claim 1, wherein the depth of the second groove is 40 microns to 50 microns.
5. the method according to claim 1, wherein the material of first protective layer is silica.
6. the method according to claim 1, wherein the material of second protective layer is silicon nitride.
7. the method according to claim 1, wherein the second protective layer side wall of the removal, comprising: use hot phosphorus
Acid, erosion removal the second protective layer side wall.
8. the method according to claim 1, wherein described pass through composition work on the first conductive type epitaxial layer
Skill forms the first protective layer, comprising:
The first protective layer is deposited on the first conductive type epitaxial layer；
Photoresist is coated on first protective layer, and photoresist is exposed, is developed；
Etching removes the first protective layer of no photoresist protection, and removes remaining photoresist, forms the first protective layer.
9. the method according to claim 1, wherein making the second conductive type epitaxial layer in first groove
Afterwards, the method also includes:
The first protective layer is removed, successively makes grid oxygen on first conductive type epitaxial layer and the second conductive type epitaxial layer
Change layer and grid layer, wherein the gate oxide covers the first conductive type epitaxial layer and the second conductive type epitaxial layer, described
Grid layer covers the first conductive type epitaxial layer and the second conductive type epitaxial layer of part；
Photoresist is not being formed in partial region that grid layer covers, the first conductive type ion is injected, not by grid
The first conductive type source area is formed in the second conductive type epitaxial layer in the first groove of pole layer and photoresist overlay；
Photoresist is removed, dielectric layer is made on grid layer, metal layer is made on dielectric layer.
10. a kind of semiconductor device, which is characterized in that described device includes making to obtain using any claim of claim 1-9
Superjunction semiconductor field.
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| CN201410383910.2A CN105448722B (en) | 2014-08-06 | 2014-08-06 | A kind of production method and semiconductor device of superjunction semiconductor field |
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| CN106024898B (en) * | 2016-07-12 | 2023-04-18 | 杭州士兰集成电路有限公司 | Groove power device and manufacturing method |
| CN116646252A (en) * | 2023-07-27 | 2023-08-25 | 北京智芯微电子科技有限公司 | Super junction device manufacturing method, super junction device, chip and circuit |
| CN117080078A (en) * | 2023-10-17 | 2023-11-17 | 深圳基本半导体有限公司 | Method for preparing MOS device based on composite film layer self-alignment process and device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101903998A (en) * | 2007-12-19 | 2010-12-01 | 飞兆半导体公司 | Method for forming trenches with wide upper portion and narrow lower portion |
| CN103367157A (en) * | 2012-04-06 | 2013-10-23 | 北大方正集团有限公司 | Preparation method of super junction MOSFET |
| CN103579003A (en) * | 2012-08-09 | 2014-02-12 | 北大方正集团有限公司 | Method for manufacturing super joint MOSFET |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101903998A (en) * | 2007-12-19 | 2010-12-01 | 飞兆半导体公司 | Method for forming trenches with wide upper portion and narrow lower portion |
| CN103367157A (en) * | 2012-04-06 | 2013-10-23 | 北大方正集团有限公司 | Preparation method of super junction MOSFET |
| CN103579003A (en) * | 2012-08-09 | 2014-02-12 | 北大方正集团有限公司 | Method for manufacturing super joint MOSFET |
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