CN116646252A - Super junction device manufacturing method, super junction device, chip and circuit - Google Patents
Super junction device manufacturing method, super junction device, chip and circuit Download PDFInfo
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- CN116646252A CN116646252A CN202310928114.1A CN202310928114A CN116646252A CN 116646252 A CN116646252 A CN 116646252A CN 202310928114 A CN202310928114 A CN 202310928114A CN 116646252 A CN116646252 A CN 116646252A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 81
- 210000000746 body region Anatomy 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 26
- 239000000463 material Substances 0.000 claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 48
- 238000001259 photo etching Methods 0.000 claims description 16
- 239000000945 filler Substances 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000012212 insulator Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The application provides a manufacturing method of a super junction device, the super junction device, a chip and a circuit, and relates to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate with an epitaxial layer, wherein the substrate and the epitaxial layer are of a first conductivity type, and the substrate is heavily doped; forming a deep trench fill region within the epitaxial layer using a deep trench mask, the deep trench fill region having a second conductivity type different from the first conductivity type; the deep trench filling region and the epitaxial layers on two sides form a super junction structure; forming a body region etching groove at the top of the deep groove; filling a filling material with a second conductivity type in the body region etching groove to form a body region; and forming gate oxide and a planar gate structure on the surfaces of the epitaxial layers at two sides of the body region to form the super junction device. By the method provided by the application, the body region with uniform concentration and accurate range is formed, and the channel length and the threshold voltage of the super junction device are accurately controlled.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a manufacturing method of a super junction device, the super junction device, a chip and a circuit.
Background
The power semiconductor device is widely applied to power supplies or adapters of consumer electronic products such as mobile phones, computers, illumination, liquid crystal televisions and the like. The conventional power semiconductor device has contradiction between breakdown voltage and on-resistance, that is, the on-resistance of the power semiconductor device has a limit due to the limitation of the breakdown voltage, and in order to break the limitation, a super junction device has appeared.
The super junction is composed of P-type semiconductor thin layers (P pillars) and N-type semiconductor thin layers (N pillars) which are alternately arranged. According to the structure, charge compensation can be realized by exhausting the P column and the N column under the lower voltage in the cut-off state, so that the P column and the N column can realize high breakdown voltage under the higher doping concentration, and meanwhile, low on-resistance can be obtained, and the theoretical limit of a traditional power device is broken through.
In the prior art, after forming P pillars and N pillars alternately arranged, a dedicated "body mask" is required to define a region to be doped in a body region on the surface of each P pillar or N pillar by using a photolithography process, and then doping the defined body region. After the doping of the body region is completed, a thermal annealing process is required to diffuse the doped region of the body region to two sides and below to form a final body region. The doping process can form concentration gradient on the surface of the substrate, and the thermal annealing can enable the concentration of the finally generated body region to be more uneven and the diffusion range to be not accurately controlled, so that the channel length and the threshold voltage of the super junction device can not be accurately controlled.
Disclosure of Invention
Aiming at the technical problem that the channel length and the threshold voltage of the super junction device cannot be accurately controlled due to the body region manufactured by the doping and thermal annealing process in the prior art, the application provides a manufacturing method of the super junction device, a chip and a circuit.
To achieve the above object, a first aspect of the present application provides a method for manufacturing a super junction device, the method comprising: providing a substrate with an epitaxial layer, wherein the substrate and the epitaxial layer are of a first conductivity type, and the substrate is heavily doped; forming a deep trench fill region within the epitaxial layer using a deep trench mask, the deep trench fill region having a second conductivity type different from the first conductivity type; the deep trench filling region and the epitaxial layers on two sides form a super junction structure; forming a body region etching groove at the top of the deep groove; filling a filling material with a second conductivity type in the body region etching groove to form a body region; and forming gate oxide and a planar gate structure on the surfaces of the epitaxial layers at two sides of the body region to form the super junction device.
Further, the forming a deep trench filling region in the epitaxial layer by using the deep trench photomask comprises: sequentially forming a first hard mask layer and a first photoresist layer on the surface of the epitaxial layer; photoetching the first photoresist layer by using a deep trench photomask, and forming a first etching window on the first photoresist layer; etching the first hard mask layer and the epitaxial layer through the first etching window to form a super junction etching groove in the epitaxial layer; and filling a filling material of a second conductivity type in the super junction etched groove to form the deep groove filling region.
Further, the filling material of the second conductivity type in the super junction etched trench is filled, so as to form the deep trench filling region, which comprises: and growing a filling material with a second conductivity type in the super junction etching groove by using an epitaxial process to form the deep groove filling region.
Further, after growing a fill material having a second conductivity type within the super junction etched trench using an epitaxial process, the method further comprises: and removing the first hard mask layer.
Further, the forming a body region etching groove at the top of the deep groove comprises the following steps: and forming the body region etching groove at the top of the deep groove by utilizing the deep groove photomask.
Further, the forming the body etching trench on the top of the deep trench by using the deep trench mask includes: sequentially forming a second hard mask layer and a second photoresist layer on the surface of the epitaxial layer; photoetching the second photoresist layer by utilizing the deep trench photomask, and forming a second etching window on the second photoresist layer; and etching the second hard mask layer and the epitaxial layer by using the second etching window, and forming the body etching groove at the top of the deep groove.
Further, the exposure energy of the deep trench photomask for photoetching the second photoresist layer is larger than that of the deep trench photomask for photoetching the first photoresist layer.
A second aspect of the application provides a superjunction device manufactured by the method of manufacturing a superjunction device as described above.
A third aspect of the application provides a chip comprising a superjunction device as described above.
A fourth aspect of the application provides a circuit comprising a superjunction device as described above.
Through the technical scheme provided by the application, the application has at least the following technical effects:
the method for manufacturing the super junction device comprises the steps of firstly providing a substrate with an epitaxial layer, forming a deep trench filling region in the epitaxial layer by using a deep trench photomask, and forming a super junction structure by the deep trench filling region and the epitaxial layers on two sides; then forming a body region etching groove at the top of the deep groove, and filling a filling material with a second conductivity type in the body region etching groove to form a body region; and then forming gate oxide and a planar gate structure on the surfaces of the epitaxial layers at two sides of the body region to form the super junction device. By the method for manufacturing the super junction device, the body region with uniform concentration and accurate range can be formed, and the channel length and the threshold voltage of the super junction device can be accurately controlled.
Additional features and advantages of the application will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain, without limitation, the embodiments of the application. In the drawings:
FIG. 1 is a flow chart of a method of fabricating a superjunction device according to an embodiment of the present application;
FIG. 2 is a cross-sectional view of a first photoresist layer and a first hard mask layer formed in a method of fabricating a super junction device according to an embodiment of the present application;
fig. 3 is a cross-sectional view of a deep trench fill region formed in a method of fabricating a superjunction device according to an embodiment of the present application;
FIG. 4 is a cross-sectional view of a second photoresist layer and a second hard mask layer formed in a method of fabricating a super junction device according to an embodiment of the present application;
fig. 5 is a cross-sectional view of a body region formed in a method of fabricating a superjunction device according to an embodiment of the present application;
fig. 6 is a cross-sectional view of a superjunction device formed in a method of fabricating a superjunction device according to an embodiment of the present application.
Detailed Description
The following describes the detailed implementation of the embodiments of the present application with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the application, are not intended to limit the application.
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other.
In the present application, unless otherwise indicated, terms of orientation such as "upper, lower, top, bottom" are used generally with respect to the orientation shown in the drawings or with respect to the positional relationship of the various components with respect to one another in the vertical, vertical or gravitational directions.
The application will be described in detail below with reference to the drawings in connection with embodiments.
Referring to fig. 1-6, an embodiment of the present application provides a method for manufacturing a super junction device, the method including the following steps: s101: providing a substrate with an epitaxial layer, wherein the substrate and the epitaxial layer are of a first conductivity type, and the substrate is heavily doped; s102: forming a deep trench fill region within the epitaxial layer using a deep trench mask, the deep trench fill region having a second conductivity type different from the first conductivity type; the deep trench filling region and the epitaxial layers on two sides form a super junction structure; s103: forming a body region etching groove at the top of the deep groove; s104: filling a filling material with a second conductivity type in the body region etching groove to form a body region; s105: and forming gate oxide and a planar gate structure on the surfaces of the epitaxial layers at two sides of the body region to form the super junction device.
Step S101 is first performed: a substrate is provided having an epitaxial layer, the substrate and the epitaxial layer having a first conductivity type, and the substrate being heavily doped.
Specifically, in the embodiment of the present application, the first doping type is P-type, the second doping type is N-type, or the first doping type is N-type and the second doping type is P-type, which is not limited in this regard, and the following embodiments only take the first doping type is N-type and the second doping type is P-type as examples.
Referring to fig. 2, a substrate is provided, wherein the substrate is one of a silicon substrate, a silicon germanium substrate, a silicon-on-insulator substrate, and a germanium-on-insulator substrate. In this embodiment, the substrate is an N-type heavily doped silicon substrate. Those skilled in the art may select the type of substrate according to the performance of the semiconductor device to be formed, and thus the type of substrate should not unduly limit the scope of the present application. An N-type epitaxial layer is then grown on the upper surface of the substrate.
Step S102 is then performed: forming a deep trench fill region within the epitaxial layer using a deep trench mask, the deep trench fill region having a second conductivity type different from the first conductivity type; and the deep trench filling region and the epitaxial layers at two sides form a super junction structure.
Further, the forming a deep trench filling region in the epitaxial layer by using the deep trench photomask comprises: sequentially forming a first hard mask layer and a first photoresist layer on the surface of the epitaxial layer; photoetching the first photoresist layer by using a deep trench photomask, and forming a first etching window on the first photoresist layer; etching the first hard mask layer and the epitaxial layer through the first etching window to form a super junction etching groove in the epitaxial layer; and filling a filling material of a second conductivity type in the super junction etched groove to form the deep groove filling region.
Further, the filling material of the second conductivity type in the super junction etched trench is filled, so as to form the deep trench filling region, which comprises: and growing a filling material with a second conductivity type in the super junction etching groove by using an epitaxial process to form the deep groove filling region.
Further, after growing a fill material having a second conductivity type within the super junction etched trench using an epitaxial process, the method further comprises: and removing the first hard mask layer.
Specifically, in the embodiment of the application, a first hard mask layer and a first photoresist layer are sequentially formed on the surface of an epitaxial layer, exposure and lithography are performed on the first photoresist layer by using a deep trench photomask, a first etching window shown in fig. 2 is formed on the first photoresist layer, then the first hard mask layer and the epitaxial layer are etched through the first etching window, a trench is formed in the epitaxial layer, and a super junction etching trench is formed when the trench reaches a set depth. And then, using an epitaxial process to grow a filling material with a second conductivity type in the super junction etching groove to form a deep groove filling region shown in fig. 3, forming a super junction structure by the deep groove filling region and epitaxial layers on two sides, and removing the first hard mask layer on the surface of the epitaxial layer.
In one possible implementation, a layer of silicon oxide is deposited on the surface of the N-type epitaxial layer to form a first hard mask layer, and then a layer of photoresist is coated on the surface of the first hard mask layer to form a first photoresist layer. And performing exposure and lithography on the first photoresist layer by using the deep trench photomask, and defining an etching region of the deep trench filling region on the first photoresist layer to form an etching window. And then sequentially carrying out ion etching on the first hard mask layer and the epitaxial layer through the etching window until the groove of the epitaxial layer reaches the design depth, so as to form a super junction etching groove. And then, the P-type silicon is epitaxially grown in the super junction etching groove, the super junction etching groove is filled, a P-type deep groove filling area is formed, and the P-type deep groove filling area and N-type epitaxy at two sides form a super junction structure. And then removing the first hard mask layer on the surface of the N-type epitaxial layer.
Step S103 is then performed: and forming a body region etching groove at the top of the deep groove.
Further, the forming a body region etching groove at the top of the deep groove comprises the following steps: and forming the body region etching groove at the top of the deep groove by utilizing the deep groove photomask.
Further, the forming the body etching trench on the top of the deep trench by using the deep trench mask includes: sequentially forming a second hard mask layer and a second photoresist layer on the surface of the epitaxial layer; photoetching the second photoresist layer by utilizing the deep trench photomask, and forming a second etching window on the second photoresist layer; and etching the second hard mask layer and the epitaxial layer by using the second etching window, and forming the body etching groove at the top of the deep groove.
Further, the exposure energy of the deep trench photomask for photoetching the second photoresist layer is larger than that of the deep trench photomask for photoetching the first photoresist layer.
Specifically, in the embodiment of the application, the pattern corresponding to the configuration of the etched groove is formed on the photomask, and for the etched grooves with different configurations, the corresponding etched areas can be etched only by the special photomask, and the photomask is high in price, so that the photoetching manufacturing cost is high. The configuration of the deep trench filling region and the configuration of the body region are similar, and the cross section size of the body region is larger than the size of the deep trench filling region, so that after the deep trench filling region is formed by using the deep trench photomask, the deep trench photomask is continuously utilized to replace the special body region photomask, and then the body region etching trench is formed by etching the deep trench photomask in cooperation with corresponding exposure energy, so that the cost of the special body region etching photomask is saved, and the manufacturing cost is reduced.
Depositing a second hard mask layer on the surface of the epitaxial layer, coating a photoresist layer on the surface of the second hard mask layer to form a second photoresist layer, placing a deep trench photomask above the second photoresist layer, photoetching the second photoresist layer by using exposure energy larger than photoetching during deep trench etching, and defining an etching area of a body region in the second photoresist layer to form a second etching window shown in fig. 4, wherein the photoetching exposure energy of the second photoresist layer is determined by the opening size of the body region required by the threshold voltage of the super junction device. And then etching the second hard mask layer and the epitaxial layer through the etching window respectively, and forming a body etching groove at the top of the deep groove.
In one possible implementation manner, when the exposure energy is determined, the design size of the body region is determined, then a deep trench photomask is arranged on the surface of the epitaxial sample coated with the photoresist layer, a plurality of etching windows are formed by photoetching the photoresist layer by adopting different exposure energies, the etching windows with the same size as the design size of the body region are selected from the plurality of etching windows, and the exposure energy corresponding to the etching windows is determined as the exposure energy required for etching the second etching windows.
In another possible implementation manner, when the exposure energy is determined, a photoresist layer is formed on the surface of the epitaxial sample, a deep trench photomask is arranged above the photoresist layer, the photoresist layer is subjected to photoetching by adopting different exposure energies, corresponding etching windows are formed, and the sizes of the corresponding etching windows are determined. And establishing an exposure energy model according to different exposure energies and the sizes of the corresponding etching windows. After the body size is determined, the body size is input into an exposure energy model to determine the exposure energy corresponding to the etched body.
In one possible implementation, a layer of silicon oxide is deposited on the surface of the N-type epitaxial layer to form a second hard mask layer, and then a layer of photoresist is coated on the surface of the second hard mask layer to form a second photoresist layer. And performing exposure and lithography on the second photoresist layer by using the deep trench photomask, and defining an etching region of the body region on the second photoresist layer to form an etching window. And then sequentially carrying out ion etching on the second hard mask layer and the epitaxial layer through the etching window until the groove of the epitaxial layer reaches the design depth, and forming a body region etching groove at the top of the deep groove filling region.
According to the manufacturing method of the super junction device, the deep trench photomask can be used for replacing a special body region photomask, and the body region trench is formed by etching in combination with exposure energy, so that the expenditure of the special body region photomask is reduced, and the manufacturing cost is saved.
Step S104 is then performed: and filling a filling material with a second conductivity type in the body region etching groove to form a body region.
Specifically, in the embodiment of the present application, after the body region etching trench is formed, a filling material having the second conductivity type is filled in the body region etching trench to form the body region shown in fig. 5. In one possible implementation, the P-type epitaxial silicon is grown in the body etched trench by an epitaxial process, and the body etched trench is filled to form a P-type body region. And then removing the second hard mask layer on the surface of the N-type epitaxial layer.
Finally, step S105 is executed: and forming gate oxide and a planar gate structure on the surfaces of the epitaxial layers at two sides of the body region to form the super junction device.
Specifically, in the embodiment of the application, after the body region is formed, gate oxide and a planar gate structure are formed on the surface of the epitaxial layer at two sides of the body region, so that the final super junction device is formed.
By the method for manufacturing the super junction device, the body region with uniform concentration and accurate range can be formed, and the channel length and the threshold voltage of the super junction device can be accurately controlled.
Referring to fig. 6, a second aspect of the present application provides a superjunction device fabricated by the method of fabricating a superjunction device as described above.
A third aspect of the application provides a chip comprising a superjunction device as described above.
A fourth aspect of the application provides a circuit comprising a superjunction device as described above.
The preferred embodiments of the present application have been described in detail above with reference to the accompanying drawings, but the present application is not limited to the specific details of the above embodiments, and various simple modifications can be made to the technical solution of the present application within the scope of the technical concept of the present application, and all the simple modifications belong to the protection scope of the present application.
In addition, the specific features described in the above embodiments may be combined in any suitable manner, and in order to avoid unnecessary repetition, various possible combinations are not described further.
Moreover, any combination of the various embodiments of the application can be made without departing from the spirit of the application, which should also be considered as disclosed herein.
Claims (10)
1. A method of fabricating a superjunction device, the method comprising:
providing a substrate with an epitaxial layer, wherein the substrate and the epitaxial layer are of a first conductivity type, and the substrate is heavily doped;
forming a deep trench fill region within the epitaxial layer using a deep trench mask, the deep trench fill region having a second conductivity type different from the first conductivity type; the deep trench filling region and the epitaxial layers on two sides form a super junction structure;
forming a body region etching groove at the top of the deep groove;
filling a filling material with a second conductivity type in the body region etching groove to form a body region;
and forming gate oxide and a planar gate structure on the surfaces of the epitaxial layers at two sides of the body region to form the super junction device.
2. The method of fabricating a super junction device according to claim 1, wherein forming a deep trench fill region in the epitaxial layer using a deep trench mask comprises:
sequentially forming a first hard mask layer and a first photoresist layer on the surface of the epitaxial layer;
photoetching the first photoresist layer by using a deep trench photomask, and forming a first etching window on the first photoresist layer;
etching the first hard mask layer and the epitaxial layer through the first etching window to form a super junction etching groove in the epitaxial layer;
and filling a filling material of a second conductivity type in the super junction etched groove to form the deep groove filling region.
3. The method of manufacturing a super junction device according to claim 2, wherein said filling a filling material of a second conductivity type in said super junction etched trench to form said deep trench filling region comprises:
and growing a filling material with a second conductivity type in the super junction etching groove by using an epitaxial process to form the deep groove filling region.
4. The method of manufacturing a super junction device according to claim 3, wherein after growing a filler material of a second conductivity type in the super junction etched trench using an epitaxial process, forming the deep trench fill region, the method further comprises:
and removing the first hard mask layer.
5. The method of fabricating a super junction device according to claim 2, wherein forming a body etch trench on top of the deep trench comprises:
and forming the body region etching groove at the top of the deep groove by utilizing the deep groove photomask.
6. The method of claim 5, wherein forming the body etch trench in the top of the deep trench using the deep trench mask comprises:
sequentially forming a second hard mask layer and a second photoresist layer on the surface of the epitaxial layer;
photoetching the second photoresist layer by utilizing the deep trench photomask, and forming a second etching window on the second photoresist layer;
and etching the second hard mask layer and the epitaxial layer by using the second etching window, and forming the body etching groove at the top of the deep groove.
7. The method of claim 6, wherein the exposure energy of the deep trench mask to photo-etch the second photoresist layer is greater than the exposure energy of the deep trench mask to photo-etch the first photoresist layer.
8. A superjunction device, characterized in that it is manufactured by the method of manufacturing a superjunction device according to any of claims 1 to 7.
9. A chip comprising the superjunction device of claim 8.
10. A circuit comprising the superjunction device of claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310928114.1A CN116646252A (en) | 2023-07-27 | 2023-07-27 | Super junction device manufacturing method, super junction device, chip and circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310928114.1A CN116646252A (en) | 2023-07-27 | 2023-07-27 | Super junction device manufacturing method, super junction device, chip and circuit |
Publications (1)
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