CN114823532A - Super junction device manufacturing method, super junction device, chip and circuit - Google Patents
Super junction device manufacturing method, super junction device, chip and circuit Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 69
- 238000000034 method Methods 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 210000000746 body region Anatomy 0.000 claims abstract description 26
- 238000005468 ion implantation Methods 0.000 claims abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 17
- 239000012535 impurity Substances 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 abstract description 10
- 230000015556 catabolic process Effects 0.000 description 4
- -1 boron ion Chemical class 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000779 depleting effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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Abstract
The invention provides a manufacturing method of a super junction device, the super junction device, a chip and a circuit, belonging to the technical field of semiconductors, wherein the manufacturing method comprises the following steps: providing a substrate with an epitaxial layer; defining an etching area on the upper surface of the epitaxial layer; forming an etching groove with a first depth in the epitaxial layer by using an etching process according to the etching region; performing ion implantation on the bottom of the etched groove to form a doped region, wherein the doped region has a second conductivity type, and the sum of the second depth and the first depth of the doped region is equal to the target depth; carrying out epitaxial filling on the etched groove to form a filling region, wherein a longitudinal doped region formed by the filling region and the doped region and an adjacent epitaxial layer region form a super junction; and forming a gate and a body region, wherein the body region is positioned on the top of the longitudinal doped region, and the gate is positioned on the upper surface of the epitaxial layer and covers part of the body region. By the method provided by the invention, the uniformity of the etching depth of the groove is improved, the depth-to-width ratio of the groove is reduced, and the epitaxial filling cavity is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a super junction device, the super junction device, a chip and a circuit.
Background
The power semiconductor device is widely applied to power supplies or adapters of consumer electronic products such as mobile phones, computers, lighting, liquid crystal televisions and the like. The conventional power semiconductor device has the contradiction between the breakdown voltage and the on-resistance, namely the on-resistance of the power semiconductor device has a limit due to the limitation of the breakdown voltage, and in order to break the limitation, the super junction device appears.
The super junction is composed of P-type semiconductor thin layers (P columns for short) and N-type semiconductor thin layers (N columns for short) which are alternately arranged. The structure can realize charge compensation by depleting the P column and the N column at a lower voltage in a cut-off state, so that the P column and the N column can realize high breakdown voltage at a higher doping concentration, and can obtain low on-resistance at the same time, thereby breaking through the theoretical limit of the traditional power device.
In the prior art, the mainstream process of a super junction device is a deep trench single epitaxial filling technology, and the technology adopts a process of performing single deep trench etching on an N-type epitaxial layer and filling a P-type epitaxial layer once to obtain alternately arranged P columns and N columns. However, the difficulty of the trench etching process with a high aspect ratio is high, the uniformity of the trench etching depth at different positions on the same wafer is not easy to control, and voids are easily formed during epitaxial filling, which affects the breakdown voltage of devices.
Disclosure of Invention
Aiming at the technical problems that the uniformity of the etching depth of a groove is not easy to control and a cavity is easy to form during epitaxial filling in the prior art, the invention provides a manufacturing method of a super junction device, the super junction device, a chip and a circuit.
In order to achieve the above object, a first aspect of the present invention provides a method for manufacturing a super junction device, the method comprising the steps of: providing a substrate with an epitaxial layer, wherein the substrate and the epitaxial layer have a first conductivity type, and the substrate is heavily doped; defining an etching area on the upper surface of the epitaxial layer; forming an etching groove with a first depth in the epitaxial layer by using an etching process according to the etching area; performing ion implantation on the bottom of the etched groove, and forming a doped region in at least part of the epitaxial layer at the bottom of the etched groove, wherein the doped region has a second conductivity type, and the sum of the second depth and the first depth of the doped region is equal to a target depth; carrying out epitaxial filling on the etched groove to form a filling region, wherein the filling region has a second conductivity type, and a longitudinal doped region formed by the filling region and the doped region and an adjacent epitaxial layer region form the super junction; and forming a gate and a body region, wherein the body region is positioned at the top of the longitudinal doped region, and the gate is positioned on the upper surface of the epitaxial layer and covers part of the body region.
Further, the ratio of the first depth to the target depth is between 1/2 and 2/3.
Further, the angle of the ion implantation is perpendicular to the upper surface of the epitaxial layer.
Further, the width of the doped region is the same as the width of the filling region.
Further, the impurity concentration of the doped region is the same as that of the filling region, and the impurity concentration enables the doped region and the filling region to realize charge balance with the adjacent epitaxial layer region.
Further, the defining an etching area on the upper surface of the epitaxial layer includes: forming a silicon oxide layer on the upper surface of the epitaxial layer; forming a photoresist layer on the surface of the silicon oxide layer and defining an etching window; and etching the silicon oxide layer through the etching window to define the etching area.
Further, forming an etching trench in the epitaxial layer by using an etching process according to the etching region includes: and forming an etching groove in the epitaxial layer by a dry etching process according to the etching area.
A second aspect of the present invention provides a super junction device, comprising: the semiconductor device comprises a substrate, an epitaxial layer, a grid, a body region and a super junction on the epitaxial layer, wherein the super junction is manufactured by the manufacturing method of the super junction, the body region is positioned at the top of the longitudinal doped region, and the grid is positioned on the upper surface of the epitaxial layer and covers part of the body region.
A third aspect of the invention provides a chip comprising a superjunction device as described above.
A fourth aspect of the invention provides a circuit comprising a superjunction device as described above.
Through the technical scheme provided by the invention, the invention at least has the following technical effects:
the manufacturing method of the super junction device comprises the steps of firstly providing a substrate with an epitaxial side, defining an etching area on the upper surface of the epitaxial layer, forming an etching groove with a first depth in the epitaxial layer by utilizing an etching process, wherein the first depth of the etching groove is smaller than the target depth of a super junction, then forming a doping area in at least part of the epitaxial layer at the bottom of the etching groove by carrying out ion implantation on the bottom of the etching groove, wherein the sum of the second depth and the first depth of the doping area is equal to the target depth of the super junction, then carrying out epitaxial filling in the etching groove to form a filling area, wherein the filling area and the doping area have a second conductivity type, a longitudinal doping area formed by the filling area and the doping area and an adjacent epitaxial layer area form the super junction, and finally forming a grid electrode and a body area to obtain the final super junction device. The method provided by the invention can reduce the etching difficulty of the groove, reduce the etching depth of the groove, improve the uniformity of the etching depth of the groove, reduce the depth-to-width ratio of the groove and improve the epitaxial filling cavity.
Additional features and advantages of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
FIG. 1 is a flow chart of a method for fabricating a super junction device according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view of a photoresist layer formed in a method for fabricating a super junction device according to an embodiment of the present invention;
FIG. 3 is a cross-sectional view of a hard mask layer formed in a method for fabricating a super junction device according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view of an etched trench formed in a method of fabricating a super junction device according to an embodiment of the present invention;
FIG. 5 is a cross-sectional view of a doped region formed in a method of fabricating a super junction device according to an embodiment of the present invention;
FIG. 6 is a cross-sectional view of a super junction formed in a method of fabricating a super junction device according to an embodiment of the present invention;
fig. 7 is a cross-sectional view of a super junction device formed in a method of fabricating a super junction device according to an embodiment of the present invention.
Description of the reference numerals
1-a substrate; 2-an epitaxial layer; 3-a silicon oxide layer; 4-a photoresist layer; 5, etching a groove; 6-doped region; 7-longitudinal doped region; an 8-body region; 9-grid electrode.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
In the present invention, unless specified to the contrary, use of the terms of orientation such as "upper, lower, top, bottom" or the like are generally described with respect to the orientation shown in the drawings or the positional relationship of the components with respect to each other in the vertical, or gravitational direction.
The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
Referring to fig. 1 to 7, a method for manufacturing a super junction device according to an embodiment of the present invention includes the following steps: s101: providing a substrate with an epitaxial layer, wherein the substrate and the epitaxial layer have a first conductivity type, and the substrate is heavily doped; s102: defining an etching area on the upper surface of the epitaxial layer; s103: forming an etching groove with a first depth in the epitaxial layer by using an etching process according to the etching area; s104: performing ion implantation on the bottom of the etched groove, and forming a doped region in at least part of the epitaxial layer at the bottom of the etched groove, wherein the doped region has a second conductivity type, and the sum of the second depth and the first depth of the doped region is equal to the target depth; s105: carrying out epitaxial filling on the etched groove to form a filling region, wherein the filling region has a second conductivity type, and a longitudinal doped region formed by the filling region and the doped region and an adjacent epitaxial layer region form the super junction; s106: and forming a gate and a body region, wherein the body region is positioned at the top of the longitudinal doped region, and the gate is positioned on the upper surface of the epitaxial layer and covers part of the body region.
Step S101 is first executed: a substrate having an epitaxial layer is provided, the substrate and the epitaxial layer having a first conductivity type, and the substrate being heavily doped.
Specifically, in the embodiment of the present invention, a substrate 1 is provided, where the substrate 1 is one of a silicon substrate, a silicon germanium substrate, a silicon-on-insulator substrate, and a germanium-on-insulator substrate. In the present embodiment, the substrate 1 is an N-type heavily doped silicon substrate. The type of substrate 1 may be selected by those skilled in the art depending on the properties of the semiconductor device to be formed and therefore should not unduly limit the scope of the present invention. An N-type epitaxial layer 2 is then grown on the upper surface of the substrate 1.
Then, step S102 is executed: an etch region is defined on an upper surface of the epitaxial layer.
Further, the defining an etching area on the upper surface of the epitaxial layer includes: forming a silicon oxide layer on the upper surface of the epitaxial layer; forming a photoresist layer on the surface of the silicon oxide layer and defining an etching window; and etching the silicon oxide layer through the etching window to define the etching area.
Referring to fig. 2 and 3, in the embodiment of the invention, a silicon oxide layer 3 is formed on the upper surface of the epitaxial layer 2, a photoresist layer 4 is formed on the upper surface of the silicon oxide layer 3, an etching window is defined on the photoresist layer 4 by an etching process, the silicon oxide layer 3 is dry-etched by using the photoresist layer 4 as a mask, the photoresist layer 4 is removed after etching until the surface of the epitaxial layer 2 is exposed, and the etched silicon oxide layer 3 is used as a hard mask layer.
Step S103 is then executed: and forming an etching groove with a first depth in the epitaxial layer by using an etching process according to the etching area.
Further, forming an etching trench in the epitaxial layer by using an etching process according to the etching region includes: and forming an etching groove in the epitaxial layer by a dry etching process according to the etching area.
Further, the ratio of the first depth to the target depth is between 1/2 and 2/3.
Referring to fig. 4, in the embodiment of the invention, the etched silicon oxide layer 3 is used as a hard mask to perform dry etching on the epitaxial layer 2 to form the etched trench 5, and the first depth of the etched trench 5 is 1/2 to 2/3 of the target depth.
The method provided by the invention can reduce the etching depth of the groove, reduce the etching difficulty of the groove, ensure the balance of the etching depth of the groove at different positions on the same wafer, reduce the depth-to-width ratio of the groove and reduce the difficulty of subsequent epitaxial filling.
Then, step S104 is executed: and performing ion implantation on the bottom of the etched groove, and forming a doped region in at least part of the epitaxial layer at the bottom of the etched groove, wherein the doped region has a second conductivity type, and the sum of the second depth and the first depth of the doped region is equal to the target depth.
Further, the angle of the ion implantation is perpendicular to the upper surface of the epitaxial layer.
Referring to fig. 5, in the embodiment of the invention, the silicon oxide layer 3 is used as a hard mask to perform P-type ion implantation on the bottom of the etched trench 5, the P-type ion implantation is boron ion, and the ion implantation dose is between 1E15cm -2 ~1E16cm -2 The ion implantation energy is between 100keV and 200keV, the implantation angle is perpendicular to the upper surface of the epitaxial layer 2, and the doped region 6 extends downwards along the wall of the etched trench 5 to form the doped region 6, specifically, the second depth of the doped region 6 can be determined according to the difference between the target depth of the super junction and the first depth of the etched trench, and the doped region 6 reaches the corresponding second depth by adjusting the implantation energy. In this embodiment, the depth of the doped region 6 is between 10-15 um. When P-type epitaxy is adopted, N-type ion implantation can be carried out, and the implanted ions are phosphorus ions or arsenic ions.
Then, step S105 is executed: and carrying out epitaxial filling on the etched groove to form a filling region, wherein the filling region has a second conductivity type, and the filling region and a longitudinal doped region formed by the doped region and an adjacent epitaxial layer region form the super junction.
Further, the width of the doped region is the same as the width of the filling region.
Further, the impurity concentration of the doped region is the same as that of the filling region, and the impurity concentration enables the doped region and the filling region to realize charge balance with the adjacent epitaxial layer region.
Referring to fig. 6, in the embodiment of the invention, a filling region is formed by performing P-type filling on an etched trench 5 through epitaxy, the width of the doped region 6 is the same as the width of the filling region, the impurity concentration of the doped region 6 is also the same as the impurity concentration of the filling region, the filling region and the doped region 6 form a columnar longitudinal doped region 7 (i.e., a P column), the columnar longitudinal doped region and an adjacent epitaxial layer region (i.e., an N column) form a super junction structure, and charge balance between the doped region 6 and the filling region and the adjacent epitaxial layer region is realized.
By the method, the whole depth of the longitudinal doped region can be increased through ion implantation, the depth of the etched groove is reduced through increasing the doped region, the depth of the etched groove at different positions on the same wafer is ensured to have better uniformity, the depth-to-width ratio of the groove is reduced, the etching difficulty of the deep groove is reduced, and the epitaxial filling hole is improved.
Finally, step S106 is executed: and forming a gate and a body region, wherein the body region is positioned at the top of the longitudinal doped region, and the gate is positioned on the upper surface of the epitaxial layer and covers part of the body region.
Referring to fig. 7, in the embodiment of the invention, the silicon oxide layer 3 is removed by wet etching to form the gate 9 and the body region 8, the body region 8 is located on top of the vertical doped region 7, and the gate 9 is located on the upper surface of the epitaxial layer 2 and covers a portion of the body region 8, including the gate oxide and the gate structure.
A second aspect of the present invention provides a super junction device, comprising: the semiconductor device comprises a substrate, an epitaxial layer, a grid, a body region and a super junction on the epitaxial layer, wherein the super junction is manufactured by the manufacturing method of the super junction, the body region is positioned at the top of the longitudinal doped region, and the grid is positioned on the upper surface of the epitaxial layer and covers part of the body region.
A third aspect of the invention provides a chip comprising a superjunction device as described above.
A fourth aspect of the invention provides a circuit comprising a superjunction device as described above.
The preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, however, the present invention is not limited to the specific details of the above embodiments, and various simple modifications can be made to the technical solution of the present invention within the technical idea of the present invention, and these simple modifications are within the protective scope of the present invention.
It should be noted that, in the above embodiments, the various features described in the above embodiments may be combined in any suitable manner, and in order to avoid unnecessary repetition, the present invention does not separately describe various possible combinations.
In addition, any combination of the various embodiments of the present invention is also possible, and the same should be considered as the disclosure of the present invention as long as it does not depart from the spirit of the present invention.
Claims (10)
1. A manufacturing method of a super junction device is characterized by comprising the following steps:
providing a substrate with an epitaxial layer, wherein the substrate and the epitaxial layer have a first conductivity type, and the substrate is heavily doped;
defining an etching area on the upper surface of the epitaxial layer;
forming an etching groove with a first depth in the epitaxial layer by using an etching process according to the etching area;
performing ion implantation on the bottom of the etched groove, and forming a doped region in at least part of the epitaxial layer at the bottom of the etched groove, wherein the doped region has a second conductivity type, and the sum of the second depth and the first depth of the doped region is equal to a target depth;
carrying out epitaxial filling on the etched groove to form a filling region, wherein the filling region has a second conductivity type, and a longitudinal doped region formed by the filling region and the doped region and an adjacent epitaxial layer region form the super junction;
and forming a gate and a body region, wherein the body region is positioned at the top of the longitudinal doped region, and the gate is positioned on the upper surface of the epitaxial layer and covers part of the body region.
2. The method of claim 1, wherein a ratio of the first depth to the target depth is 1/2-2/3.
3. The method of claim 1, wherein the angle of the ion implantation is perpendicular to the upper surface of the epitaxial layer.
4. The method of claim 1, wherein the width of the doped region is the same as the width of the fill region.
5. The method of claim 1, wherein the impurity concentration of the doped region is the same as the impurity concentration of the fill region, and the impurity concentration is such that the doped region and the fill region are both charge balanced with adjacent epitaxial layer regions.
6. The method of claim 1, wherein the defining an etch region on the top surface of the epitaxial layer comprises:
forming a silicon oxide layer on the upper surface of the epitaxial layer;
forming a photoresist layer on the surface of the silicon oxide layer and defining an etching window;
and etching the silicon oxide layer through the etching window to define the etching area.
7. The method of manufacturing a super junction device according to claim 1, wherein the forming of the etched trench in the epitaxial layer by an etching process according to the etched region comprises:
and forming an etching groove in the epitaxial layer by a dry etching process according to the etching area.
8. A super junction device, comprising: the super junction is manufactured by the manufacturing method of the super junction in claim 1, the body region is located on the top of the longitudinal doped region, and the gate is located on the upper surface of the epitaxial layer and covers a part of the body region.
9. A chip comprising the superjunction device of claim 8.
10. A circuit comprising the superjunction device of claim 8.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116646252A (en) * | 2023-07-27 | 2023-08-25 | 北京智芯微电子科技有限公司 | Super junction device manufacturing method, super junction device, chip and circuit |
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