CN105448722A - Method for manufacturing super-junction semiconductor field effect transistor, and semiconductor device - Google Patents
Method for manufacturing super-junction semiconductor field effect transistor, and semiconductor device Download PDFInfo
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- CN105448722A CN105448722A CN201410383910.2A CN201410383910A CN105448722A CN 105448722 A CN105448722 A CN 105448722A CN 201410383910 A CN201410383910 A CN 201410383910A CN 105448722 A CN105448722 A CN 105448722A
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Abstract
The invention discloses a method for manufacturing a super-junction semiconductor field effect transistor, and a semiconductor device. The method can optimize a manufacturing flow, simplify a manufacturing process, and reduce the manufacturing cost. The method for manufacturing the super-junction semiconductor field effect transistor includes the following steps of: successively manufacturing a first conductive epitaxial layer and a first protection layer on a semiconductor substrate; etching the first conductive epitaxial layer without protection of the first protection layer to form a first trench; manufacturing a second protection layer on the semiconductor substrate where the first trench forms; etching the second protection layer to form a second protection side wall on a side wall of the first trench; etching the first conductive epitaxial layer without protection of the first protection layer and the second protection layer side wall to form a second trench; manufacturing a second conductive epitaxial layer in the second trench; and removing the second protection side wall, and manufacturing the second conductive epitaxial layer in the first trench, wherein the depth of the first trench is less than that of the second trench, and a material of the first protection layer is different from that of the second protection layer.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of manufacture method and semiconductor device of superjunction semiconductor field.
Background technology
The semiconductor device of super-junction structure, become the important trend of device development, prior art is at super-junction metal oxide semiconductor field effect pipe (MetalOxideSemiconductorFieldEffectTransistor, MOSFET), in the manufacture of i.e. metal-oxide-semiconductor, wherein a kind of way etches deep trench in N-type epitaxy layer, then growing P-type extension in deep trench, then polysilicon gate is made further, in the polysilicon window of etching, carry out the injection in P type tagma and drive in, thus forming P type tagma.
Particularly, as shown in Figure 1, N-type substrate 10 grows N-type epitaxy layer 11, N-type epitaxy layer 11 grows initial oxide layer 12, then the initial oxide layer needing to etch deep trench region place is got rid of, etch deep trench 13, growing P-type epitaxial loayer 20 in deep trench 13, as shown in Figure 2, then unnecessary P type epitaxial loayer grinding and polishing is fallen, as shown in Figure 3, regrowth gate oxide 40 afterwards, as shown in Figure 4, growing polycrystalline silicon grid layer 41 on gate oxide 40 again, then etching gets rid of partial polysilicon grid layer, as shown in Figure 5, carry out the injection of P type ion again and drive in, because the thickness of polycrystalline silicon gate layer is thicker, therefore, the region P type ion having polycrystalline silicon gate layer to cover can not be injected in the N-type epitaxy layer 11 below it, the region P type ion covered without polycrystalline silicon gate layer can be injected in the P type epitaxial loayer 20 below it, and then the P type ion injected is carried out to high temperature and drives in process, under high temperature action, the P type ion injected can carry out horizontal proliferation, like this, in P type epitaxial loayer, just define the tagma of superjunction MOS.As shown in Figure 6, the N-type substrate 10 being formed with polycrystalline silicon gate layer applies photoresist, and the photoresist of coating is exposed, developed, finally form the photoresist 60 shown in Fig. 6, and then inject N-type ion, in the region covered without polycrystalline silicon gate layer 41 and photoresist 60, N-type ion can be injected in the P type epitaxial loayer below it, form N+ source area 61, then in the N-type substrate of the formation N+ source area shown in Fig. 6, make the contact hole between dielectric layer 70 and dielectric layer, finally on dielectric layer, form metal level 71, as shown in Figure 7.
In sum, prior art in the process making superjunction MOS, the injection needing to carry out P type ion when forming P type tagma with drive in, complex manufacturing technology, and manufacturing cost is higher.
Summary of the invention
Embodiments provide a kind of manufacture method and semiconductor device of superjunction semiconductor field, in order to optimize Making programme, simplify manufacture craft, reduce cost of manufacture.
The manufacture method of a kind of superjunction semiconductor field that the embodiment of the present invention provides, comprising:
Make the first conduction epitaxial loayer on a semiconductor substrate, the first conduction epitaxial loayer forms the first protective layer by patterning processes;
Etching does not have the first conduction epitaxial loayer of the first protective layer protection, forms the first groove;
The Semiconductor substrate being formed with the first groove makes the second protective layer;
Etch the second protective layer, form the second protective layer side wall at the sidewall of the first groove;
Etching does not have the first conduction epitaxial loayer of the first protective layer and the second protective layer side wall protection, forms the second groove;
The second conduction epitaxial loayer is made in the second groove;
Remove the second protective layer side wall, in the first groove, make the second conduction epitaxial loayer;
Wherein, the degree of depth of described first groove is less than the degree of depth of described second groove; The material of described first protective layer is different with the material of described second protective layer.
The manufacture method of the superjunction semiconductor field provided by the embodiment of the present invention, due to when making groove, first the first groove is produced, make the second groove more afterwards, simultaneously, when making conduction epitaxial loayer, first in the second groove, make the second conduction epitaxial loayer, the second conduction epitaxial loayer is made afterwards in the first groove, by simply growing the second conduction epitaxial loayer, P type tagma is formed in the first groove, eliminate prior art and need the injection carrying out P type ion and the process driven in when forming P type tagma, thus optimization Making programme can be reached, simplify manufacture craft, reduce the object of cost of manufacture.
Preferably, described Semiconductor substrate is N type semiconductor substrate, and described first conduction epitaxial loayer is N-type conduction epitaxial loayer, and described second conduction epitaxial loayer is P-type conduction epitaxial loayer.
Like this, when making superjunction semiconductor field, convenient, simple.
Preferably, the degree of depth of described first groove is 1 micron to 5 microns.
Like this, the degree of depth of the first groove is 1 micron to 5 microns, convenient, simple when follow-up formation P type tagma.
Preferably, the degree of depth of described second groove is 40 microns to 50 microns.
Like this, the degree of depth of the second groove is 40 microns to 50 microns, better can form the PN post alternately connected, form better super-junction structure in semiconductor substrate.
Preferably, the material of described first protective layer is silicon dioxide.
Like this, make the material of the first protective layer with silicon dioxide, convenient in actual production process, simple.
Preferably, the material of described second protective layer is silicon nitride.
Like this, make the material of the second protective layer with silicon nitride, convenient in actual production process, simple.
Preferably, described removal second protective layer side wall, comprising: adopt hot phosphoric acid, erosion removal second protective layer side wall.
Like this, hot phosphoric acid is adopted to remove the second protective layer side wall, convenient in actual production process, simple.
Preferably, described first conduction epitaxial loayer on form the first protective layer by patterning processes, comprising:
First conduction epitaxial loayer deposits the first protective layer;
Described first protective layer applies photoresist, and photoresist is exposed, develops;
Etching removes the first protective layer not having photoresist to protect, and removes residue photoresist, forms the first protective layer.
Like this, form the first protective layer by said method, convenient in actual production process, simple.
Preferably, make the second conduction epitaxial loayer in the first groove after, described method also comprises:
Remove the first protective layer, manufacturing gate oxide layers and grid layer successively on described first conduction epitaxial loayer and the second conduction epitaxial loayer, wherein, described gate oxide covers the first conduction epitaxial loayer and the second conduction epitaxial loayer, and described grid layer covers the first conduction epitaxial loayer and part second and conducts electricity epitaxial loayer;
In the subregion do not covered by grid layer, form photoresist, inject N+ ion, in the P type epitaxial loayer in the first groove do not covered by grid layer and photoresist, form N+ source area;
Remove photoresist, grid layer makes dielectric layer, dielectric layer makes metal level.
Like this, can be made easily by said method and obtain superjunction semiconductor field.
The embodiment of the present invention also provides a kind of semiconductor device, and this device comprises employing said method and makes the superjunction semiconductor field obtained.
By this semiconductor device provided by the invention, owing to being adopt above-mentioned method to make to obtain, therefore, the manufacture craft of this semiconductor device is simple, and cost of manufacture is lower.
Accompanying drawing explanation
Fig. 1-Fig. 7 is respectively the structural representation that prior art makes the different phase of superjunction semiconductor field;
The manufacture method flow chart of a kind of superjunction semiconductor field that Fig. 8 provides for the embodiment of the present invention;
Fig. 9-Figure 19 is respectively the structural representation of the different phase of a kind of superjunction semiconductor field in manufacturing process that the embodiment of the present invention provides.
Embodiment
Embodiments provide a kind of manufacture method and semiconductor device of superjunction semiconductor field, in order to optimize Making programme, simplify manufacture craft, reduce cost of manufacture.
As shown in Figure 8, the specific embodiment of the invention provides a kind of manufacture method of superjunction semiconductor field, and described method comprises:
S101, on a semiconductor substrate making first conduction epitaxial loayer, the first conduction epitaxial loayer forms the first protective layer by patterning processes;
S102, etching do not have the first conduction epitaxial loayer of the first protective layer protection, form the first groove;
S103, in the Semiconductor substrate being formed with the first groove, make the second protective layer;
S104, etch the second protective layer, form the second protective layer side wall at the sidewall of the first groove;
S105, etching do not have the first conduction epitaxial loayer of the first protective layer and the second protective layer side wall protection, form the second groove;
S106, in the second groove make second conduction epitaxial loayer;
S107, remove the second protective layer side wall, in the first groove, make the second conduction epitaxial loayer;
Wherein, the degree of depth of described first groove is less than the degree of depth of described second groove; The material of described first protective layer is different with the material of described second protective layer.
The manufacture method of the superjunction semiconductor field that the specific embodiment of the invention provides is introduced in detail below in conjunction with accompanying drawing.
As shown in Figure 9, first the first conduction epitaxial loayer 111 is made on semiconductor substrate 110, first conduction epitaxial loayer 111 forms the first protective layer 112 by patterning processes, wherein, in the specific embodiment of the invention, Semiconductor substrate 110 is N type semiconductor substrate, first conduction epitaxial loayer 111 is N-type conduction epitaxial loayer, the material of the first protective layer 112 is silicon dioxide (SiO2), in the specific embodiment of the invention, the growth temperature of the first protective layer 112 is about 800 DEG C to 1100 DEG C, thickness is about 0.4 micron to 1.0 microns, certainly, according to needs of production, the growth temperature of the first protective layer and thickness can carry out suitable adjustment, the present invention does not do concrete restriction to it.The process that first conduction epitaxial loayer 111 forms the first protective layer 112 by patterning processes is; first on the first conduction epitaxial loayer 111, SiO2 film is deposited; the SiO2 film of deposition applies photoresist; and the photoresist of coating is exposed, developed; etching removes the SiO2 film not having photoresist to protect afterwards; and remove residue photoresist, form the first protective layer 112.The first groove 113 is etched afterwards on the first conduction epitaxial loayer 111 not having the first protective layer 112 to protect; in the specific embodiment of the invention, the etching of the first groove can be etched by plasma dry etch; the degree of depth of the first groove 113 etched is 1 micron to 5 microns; certainly can also carry out suitable adjustment according to the degree of depth of the need of production of reality to the first groove 113, the present invention does not do concrete restriction to it.
As shown in Figure 10; Semiconductor substrate shown in Fig. 9 makes the second protective layer 120; the material of the second protective layer 120 in the specific embodiment of the invention is silicon nitride (SiN); the growth temperature of SiN is about 700 DEG C to 1000 DEG C; thickness is about 0.1 micron to 0.5 micron, certainly, according to needs of production; the growth temperature of SiN and thickness can carry out suitable adjustment, and the present invention does not do concrete restriction to it.
As shown in figure 11; the second protective layer obtained is made in etching Figure 10; the second protective layer side wall is formed at the sidewall of the first groove 113; etched vertically downward by plasma dry etch in the specific embodiment of the invention; due in etching process; etching speed is vertically downward very fast; the etching speed of horizontal direction is slower; therefore when the second protective layer in vertical direction is etched away; still remain with part second protective layer in the side-walls of the first groove 113, this part second protective layer is the second protective layer side wall 130.
As shown in figure 12; etching does not have the first conduction epitaxial loayer of the first protective layer and the second protective layer side wall protection; form the second groove 140; in the specific embodiment of the invention; form the second groove 140 by plasma dry etch, wherein, in the specific embodiment of the invention, the degree of depth of the second groove 140 is 40 microns to 50 microns; certainly can also carry out suitable adjustment according to the degree of depth of the need of production of reality to the second groove 140, the present invention does not do concrete restriction to it.
As shown in figure 13, the second conduction epitaxial loayer 150 is made in the second groove 140, the second conduction epitaxial loayer 150 in the specific embodiment of the invention is P-type conduction epitaxial loayer, sidewall due to the second groove 140 is the first conduction epitaxial loayer 111, and the sidewall of the first groove 113 is the second protective layer SiN side wall, by the restriction of epitaxial growth technology condition, now the second conduction epitaxial loayer can only grow in the second groove 140, the second conduction epitaxial loayer can not be grown in first groove 113, now, first conduction epitaxial loayer 111 forms with the second conduction epitaxial loayer 150 the PN post be alternately connected, super-junction structure is formed in semiconductor substrate.
As shown in figure 14, remove the second protective layer side wall, particularly, the specific embodiment of the invention is by adopting hot phosphoric acid, the temperature of hot phosphoric acid is generally 180 DEG C, erosion removal second protective layer side wall, hot phosphoric acid only has the effect of corrosion to the second protective layer, the effect of corrosion is not had to the first protective layer and the first conduction epitaxial loayer and the second conduction epitaxial loayer, after the second protective layer side wall is corroded and gets rid of, the sidewall of the first groove 113 is the first conduction epitaxial loayer 111, the second conduction epitaxial loayer 150 is made in the first groove 113, as shown in figure 15, now, in first groove 113, the second conduction epitaxial loayer 150 of growth forms P type tagma.
As shown in figure 16; remove the first protective layer; manufacturing gate oxide layers 180 and grid layer 181 successively on the first conduction epitaxial loayer 111 and the second conduction epitaxial loayer 150; wherein grid layer 181 is polysilicon layer, and in the specific embodiment of the invention, the growth temperature of gate oxide 180 is about 800 DEG C to 1100 DEG C, and thickness is about 0.05 micron to 0.2 micron; certainly; according to needs of production, the growth temperature of gate oxide and thickness can carry out suitable adjustment, and the present invention does not do concrete restriction to it.In the specific embodiment of the invention, the growth temperature of grid layer 181 is about 500 DEG C to 700 DEG C, thickness is about 0.2 micron to 0.8 micron, certainly, according to needs of production, the growth temperature of grid layer and thickness can carry out suitable adjustment, and the present invention does not do concrete restriction to it.
As shown in figure 17, apply photoresist making on the grid layer that obtains, and expose photoresist, develop, etch away the grid layer not having photoresist to cover, formation covering first is conducted electricity epitaxial loayer and part second and is conducted electricity the grid layer 181 of epitaxial loayer.
As shown in figure 18, photoresist 200 is formed in the subregion do not covered by grid layer, inject N+ ion afterwards, N+ ion can not penetrate to be existed region that grid layer and photoresist cover and is injected in the region below it, and N+ ion can penetrate the region that do not have grid layer and photoresist to cover and be injected in the P type epitaxial loayer below it in the first groove, form N+ source area 201, it is phosphonium ion that N+ in the specific embodiment of the invention injects ion, and implantation dosage is 1.0E15 ~ 1.0E16/cm
2, Implantation Energy is 50Kev to 150Kev.
As shown in figure 19, grid layer 181 in figure 18 makes dielectric layer 210, the structure of the dielectric layer in the specific embodiment of the invention is plain SiO2 and phosphorosilicate glass, the thickness of plain SiO2 is 0.2 micron, the thickness of phosphorosilicate glass is 0.8 micron, certainly, the thickness of plain SiO2 and phosphorosilicate glass can carry out suitable adjustment according to needs of production, the present invention does not do concrete restriction to it, wherein, the concrete manufacture method of dielectric layer is same as the prior art, does not repeat here.Dielectric layer 210 makes metal level 211, the thickness of the metal level 211 in the specific embodiment of the invention is 2 microns to 5 microns, and the material of metal level 211 is aluminium or the alloy for aluminium, silicon, copper, wherein, the concrete manufacture method of metal level is same as the prior art, does not repeat here.
In sum, the specific embodiment of the invention is optimized the technological process making superjunction semiconductor field, when etching groove, first etch shallow trench, then produce silicon nitride spacer, then side wall is utilized to carry out the etching of deep trench, growing P-type extension in deep trench, then remove silicon nitride spacer, regrowth P type extension, self-assembling formation P type tagma, eliminates the injection in P type tagma and drives in.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. a manufacture method for superjunction semiconductor field, is characterized in that, described method comprises:
Make the first conduction epitaxial loayer on a semiconductor substrate, the first conduction epitaxial loayer forms the first protective layer by patterning processes;
Etching does not have the first conduction epitaxial loayer of the first protective layer protection, forms the first groove;
The Semiconductor substrate being formed with the first groove makes the second protective layer;
Etch the second protective layer, form the second protective layer side wall at the sidewall of the first groove;
Etching does not have the first conduction epitaxial loayer of the first protective layer and the second protective layer side wall protection, forms the second groove;
The second conduction epitaxial loayer is made in the second groove;
Remove the second protective layer side wall, in the first groove, make the second conduction epitaxial loayer;
Wherein, the degree of depth of described first groove is less than the degree of depth of described second groove; The material of described first protective layer is different with the material of described second protective layer.
2. method according to claim 1, is characterized in that, described Semiconductor substrate is N type semiconductor substrate, and described first conduction epitaxial loayer is N-type conduction epitaxial loayer, and described second conduction epitaxial loayer is P-type conduction epitaxial loayer.
3. method according to claim 1, is characterized in that, the degree of depth of described first groove is 1 micron to 5 microns.
4. method according to claim 1, is characterized in that, the degree of depth of described second groove is 40 microns to 50 microns.
5. method according to claim 1, is characterized in that, the material of described first protective layer is silicon dioxide.
6. method according to claim 1, is characterized in that, the material of described second protective layer is silicon nitride.
7. method according to claim 1, is characterized in that, described removal second protective layer side wall, comprising: adopt hot phosphoric acid, erosion removal second protective layer side wall.
8. method according to claim 1, is characterized in that, described first conduction epitaxial loayer on form the first protective layer by patterning processes, comprising:
First conduction epitaxial loayer deposits the first protective layer;
Described first protective layer applies photoresist, and photoresist is exposed, develops;
Etching removes the first protective layer not having photoresist to protect, and removes residue photoresist, forms the first protective layer.
9. method according to claim 1, is characterized in that, make the second conduction epitaxial loayer in the first groove after, described method also comprises:
Remove the first protective layer, manufacturing gate oxide layers and grid layer successively on described first conduction epitaxial loayer and the second conduction epitaxial loayer, wherein, described gate oxide covers the first conduction epitaxial loayer and the second conduction epitaxial loayer, and described grid layer covers the first conduction epitaxial loayer and part second and conducts electricity epitaxial loayer;
In the subregion do not covered by grid layer, form photoresist, inject N+ ion, in the P type epitaxial loayer in the first groove do not covered by grid layer and photoresist, form N+ source area;
Remove photoresist, grid layer makes dielectric layer, dielectric layer makes metal level.
10. a semiconductor device, is characterized in that, described device comprises the arbitrary claim of employing claim 1-9 and makes the superjunction semiconductor field obtained.
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| CN201410383910.2A CN105448722B (en) | 2014-08-06 | 2014-08-06 | A kind of production method and semiconductor device of superjunction semiconductor field |
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| CN201410383910.2A CN105448722B (en) | 2014-08-06 | 2014-08-06 | A kind of production method and semiconductor device of superjunction semiconductor field |
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| CN105448722B CN105448722B (en) | 2019-02-01 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024898A (en) * | 2016-07-12 | 2016-10-12 | 杭州士兰集成电路有限公司 | Trench power device and manufacturing method |
| CN116646252A (en) * | 2023-07-27 | 2023-08-25 | 北京智芯微电子科技有限公司 | Super junction device manufacturing method, super junction device, chip and circuit |
| CN117080078A (en) * | 2023-10-17 | 2023-11-17 | 深圳基本半导体有限公司 | Method for preparing MOS device based on composite film layer self-alignment process and device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8003522B2 (en) * | 2007-12-19 | 2011-08-23 | Fairchild Semiconductor Corporation | Method for forming trenches with wide upper portion and narrow lower portion |
| CN103367157B (en) * | 2012-04-06 | 2015-12-09 | 北大方正集团有限公司 | A kind of preparation method of super node MOSFET |
| CN103579003B (en) * | 2012-08-09 | 2016-02-03 | 北大方正集团有限公司 | A kind of method making super node MOSFET |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024898A (en) * | 2016-07-12 | 2016-10-12 | 杭州士兰集成电路有限公司 | Trench power device and manufacturing method |
| CN106024898B (en) * | 2016-07-12 | 2023-04-18 | 杭州士兰集成电路有限公司 | Groove power device and manufacturing method |
| CN116646252A (en) * | 2023-07-27 | 2023-08-25 | 北京智芯微电子科技有限公司 | Super junction device manufacturing method, super junction device, chip and circuit |
| CN117080078A (en) * | 2023-10-17 | 2023-11-17 | 深圳基本半导体有限公司 | Method for preparing MOS device based on composite film layer self-alignment process and device |
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