CN103928346B - It is epitaxially-formed the UMOSFET device preparation method of N-type heavy doping drift layer table top - Google Patents
It is epitaxially-formed the UMOSFET device preparation method of N-type heavy doping drift layer table top Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
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Abstract
The present invention relates to a kind of UMOSFET device preparation method being epitaxially-formed N-type heavy doping drift layer table top, epitaxial growth N-type drift region；It is epitaxially-formed the N+ drift layer of table top；N+ drift layer etching is table top；Epitaxial growth P epitaxial layer；Epitaxial growth N+ source region layer；Etching grooving；Etching forms source region；Oxidation forms groove grid；Depositing polysilicon；Opening contact hole: prepare passivation layer, opens electrode contact hole；Prepare electrode: evaporated metal, prepare electrode.The present invention improves the doping content of N-type drift region table top in the carborundum UMOSFET device with N drift layer table top by epitaxial growth and etching technics, reduces the conducting resistance of this device.
Description
Technical field
The present invention relates to microelectronics technology, particularly relate to one and be epitaxially-formed N-type heavy doping
The UMOSFET device preparation method of drift layer table top.
Background technology
Third generation semiconductor material with wide forbidden band carborundum has broad-band gap, high critical breakdown electric field, high electricity
Excellent physics and the chemical property such as sub-saturation drift velocity and higher thermal conductivity, at high temperature, high pressure,
In the application of large power semiconductor device, tool has great advantage.
Power MOSFET is as switch, and its forward conduction resistance and breakdown reverse voltage are that conflict closes
System, and the UMOSFET of vertical structure eliminates parasitic accumulation layer resistance and JFET resistance, so
UMOSFET compares with the MOSFET of transversary in this respect has certain advantage.
UMOSFET self there is also shortcoming, and the electric field concentration effect of its Cao Shan corner causes device in advance
Puncture, reduce the reliability of device.A kind of can reduce groove grid turning electric field with N-type
The carborundum UMOSFET device of drift layer table top, through being developed, the P-epitaxial layer parcel of this device
Groove grid turnings, instead of the SiO at turning with SiC PN junction interface2/ SiC bears at interface reverse electricity
Pressure, improves the reliability of device.
But owing in the program, P-epitaxial layer has wrapped up groove grid turning, make conductive path become at table top
Narrow, and impurity concentration and the drift layer concentration at table top is equal, and doping content is relatively low, and this is all right
The disadvantageous factor of conducting resistance.
In view of drawbacks described above, creator of the present invention obtains this finally through research for a long time and practice
Creation.
Summary of the invention
It is an object of the invention to provide a kind of N-type heavy doping drift layer table top of being epitaxially-formed
UMOSFET device preparation method, in order to overcome above-mentioned technological deficiency.
For achieving the above object, the present invention provides one to be epitaxially-formed N-type heavy doping drift layer platform
The UMOSFET device preparation method in face, this detailed process is:
Step a, epitaxial growth N-type drift region: at silicon carbide N+substrate print Epitaxial growth thickness about
Being 10 μm～20 μm, Nitrogen ion doping content is 1 × 1015cm-3～5 × 1015cm-3N-type drift region；
Step b, is epitaxially-formed the N+ drift layer of table top: epitaxial growth on N-type drift region
One layer of heavily doped N+ drift layer, thickness is 1 μm～2 μm, Nitrogen ion doping content is 1 ×
1017cm-3～5 × 1017cm-3；
Step c, N+ drift layer etching is for table top: N+ drift layer is etched into a table top, table surface height
With the deep equality of N+ drift layer, mesa width is 3 μm～4 μm；
Step d, epitaxial growth P-epitaxial layer: grow in N-type drift region and N+ drift layer table top
Layer P-epitaxial layer, thickness is 3 μm, and Al-doping concentration is 5 × 1017cm-3～1 × 1018cm-3；
Step e, epitaxial growth N+ source region layer: grow one layer of N+ source region layer, thickness on P-epitaxial layer
Being 0.5 μm, doping content is 5 × 1018cm-3；
Step f, etches grooving: use ICP etching to be formed directly over N-type heavy doping drift layer table top
Groove, width is 6 μm, and the degree of depth is 3 μm, and two base angles of such groove are wrapped up by P-epitaxial layer；
Step g, etching forms source region: use ICP etching to form source contact；
Step h, oxidation forms groove grid: by thermal oxidation technology preparation vessel gate medium SiO2, thickness is
100nm；
Step i, depositing polysilicon: the groove gate medium SiO in groove grid2Upper deposit polySi layer；
Step j, opening contact hole: prepare passivation layer, open electrode contact hole；
Step k, prepares electrode: evaporated metal, prepares electrode.
Further, in above-mentioned steps a, first to carry out RCA standard clear for the silicon carbide substrates sheet to N-type
Wash, be then 10 μm～20 μm at whole substrate slice Epitaxial growth thickness, Nitrogen ion doping content
It is 1 × 1015cm-3～5 × 1015cm-3N-drift layer, its process conditions are: temperature is 1600 DEG C, pressure
Power is 100mbar, and reacting gas uses silane and propane, and carrier gas uses pure hydrogen, doped source
Use liquid nitrogen.
Further, in above-mentioned steps b,
Being epitaxially-formed the N+ drift layer of table top, thickness is 1～2 μm, and Nitrogen ion doping content is
1×1017cm-3～5 × 1017cm-3, its process conditions are: temperature is 1600 DEG C, and pressure is 100mbar,
Reacting gas uses silane and propane.
Further, in above-mentioned steps c, process conditions are: ICP coil power 850W, source power
100W, reacting gas SF6And O2It is respectively 48sccm and 12sccm.
Further, in above-mentioned steps d, N-type drift region and N+ drift layer table top grow one layer of P-
Epitaxial layer, thickness is 3 μm, and Al-doping concentration is 5 × 1017cm-3～1 × 1018cm-3；Its technique
Condition be temperature be 1600 DEG C, pressure is 100mbar, and reacting gas uses silane and propane, carrying
Gas uses pure hydrogen, and doped source uses trimethyl aluminium..
Further, in above-mentioned steps e, growing a layer thickness on P-epitaxial layer is 0.5 μm, nitrogen
Ion doping concentration is 5 × 1018cm-3N-type silicon carbide epitaxial layers, as N+ source region layer, its technique
Condition is: temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas uses silane and propane, carries
Fortune body uses pure hydrogen, and doped source uses liquid nitrogen.
Further, in above-mentioned steps f, first magnetron sputtering one layerTi film as ICP
Etch mask, then gluing photoetching, carry out ICP etching, and the width etching groove is 6 μm, the degree of depth
It is 3 μm, finally removes photoresist, go etch mask, clean into mating plate；Process conditions are: ICP coil merit
Rate 850W, source power 100W, reacting gas SF6And O2It is respectively 48sccm and 12sccm.
Further, in above-mentioned steps g, first magnetron sputtering one layerTi film as ICP
Etch mask, then gluing photoetching, carry out ICP etching, forms source contact hole, finally removes photoresist,
Go etch mask, clean into mating plate；Process conditions are: ICP coil power 850W, source power 100W,
Reacting gas SF6And O2It is respectively 48sccm and 12sccm.
Further, in above-mentioned steps h, dry oxygen technique is used to prepare SiO at 1150 DEG C2Grid are thick
Degree is 100nm, then at 1050 DEG C, N2Anneal under atmosphere, reduce SiO2Film surface thick
Rugosity.
Further, in above-mentioned steps i, use low pressure hot wall chemical vapor deposition method growth ploySi
Filling up groove, deposition temperature is 600～650 DEG C, and deposit pressure is 60～80Pa, and reacting gas is silicon
Alkane and hydrogen phosphide, carrier gas is helium, then gluing photoetching, etches ploySi layer, forms polycrystalline
Si-gate, finally removes photoresist, and cleans.
The beneficial effects of the present invention is compared with prior art: the present invention passes through epitaxial growth and quarter
Etching technique improves the N-type drift region platform in the carborundum UMOSFET device with N-drift layer table top
The doping content in face, reduces the conducting resistance of this device.Epitaxial growth (CVD) technology is used to be formed
The N+ drift layer of table top, it is possible to form the thin film of high uniformity；Additionally epitaxial growth can avoid ion
High-temperature annealing activation process after injection and ion implanting, thus reduce the crystalline substance brought by ion implanting
Lattice damage.
Accompanying drawing explanation
Fig. 1 is the present invention structural representation with the carborundum UMOSFET device of N-type drift layer table top
Figure；
Fig. 2 is the present invention processing technology with the carborundum UMOSFET device of N-type drift layer table top
Flow chart.
Detailed description of the invention
Below in conjunction with accompanying drawing, to the present invention, above-mentioned and other technical characteristic and advantage are made more detailed
Explanation.
Referring to shown in Fig. 2, it is the present invention carborundum UMOSFET with N-type drift layer table top
The structural representation of device, this detailed process is:
Step a, epitaxial growth N-type drift region: at silicon carbide N+substrate print Epitaxial growth thickness about
Being 10 μm～20 μm, Nitrogen ion doping content is 1 × 1015cm-3～5 × 1015cm-3N-type drift region；
Step b, is epitaxially-formed the N+ drift layer of table top: epitaxial growth on N-type drift region
One layer of heavily doped N+ drift layer, thickness is 1 μm～2 μm, Nitrogen ion doping content is 1 ×
1017cm-3～5 × 1017cm-3；Being epitaxially-formed the N+ drift layer of table top, thickness is 1～2 μm, nitrogen
Ion doping concentration is 1 × 1017cm-3～5 × 1017cm-3, its process conditions are: temperature is 1600 DEG C,
Pressure is 100mbar, and reacting gas uses silane and propane；
Step c, N+ drift layer etching is for table top: N+ drift layer is etched into a table top, table surface height
With the deep equality of N+ drift layer, mesa width is 3 μm～4 μm；Its process conditions are: ICP line
Circle power 850W, source power 100W, reacting gas SF6And O2It is respectively 48sccm and 12sccm.
Step d, epitaxial growth P-epitaxial layer: grow in N-type drift region and N+ drift layer table top
Layer P-epitaxial layer, thickness is 3 μm, and Al-doping concentration is 5 × 1017cm-3～1 × 1018cm-3；
Step e, epitaxial growth N+ source region layer: grow one layer of N+ source region layer, thickness on P-epitaxial layer
Being 0.5 μm, doping content is 5 × 1018cm-3；
Step f, etches grooving: use ICP etching to be formed directly over N-type heavy doping drift layer table top
Groove, width is 6 μm, and the degree of depth is 3 μm, and two base angles of such groove are wrapped up by P-epitaxial layer；
Step g, etching forms source region: use ICP etching to form source contact；
Step h, oxidation forms groove grid: by thermal oxidation technology preparation vessel gate medium SiO2, thickness is
100nm；
Step i, depositing polysilicon: the groove gate medium SiO in groove grid2Upper deposit polySi layer；
Step j, opening contact hole: prepare passivation layer, open electrode contact hole；
Step k, prepares electrode: evaporated metal, prepares electrode.
Each embodiment based on above-mentioned steps, as described below:
Embodiment one:
Step a1, epitaxial growth N-type drift region, as shown in a in Fig. 2；
First the silicon carbide substrates sheet to N-type carries out RCA standard cleaning, then on whole substrate slice outside
Epitaxial growth thickness is 10 μm, and Nitrogen ion doping content is 1 × 1015cm-3N-drift layer, its technique
Condition is: temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas uses silane and propane, carries
Fortune body uses pure hydrogen, and doped source uses liquid nitrogen.
Step b1, is epitaxially-formed the N+ drift layer of table top, as shown in the b in Fig. 2；
Growing the N+ drift layer of 1 μ m-thick on N-drift layer, Nitrogen ion doping content is
1×1017cm-3, its process conditions are: temperature is 1600 DEG C, and pressure is 100mbar, reacting gas
Using silane and propane, carrier gas uses pure hydrogen, and doped source uses liquid nitrogen.
Step c1, N+ drift layer etching forms table top, as shown in the c in Fig. 2；
First magnetron sputtering one layerTi film as ICP etch mask, then gluing photoetching,
Carrying out ICP etching, N+ trap is etched into mesa structure, table surface height is equal to N+ well depth mesa width
It is 3 μm.Finally remove photoresist, go etch mask, clean into mating plate.ICP etch technological condition is: ICP
Coil power 850W, source power 100W, reacting gas SF6And O2It is respectively 48sccm and 12sccm.
Step d1, epitaxial growth P-epitaxial layer, as shown in the d in Fig. 2；
Growing a layer thickness in N-type drift region and heavily doped drift region mesa is 3 μm, aluminium ion
Doping content is 5 × 1017cm-3P-epitaxial layer, its epitaxial growth technology condition is: temperature is 1600
DEG C, pressure is 100mbar, and reacting gas uses silane and propane, and carrier gas uses pure hydrogen,
Doped source uses trimethyl aluminium.
Step e1, epitaxial growth N+ source region layer, as shown in the e in Fig. 2；
Growing a layer thickness on P-epitaxial layer is 0.5 μm, and Nitrogen ion doping content is 5 × 1018cm-3
N-type silicon carbide epitaxial layers, as N+ source region layer, its process conditions are: temperature is 1600 DEG C, pressure
Power is 100mbar, and reacting gas uses silane and propane, and carrier gas uses pure hydrogen, doped source
Use liquid nitrogen.
Step f1, etches grooving, as shown in the f in Fig. 2；
First magnetron sputtering one layerTi film as ICP etch mask, then gluing photoetching,
Carrying out ICP etching, the width etching groove is 6 μm, and the degree of depth is 3 μm, finally removes photoresist, and goes etching
Mask, cleans into mating plate.Process conditions are: ICP coil power 850W, source power 100W, reaction
Gas SF6And O2It is respectively 48sccm and 12sccm.
Step g1, etching forms source region, as shown in the g in Fig. 2；
First magnetron sputtering one layerTi film as ICP etch mask, then gluing photoetching,
Carry out ICP etching, form source contact hole, finally remove photoresist, go etch mask, clean into mating plate.
Process conditions are: ICP coil power 850W, source power 100W, reacting gas SF6And O2It is respectively
48sccm and 12sccm.
Step h1, oxidation forms groove grid, as shown in the h in Fig. 2；
Dry oxygen technique is used to prepare SiO at 1150 DEG C2Grid, thickness is 100nm, then 1050
DEG C, N2Anneal under atmosphere, reduce SiO2The roughness of film surface.
Step i1, depositing polysilicon, as shown in the i in Fig. 2；
Using low pressure hot wall chemical vapor deposition method growth ploySi to fill up groove, deposition temperature is
600～650 DEG C, deposit pressure is 60～80Pa, and reacting gas is silane and hydrogen phosphide, and carrier gas is
Helium, then gluing photoetching, etch ploySi layer, forms polysilicon gate, finally removes photoresist, and cleans.
Step j1, opening contact hole, as shown in the j in Fig. 2；
At device surface one layer of field oxygen of deposit or Si3N4Layer, then gluing photoetching, corrosion and passivation layer is opened
Electrode contact hole, finally removes photoresist, and cleans.
Step k1, prepares electrode, as shown in the k in Fig. 2；
Electron beam evaporation Ti/Ni/Au makes front grid, source electrode, then gluing photoetching, metal erosion
Form front grid, source electrode contact pattern, remove photoresist, clean.
Electron beam evaporation Ti/Ni/Au makes back side drain electrode overleaf, then makes front grid, source electricity
Pole, encloses short annealing 3min the most in an ar atmosphere, and temperature is 1050 DEG C.
Embodiment two:
Step a2, epitaxial growth N-type drift region；
First the silicon carbide substrates sheet to N-type carries out RCA standard cleaning, then on whole substrate slice outside
Epitaxial growth thickness is 20 μm, and Nitrogen ion doping content is 5 × 1015cm-3N-drift layer, its technique
Condition is: temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas uses silane and propane, carries
Fortune body uses pure hydrogen, and doped source uses liquid nitrogen.
Step b2, is epitaxially-formed the N+ drift layer of table top；
Growing the N+ drift layer of 2 μ m-thick on N-drift layer, Nitrogen ion doping content is
5×1017cm-3, its process conditions are: temperature is 1600 DEG C, and pressure is 100mbar, reacting gas
Using silane and propane, carrier gas uses pure hydrogen, and doped source uses liquid nitrogen.
Step c2, N+ drift layer etching forms table top；
First magnetron sputtering one layerTi film as ICP etch mask, then gluing photoetching,
Carrying out ICP etching, N+ drift layer is etched into mesa structure, table surface height is equal to N+ drift thickness
Degree, mesa width is 4 μm.Finally remove photoresist, go etch mask, clean into mating plate.ICP etches work
Skill condition is: ICP coil power 850W, source power 100W, reacting gas SF6And O2It is respectively
48sccm and 12sccm.
Step d2, epitaxial growth P-epitaxial layer；
Growing a layer thickness in N-type drift region and heavily doped drift region mesa is 3 μm, aluminium ion
Doping content is 1 × 1018cm-3P-epitaxial layer, its epitaxial growth technology condition is: temperature is 1600
DEG C, pressure is 100mbar, and reacting gas uses silane and propane, and carrier gas uses pure hydrogen,
Doped source uses trimethyl aluminium.
Step e2 is identical with step e1 of embodiment one.
Step f2 is identical with step f1 of embodiment one.
Step g2 is identical with step g1 of embodiment one.
Step h2 is identical with step h1 of embodiment one.
Step i2 is identical with step i1 of embodiment one.
Step j2 is identical with step j1 of embodiment one.
Step k2 is identical with step k1 of embodiment one.
Embodiment three:
Step a3, epitaxial growth N-type drift region；
First the silicon carbide substrates sheet to N-type carries out RCA standard cleaning, then on whole substrate slice outside
Epitaxial growth thickness is 15 μm, and Nitrogen ion doping content is 3 × 1015cm-3N-drift layer, its technique
Condition is: temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas uses silane and propane, carries
Fortune body uses pure hydrogen, and doped source uses liquid nitrogen.
Step b3, is epitaxially-formed the N+ drift layer of table top；
Growing the N+ drift layer of 1.5 μ m-thick on N-drift layer, Nitrogen ion doping content is
3×1017cm-3, its process conditions are: temperature is 1600 DEG C, and pressure is 100mbar, reacting gas
Using silane and propane, carrier gas uses pure hydrogen, and doped source uses liquid nitrogen.
Step c3, N+ drift layer etching forms table top；
First magnetron sputtering one layerTi film as ICP etch mask, then gluing photoetching,
Carrying out ICP etching, N+ drift layer is etched into mesa structure, table surface height is equal to N+ drift thickness
Degree, mesa width is 3.5 μm.Finally remove photoresist, go etch mask, clean into mating plate.ICP etches
Process conditions are: ICP coil power 850W, source power 100W, reacting gas SF6And O2Respectively
For 48sccm and 12sccm.
Step d3, epitaxial growth P-epitaxial layer；
Growing a layer thickness in N-type drift region and heavily doped drift region mesa is 3 μm, aluminium ion
Doping content is 8 × 1017cm-3P-epitaxial layer, its epitaxial growth technology condition is: temperature is 1600
DEG C, pressure is 100mbar, and reacting gas uses silane and propane, and carrier gas uses pure hydrogen,
Doped source uses trimethyl aluminium.
Step e3 is identical with step e1 of embodiment one.
Step f3 is identical with step f1 of embodiment one.
Step g3 is identical with step g1 of embodiment one.
Step h3 is identical with step h1 of embodiment one.
Step i3 is identical with step i1 of embodiment one.
Step j3 is identical with step j1 of embodiment one.
Step k3 is identical with step k1 of embodiment one.
The foregoing is only presently preferred embodiments of the present invention, be merely illustrative for invention, and
Nonrestrictive.Those skilled in the art understands, in the spirit and scope that invention claim is limited
In it can be carried out many changes, amendment, even equivalence, but fall within protection scope of the present invention
In.
Claims (10)
1. the UMOSFET device preparation method being epitaxially-formed N-type heavy doping drift layer table top, it is characterised in that this preparation method is:
Step a, epitaxial growth N-type drift region: be 10 μm～20 μm at silicon carbide N+substrate print Epitaxial growth thickness, Nitrogen ion doping content is 1 × 1015cm-3～5 × 1015cm-3N-type drift region；
Step b, is epitaxially-formed the N+ drift layer of table top: the heavily doped N+ drift layer of epitaxial growth one layer on N-type drift region, thickness is 1 μm～2 μm, and Nitrogen ion doping content is 1 × 1017cm-3～5 × 1017cm-3；
Step c, N+ drift layer etching is for table top: N+ drift layer is etched into a table top, table surface height and the deep equality of N+ drift layer, and mesa width is 3 μm～4 μm；
Step d, epitaxial growth P-epitaxial layer: growing one layer of P-epitaxial layer in N-type drift region and N+ drift layer table top, thickness is 3 μm, and Al-doping concentration is 5 × 1017cm-3～1 × 1018cm-3；
Step e, epitaxial growth N+ source region layer: growing one layer of N+ source region layer on P-epitaxial layer, thickness is 0.5 μm, and doping content is 5 × 1018cm-3；
Step f, etches grooving: using ICP etching to form groove directly over N-type heavy doping drift layer table top, width is 6 μm, and the degree of depth is 3 μm, and two base angles of such groove are wrapped up by P-epitaxial layer；
Step g, etching forms source region: use ICP etching to form source contact；
Step h, oxidation forms groove grid: by thermal oxidation technology preparation vessel gate medium SiO2, thickness is 100nm；
Step i, depositing polysilicon: the groove gate medium SiO in groove grid2Upper deposit polySi layer；
Step j, opening contact hole: prepare passivation layer, open electrode contact hole；
Step k, prepares electrode: evaporated metal, prepares electrode.
The UMOSFET device preparation method being epitaxially-formed N-type heavy doping drift layer table top the most according to claim 1, it is characterized in that, in above-mentioned steps a, first the silicon carbide substrates sheet of N-type is carried out RCA standard cleaning, then being 10 μm～20 μm at whole substrate slice Epitaxial growth thickness, Nitrogen ion doping content is 1 × 1015cm-3～5 × 1015cm-3N-drift layer, its process conditions are: temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas uses silane and propane, and carrier gas uses pure hydrogen, and doped source uses liquid nitrogen.
The UMOSFET device preparation method being epitaxially-formed N-type heavy doping drift layer table top the most according to claim 1 and 2, it is characterised in that in above-mentioned steps b,
Being epitaxially-formed the N+ drift layer of table top, thickness is 1～2 μm, and Nitrogen ion doping content is 1 × 1017cm-3～5 × 1017cm-3, its process conditions are: temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas uses silane and propane.
The UMOSFET device preparation method being epitaxially-formed N-type heavy doping drift layer table top the most according to claim 3, it is characterised in that in above-mentioned steps c, process conditions are: ICP coil power 850W, source power 100W, reacting gas SF6And O2It is respectively 48sccm and 12sccm.
The UMOSFET device preparation method being epitaxially-formed N-type heavy doping drift layer table top the most according to claim 3, it is characterized in that, in above-mentioned steps d, N-type drift region and N+ drift layer table top grow one layer of P-epitaxial layer, thickness is 3 μm, and Al-doping concentration is 5 × 1017cm-3～1 × 1018cm-3；Its process conditions be temperature be 1600 DEG C, pressure is 100mbar, and reacting gas uses silane and propane, and carrier gas uses pure hydrogen, and doped source uses trimethyl aluminium.
The UMOSFET device preparation method being epitaxially-formed N-type heavy doping drift layer table top the most according to claim 3, it is characterised in that in above-mentioned steps e, growing a layer thickness on P-epitaxial layer is 0.5 μm, and Nitrogen ion doping content is 5 × 1018cm-3N-type silicon carbide epitaxial layers, as N+ source region layer, its process conditions are: temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas uses silane and propane, and carrier gas uses pure hydrogen, and doped source uses liquid nitrogen.
The UMOSFET device preparation method being epitaxially-formed N-type heavy doping drift layer table top the most according to claim 6, it is characterised in that in above-mentioned steps f, first magnetron sputtering one layerTi film as ICP etch mask, then gluing photoetching, carry out ICP etching, the width etching groove is 6 μm, and the degree of depth is 3 μm, finally removes photoresist, goes etch mask, cleans into mating plate；Process conditions are: ICP coil power 850W, source power 100W, reacting gas SF6And O2It is respectively 48sccm and 12sccm.
The UMOSFET device preparation method being epitaxially-formed N-type heavy doping drift layer table top the most according to claim 6, it is characterised in that in above-mentioned steps g, first magnetron sputtering one layerTi film as ICP etch mask, then gluing photoetching, carry out ICP etching, form source contact hole, finally remove photoresist, go etch mask, clean into mating plate；Process conditions are: ICP coil power 850W, source power 100W, reacting gas SF6And O2It is respectively 48sccm and 12sccm.
The UMOSFET device preparation method being epitaxially-formed N-type heavy doping drift layer table top the most according to claim 8, it is characterised in that in above-mentioned steps h, uses dry oxygen technique to prepare SiO at 1150 DEG C2Grid, thickness is 100nm, then at 1050 DEG C, N2Anneal under atmosphere, reduce SiO2The roughness of film surface.
The UMOSFET device preparation method being epitaxially-formed N-type heavy doping drift layer table top the most according to claim 8, it is characterised in that in above-mentioned steps i, low pressure hot wall chemical vapor deposition method growth ploySi is used to fill up groove, deposition temperature is 600～650 DEG C, and deposit pressure is 60～80Pa, and reacting gas is silane and hydrogen phosphide, carrier gas is helium, then gluing photoetching, etches ploySi layer, forms polysilicon gate, finally remove photoresist, clean.
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